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authorChristian König <christian.koenig@amd.com>2013-08-13 05:56:50 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-08-30 16:30:39 -0400
commit76a0df859defc53e6cb61f698a48ac7da92c8d84 (patch)
tree7882f906bd5bb67bd95088bc853117295a85a48d /drivers/gpu/drm
parent4543eda52113d1e2cc0e9bf416f79597e6ef1ec7 (diff)
drm/radeon: rework ring function handling
Give the ring functions a separate structure and let the asic structure point to the ring specific functions. This simplifies the code and allows us to make changes at only one point. No change in functionality. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h72
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c1026
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c2
3 files changed, 313 insertions, 787 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5e21dbeaf314..b26a20fe2859 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1578,6 +1578,34 @@ int radeon_debugfs_add_files(struct radeon_device *rdev,
1578 unsigned nfiles); 1578 unsigned nfiles);
1579int radeon_debugfs_fence_init(struct radeon_device *rdev); 1579int radeon_debugfs_fence_init(struct radeon_device *rdev);
1580 1580
1581/*
1582 * ASIC ring specific functions.
1583 */
1584struct radeon_asic_ring {
1585 /* ring read/write ptr handling */
1586 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1587 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1588 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1589
1590 /* validating and patching of IBs */
1591 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1592 int (*cs_parse)(struct radeon_cs_parser *p);
1593
1594 /* command emmit functions */
1595 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1596 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1597 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1598 struct radeon_semaphore *semaphore, bool emit_wait);
1599 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1600
1601 /* testing functions */
1602 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1603 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1604 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1605
1606 /* deprecated */
1607 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1608};
1581 1609
1582/* 1610/*
1583 * ASIC specific functions. 1611 * ASIC specific functions.
@@ -1621,23 +1649,7 @@ struct radeon_asic {
1621 uint32_t incr, uint32_t flags); 1649 uint32_t incr, uint32_t flags);
1622 } vm; 1650 } vm;
1623 /* ring specific callbacks */ 1651 /* ring specific callbacks */
1624 struct { 1652 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1625 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1626 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1627 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1628 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1629 struct radeon_semaphore *semaphore, bool emit_wait);
1630 int (*cs_parse)(struct radeon_cs_parser *p);
1631 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1632 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1633 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1634 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1635 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1636
1637 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1638 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1639 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1640 } ring[RADEON_NUM_RINGS];
1641 /* irqs */ 1653 /* irqs */
1642 struct { 1654 struct {
1643 int (*set)(struct radeon_device *rdev); 1655 int (*set)(struct radeon_device *rdev);
@@ -2442,7 +2454,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2442#define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2454#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2443#define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2455#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2444#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2456#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2445#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 2457#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2446#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2458#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2447#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2459#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2448#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2460#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
@@ -2450,16 +2462,16 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2450#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2462#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2451#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2463#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2452#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2464#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2453#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 2465#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2454#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 2466#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2455#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 2467#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2456#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 2468#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2457#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 2469#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2458#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 2470#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2459#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 2471#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2460#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r)) 2472#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2461#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r)) 2473#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2462#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r)) 2474#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2463#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2475#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2464#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2476#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2465#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2477#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
@@ -2467,8 +2479,8 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2467#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2479#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2468#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2480#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2469#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2481#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2470#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 2482#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2471#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2483#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2472#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 2484#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2473#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 2485#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2474#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 2486#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 61c06449b31a..012fe7218c74 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -172,6 +172,21 @@ void radeon_agp_disable(struct radeon_device *rdev)
172/* 172/*
173 * ASIC 173 * ASIC
174 */ 174 */
175
176static struct radeon_asic_ring r100_gfx_ring = {
177 .ib_execute = &r100_ring_ib_execute,
178 .emit_fence = &r100_fence_ring_emit,
179 .emit_semaphore = &r100_semaphore_ring_emit,
180 .cs_parse = &r100_cs_parse,
181 .ring_start = &r100_ring_start,
182 .ring_test = &r100_ring_test,
183 .ib_test = &r100_ib_test,
184 .is_lockup = &r100_gpu_is_lockup,
185 .get_rptr = &radeon_ring_generic_get_rptr,
186 .get_wptr = &radeon_ring_generic_get_wptr,
187 .set_wptr = &radeon_ring_generic_set_wptr,
188};
189
175static struct radeon_asic r100_asic = { 190static struct radeon_asic r100_asic = {
176 .init = &r100_init, 191 .init = &r100_init,
177 .fini = &r100_fini, 192 .fini = &r100_fini,
@@ -187,19 +202,7 @@ static struct radeon_asic r100_asic = {
187 .set_page = &r100_pci_gart_set_page, 202 .set_page = &r100_pci_gart_set_page,
188 }, 203 },
189 .ring = { 204 .ring = {
190 [RADEON_RING_TYPE_GFX_INDEX] = { 205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
191 .ib_execute = &r100_ring_ib_execute,
192 .emit_fence = &r100_fence_ring_emit,
193 .emit_semaphore = &r100_semaphore_ring_emit,
194 .cs_parse = &r100_cs_parse,
195 .ring_start = &r100_ring_start,
196 .ring_test = &r100_ring_test,
197 .ib_test = &r100_ib_test,
198 .is_lockup = &r100_gpu_is_lockup,
199 .get_rptr = &radeon_ring_generic_get_rptr,
200 .get_wptr = &radeon_ring_generic_get_wptr,
201 .set_wptr = &radeon_ring_generic_set_wptr,
202 }
203 }, 206 },
204 .irq = { 207 .irq = {
205 .set = &r100_irq_set, 208 .set = &r100_irq_set,
@@ -266,19 +269,7 @@ static struct radeon_asic r200_asic = {
266 .set_page = &r100_pci_gart_set_page, 269 .set_page = &r100_pci_gart_set_page,
267 }, 270 },
268 .ring = { 271 .ring = {
269 [RADEON_RING_TYPE_GFX_INDEX] = { 272 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
270 .ib_execute = &r100_ring_ib_execute,
271 .emit_fence = &r100_fence_ring_emit,
272 .emit_semaphore = &r100_semaphore_ring_emit,
273 .cs_parse = &r100_cs_parse,
274 .ring_start = &r100_ring_start,
275 .ring_test = &r100_ring_test,
276 .ib_test = &r100_ib_test,
277 .is_lockup = &r100_gpu_is_lockup,
278 .get_rptr = &radeon_ring_generic_get_rptr,
279 .get_wptr = &radeon_ring_generic_get_wptr,
280 .set_wptr = &radeon_ring_generic_set_wptr,
281 }
282 }, 273 },
283 .irq = { 274 .irq = {
284 .set = &r100_irq_set, 275 .set = &r100_irq_set,
@@ -330,6 +321,20 @@ static struct radeon_asic r200_asic = {
330 }, 321 },
331}; 322};
332 323
324static struct radeon_asic_ring r300_gfx_ring = {
325 .ib_execute = &r100_ring_ib_execute,
326 .emit_fence = &r300_fence_ring_emit,
327 .emit_semaphore = &r100_semaphore_ring_emit,
328 .cs_parse = &r300_cs_parse,
329 .ring_start = &r300_ring_start,
330 .ring_test = &r100_ring_test,
331 .ib_test = &r100_ib_test,
332 .is_lockup = &r100_gpu_is_lockup,
333 .get_rptr = &radeon_ring_generic_get_rptr,
334 .get_wptr = &radeon_ring_generic_get_wptr,
335 .set_wptr = &radeon_ring_generic_set_wptr,
336};
337
333static struct radeon_asic r300_asic = { 338static struct radeon_asic r300_asic = {
334 .init = &r300_init, 339 .init = &r300_init,
335 .fini = &r300_fini, 340 .fini = &r300_fini,
@@ -345,19 +350,7 @@ static struct radeon_asic r300_asic = {
345 .set_page = &r100_pci_gart_set_page, 350 .set_page = &r100_pci_gart_set_page,
346 }, 351 },
347 .ring = { 352 .ring = {
348 [RADEON_RING_TYPE_GFX_INDEX] = { 353 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
349 .ib_execute = &r100_ring_ib_execute,
350 .emit_fence = &r300_fence_ring_emit,
351 .emit_semaphore = &r100_semaphore_ring_emit,
352 .cs_parse = &r300_cs_parse,
353 .ring_start = &r300_ring_start,
354 .ring_test = &r100_ring_test,
355 .ib_test = &r100_ib_test,
356 .is_lockup = &r100_gpu_is_lockup,
357 .get_rptr = &radeon_ring_generic_get_rptr,
358 .get_wptr = &radeon_ring_generic_get_wptr,
359 .set_wptr = &radeon_ring_generic_set_wptr,
360 }
361 }, 354 },
362 .irq = { 355 .irq = {
363 .set = &r100_irq_set, 356 .set = &r100_irq_set,
@@ -424,19 +417,7 @@ static struct radeon_asic r300_asic_pcie = {
424 .set_page = &rv370_pcie_gart_set_page, 417 .set_page = &rv370_pcie_gart_set_page,
425 }, 418 },
426 .ring = { 419 .ring = {
427 [RADEON_RING_TYPE_GFX_INDEX] = { 420 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
428 .ib_execute = &r100_ring_ib_execute,
429 .emit_fence = &r300_fence_ring_emit,
430 .emit_semaphore = &r100_semaphore_ring_emit,
431 .cs_parse = &r300_cs_parse,
432 .ring_start = &r300_ring_start,
433 .ring_test = &r100_ring_test,
434 .ib_test = &r100_ib_test,
435 .is_lockup = &r100_gpu_is_lockup,
436 .get_rptr = &radeon_ring_generic_get_rptr,
437 .get_wptr = &radeon_ring_generic_get_wptr,
438 .set_wptr = &radeon_ring_generic_set_wptr,
439 }
440 }, 421 },
441 .irq = { 422 .irq = {
442 .set = &r100_irq_set, 423 .set = &r100_irq_set,
@@ -503,19 +484,7 @@ static struct radeon_asic r420_asic = {
503 .set_page = &rv370_pcie_gart_set_page, 484 .set_page = &rv370_pcie_gart_set_page,
504 }, 485 },
505 .ring = { 486 .ring = {
506 [RADEON_RING_TYPE_GFX_INDEX] = { 487 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
507 .ib_execute = &r100_ring_ib_execute,
508 .emit_fence = &r300_fence_ring_emit,
509 .emit_semaphore = &r100_semaphore_ring_emit,
510 .cs_parse = &r300_cs_parse,
511 .ring_start = &r300_ring_start,
512 .ring_test = &r100_ring_test,
513 .ib_test = &r100_ib_test,
514 .is_lockup = &r100_gpu_is_lockup,
515 .get_rptr = &radeon_ring_generic_get_rptr,
516 .get_wptr = &radeon_ring_generic_get_wptr,
517 .set_wptr = &radeon_ring_generic_set_wptr,
518 }
519 }, 488 },
520 .irq = { 489 .irq = {
521 .set = &r100_irq_set, 490 .set = &r100_irq_set,
@@ -582,19 +551,7 @@ static struct radeon_asic rs400_asic = {
582 .set_page = &rs400_gart_set_page, 551 .set_page = &rs400_gart_set_page,
583 }, 552 },
584 .ring = { 553 .ring = {
585 [RADEON_RING_TYPE_GFX_INDEX] = { 554 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
586 .ib_execute = &r100_ring_ib_execute,
587 .emit_fence = &r300_fence_ring_emit,
588 .emit_semaphore = &r100_semaphore_ring_emit,
589 .cs_parse = &r300_cs_parse,
590 .ring_start = &r300_ring_start,
591 .ring_test = &r100_ring_test,
592 .ib_test = &r100_ib_test,
593 .is_lockup = &r100_gpu_is_lockup,
594 .get_rptr = &radeon_ring_generic_get_rptr,
595 .get_wptr = &radeon_ring_generic_get_wptr,
596 .set_wptr = &radeon_ring_generic_set_wptr,
597 }
598 }, 555 },
599 .irq = { 556 .irq = {
600 .set = &r100_irq_set, 557 .set = &r100_irq_set,
@@ -661,19 +618,7 @@ static struct radeon_asic rs600_asic = {
661 .set_page = &rs600_gart_set_page, 618 .set_page = &rs600_gart_set_page,
662 }, 619 },
663 .ring = { 620 .ring = {
664 [RADEON_RING_TYPE_GFX_INDEX] = { 621 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
665 .ib_execute = &r100_ring_ib_execute,
666 .emit_fence = &r300_fence_ring_emit,
667 .emit_semaphore = &r100_semaphore_ring_emit,
668 .cs_parse = &r300_cs_parse,
669 .ring_start = &r300_ring_start,
670 .ring_test = &r100_ring_test,
671 .ib_test = &r100_ib_test,
672 .is_lockup = &r100_gpu_is_lockup,
673 .get_rptr = &radeon_ring_generic_get_rptr,
674 .get_wptr = &radeon_ring_generic_get_wptr,
675 .set_wptr = &radeon_ring_generic_set_wptr,
676 }
677 }, 622 },
678 .irq = { 623 .irq = {
679 .set = &rs600_irq_set, 624 .set = &rs600_irq_set,
@@ -742,19 +687,7 @@ static struct radeon_asic rs690_asic = {
742 .set_page = &rs400_gart_set_page, 687 .set_page = &rs400_gart_set_page,
743 }, 688 },
744 .ring = { 689 .ring = {
745 [RADEON_RING_TYPE_GFX_INDEX] = { 690 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
746 .ib_execute = &r100_ring_ib_execute,
747 .emit_fence = &r300_fence_ring_emit,
748 .emit_semaphore = &r100_semaphore_ring_emit,
749 .cs_parse = &r300_cs_parse,
750 .ring_start = &r300_ring_start,
751 .ring_test = &r100_ring_test,
752 .ib_test = &r100_ib_test,
753 .is_lockup = &r100_gpu_is_lockup,
754 .get_rptr = &radeon_ring_generic_get_rptr,
755 .get_wptr = &radeon_ring_generic_get_wptr,
756 .set_wptr = &radeon_ring_generic_set_wptr,
757 }
758 }, 691 },
759 .irq = { 692 .irq = {
760 .set = &rs600_irq_set, 693 .set = &rs600_irq_set,
@@ -823,19 +756,7 @@ static struct radeon_asic rv515_asic = {
823 .set_page = &rv370_pcie_gart_set_page, 756 .set_page = &rv370_pcie_gart_set_page,
824 }, 757 },
825 .ring = { 758 .ring = {
826 [RADEON_RING_TYPE_GFX_INDEX] = { 759 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
827 .ib_execute = &r100_ring_ib_execute,
828 .emit_fence = &r300_fence_ring_emit,
829 .emit_semaphore = &r100_semaphore_ring_emit,
830 .cs_parse = &r300_cs_parse,
831 .ring_start = &rv515_ring_start,
832 .ring_test = &r100_ring_test,
833 .ib_test = &r100_ib_test,
834 .is_lockup = &r100_gpu_is_lockup,
835 .get_rptr = &radeon_ring_generic_get_rptr,
836 .get_wptr = &radeon_ring_generic_get_wptr,
837 .set_wptr = &radeon_ring_generic_set_wptr,
838 }
839 }, 760 },
840 .irq = { 761 .irq = {
841 .set = &rs600_irq_set, 762 .set = &rs600_irq_set,
@@ -902,19 +823,7 @@ static struct radeon_asic r520_asic = {
902 .set_page = &rv370_pcie_gart_set_page, 823 .set_page = &rv370_pcie_gart_set_page,
903 }, 824 },
904 .ring = { 825 .ring = {
905 [RADEON_RING_TYPE_GFX_INDEX] = { 826 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
906 .ib_execute = &r100_ring_ib_execute,
907 .emit_fence = &r300_fence_ring_emit,
908 .emit_semaphore = &r100_semaphore_ring_emit,
909 .cs_parse = &r300_cs_parse,
910 .ring_start = &rv515_ring_start,
911 .ring_test = &r100_ring_test,
912 .ib_test = &r100_ib_test,
913 .is_lockup = &r100_gpu_is_lockup,
914 .get_rptr = &radeon_ring_generic_get_rptr,
915 .get_wptr = &radeon_ring_generic_get_wptr,
916 .set_wptr = &radeon_ring_generic_set_wptr,
917 }
918 }, 827 },
919 .irq = { 828 .irq = {
920 .set = &rs600_irq_set, 829 .set = &rs600_irq_set,
@@ -966,6 +875,32 @@ static struct radeon_asic r520_asic = {
966 }, 875 },
967}; 876};
968 877
878static struct radeon_asic_ring r600_gfx_ring = {
879 .ib_execute = &r600_ring_ib_execute,
880 .emit_fence = &r600_fence_ring_emit,
881 .emit_semaphore = &r600_semaphore_ring_emit,
882 .cs_parse = &r600_cs_parse,
883 .ring_test = &r600_ring_test,
884 .ib_test = &r600_ib_test,
885 .is_lockup = &r600_gfx_is_lockup,
886 .get_rptr = &radeon_ring_generic_get_rptr,
887 .get_wptr = &radeon_ring_generic_get_wptr,
888 .set_wptr = &radeon_ring_generic_set_wptr,
889};
890
891static struct radeon_asic_ring r600_dma_ring = {
892 .ib_execute = &r600_dma_ring_ib_execute,
893 .emit_fence = &r600_dma_fence_ring_emit,
894 .emit_semaphore = &r600_dma_semaphore_ring_emit,
895 .cs_parse = &r600_dma_cs_parse,
896 .ring_test = &r600_dma_ring_test,
897 .ib_test = &r600_dma_ib_test,
898 .is_lockup = &r600_dma_is_lockup,
899 .get_rptr = &radeon_ring_generic_get_rptr,
900 .get_wptr = &radeon_ring_generic_get_wptr,
901 .set_wptr = &radeon_ring_generic_set_wptr,
902};
903
969static struct radeon_asic r600_asic = { 904static struct radeon_asic r600_asic = {
970 .init = &r600_init, 905 .init = &r600_init,
971 .fini = &r600_fini, 906 .fini = &r600_fini,
@@ -983,30 +918,8 @@ static struct radeon_asic r600_asic = {
983 .set_page = &rs600_gart_set_page, 918 .set_page = &rs600_gart_set_page,
984 }, 919 },
985 .ring = { 920 .ring = {
986 [RADEON_RING_TYPE_GFX_INDEX] = { 921 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
987 .ib_execute = &r600_ring_ib_execute, 922 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
988 .emit_fence = &r600_fence_ring_emit,
989 .emit_semaphore = &r600_semaphore_ring_emit,
990 .cs_parse = &r600_cs_parse,
991 .ring_test = &r600_ring_test,
992 .ib_test = &r600_ib_test,
993 .is_lockup = &r600_gfx_is_lockup,
994 .get_rptr = &radeon_ring_generic_get_rptr,
995 .get_wptr = &radeon_ring_generic_get_wptr,
996 .set_wptr = &radeon_ring_generic_set_wptr,
997 },
998 [R600_RING_TYPE_DMA_INDEX] = {
999 .ib_execute = &r600_dma_ring_ib_execute,
1000 .emit_fence = &r600_dma_fence_ring_emit,
1001 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1002 .cs_parse = &r600_dma_cs_parse,
1003 .ring_test = &r600_dma_ring_test,
1004 .ib_test = &r600_dma_ib_test,
1005 .is_lockup = &r600_dma_is_lockup,
1006 .get_rptr = &radeon_ring_generic_get_rptr,
1007 .get_wptr = &radeon_ring_generic_get_wptr,
1008 .set_wptr = &radeon_ring_generic_set_wptr,
1009 }
1010 }, 923 },
1011 .irq = { 924 .irq = {
1012 .set = &r600_irq_set, 925 .set = &r600_irq_set,
@@ -1078,30 +991,8 @@ static struct radeon_asic rv6xx_asic = {
1078 .set_page = &rs600_gart_set_page, 991 .set_page = &rs600_gart_set_page,
1079 }, 992 },
1080 .ring = { 993 .ring = {
1081 [RADEON_RING_TYPE_GFX_INDEX] = { 994 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1082 .ib_execute = &r600_ring_ib_execute, 995 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1083 .emit_fence = &r600_fence_ring_emit,
1084 .emit_semaphore = &r600_semaphore_ring_emit,
1085 .cs_parse = &r600_cs_parse,
1086 .ring_test = &r600_ring_test,
1087 .ib_test = &r600_ib_test,
1088 .is_lockup = &r600_gfx_is_lockup,
1089 .get_rptr = &radeon_ring_generic_get_rptr,
1090 .get_wptr = &radeon_ring_generic_get_wptr,
1091 .set_wptr = &radeon_ring_generic_set_wptr,
1092 },
1093 [R600_RING_TYPE_DMA_INDEX] = {
1094 .ib_execute = &r600_dma_ring_ib_execute,
1095 .emit_fence = &r600_dma_fence_ring_emit,
1096 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1097 .cs_parse = &r600_dma_cs_parse,
1098 .ring_test = &r600_dma_ring_test,
1099 .ib_test = &r600_dma_ib_test,
1100 .is_lockup = &r600_dma_is_lockup,
1101 .get_rptr = &radeon_ring_generic_get_rptr,
1102 .get_wptr = &radeon_ring_generic_get_wptr,
1103 .set_wptr = &radeon_ring_generic_set_wptr,
1104 }
1105 }, 996 },
1106 .irq = { 997 .irq = {
1107 .set = &r600_irq_set, 998 .set = &r600_irq_set,
@@ -1187,30 +1078,8 @@ static struct radeon_asic rs780_asic = {
1187 .set_page = &rs600_gart_set_page, 1078 .set_page = &rs600_gart_set_page,
1188 }, 1079 },
1189 .ring = { 1080 .ring = {
1190 [RADEON_RING_TYPE_GFX_INDEX] = { 1081 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1191 .ib_execute = &r600_ring_ib_execute, 1082 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1192 .emit_fence = &r600_fence_ring_emit,
1193 .emit_semaphore = &r600_semaphore_ring_emit,
1194 .cs_parse = &r600_cs_parse,
1195 .ring_test = &r600_ring_test,
1196 .ib_test = &r600_ib_test,
1197 .is_lockup = &r600_gfx_is_lockup,
1198 .get_rptr = &radeon_ring_generic_get_rptr,
1199 .get_wptr = &radeon_ring_generic_get_wptr,
1200 .set_wptr = &radeon_ring_generic_set_wptr,
1201 },
1202 [R600_RING_TYPE_DMA_INDEX] = {
1203 .ib_execute = &r600_dma_ring_ib_execute,
1204 .emit_fence = &r600_dma_fence_ring_emit,
1205 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1206 .cs_parse = &r600_dma_cs_parse,
1207 .ring_test = &r600_dma_ring_test,
1208 .ib_test = &r600_dma_ib_test,
1209 .is_lockup = &r600_dma_is_lockup,
1210 .get_rptr = &radeon_ring_generic_get_rptr,
1211 .get_wptr = &radeon_ring_generic_get_wptr,
1212 .set_wptr = &radeon_ring_generic_set_wptr,
1213 }
1214 }, 1083 },
1215 .irq = { 1084 .irq = {
1216 .set = &r600_irq_set, 1085 .set = &r600_irq_set,
@@ -1280,6 +1149,19 @@ static struct radeon_asic rs780_asic = {
1280 }, 1149 },
1281}; 1150};
1282 1151
1152static struct radeon_asic_ring rv770_uvd_ring = {
1153 .ib_execute = &r600_uvd_ib_execute,
1154 .emit_fence = &r600_uvd_fence_emit,
1155 .emit_semaphore = &r600_uvd_semaphore_emit,
1156 .cs_parse = &radeon_uvd_cs_parse,
1157 .ring_test = &r600_uvd_ring_test,
1158 .ib_test = &r600_uvd_ib_test,
1159 .is_lockup = &radeon_ring_test_lockup,
1160 .get_rptr = &radeon_ring_generic_get_rptr,
1161 .get_wptr = &radeon_ring_generic_get_wptr,
1162 .set_wptr = &radeon_ring_generic_set_wptr,
1163};
1164
1283static struct radeon_asic rv770_asic = { 1165static struct radeon_asic rv770_asic = {
1284 .init = &rv770_init, 1166 .init = &rv770_init,
1285 .fini = &rv770_fini, 1167 .fini = &rv770_fini,
@@ -1297,42 +1179,9 @@ static struct radeon_asic rv770_asic = {
1297 .set_page = &rs600_gart_set_page, 1179 .set_page = &rs600_gart_set_page,
1298 }, 1180 },
1299 .ring = { 1181 .ring = {
1300 [RADEON_RING_TYPE_GFX_INDEX] = { 1182 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1301 .ib_execute = &r600_ring_ib_execute, 1183 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1302 .emit_fence = &r600_fence_ring_emit, 1184 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1303 .emit_semaphore = &r600_semaphore_ring_emit,
1304 .cs_parse = &r600_cs_parse,
1305 .ring_test = &r600_ring_test,
1306 .ib_test = &r600_ib_test,
1307 .is_lockup = &r600_gfx_is_lockup,
1308 .get_rptr = &radeon_ring_generic_get_rptr,
1309 .get_wptr = &radeon_ring_generic_get_wptr,
1310 .set_wptr = &radeon_ring_generic_set_wptr,
1311 },
1312 [R600_RING_TYPE_DMA_INDEX] = {
1313 .ib_execute = &r600_dma_ring_ib_execute,
1314 .emit_fence = &r600_dma_fence_ring_emit,
1315 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1316 .cs_parse = &r600_dma_cs_parse,
1317 .ring_test = &r600_dma_ring_test,
1318 .ib_test = &r600_dma_ib_test,
1319 .is_lockup = &r600_dma_is_lockup,
1320 .get_rptr = &radeon_ring_generic_get_rptr,
1321 .get_wptr = &radeon_ring_generic_get_wptr,
1322 .set_wptr = &radeon_ring_generic_set_wptr,
1323 },
1324 [R600_RING_TYPE_UVD_INDEX] = {
1325 .ib_execute = &r600_uvd_ib_execute,
1326 .emit_fence = &r600_uvd_fence_emit,
1327 .emit_semaphore = &r600_uvd_semaphore_emit,
1328 .cs_parse = &radeon_uvd_cs_parse,
1329 .ring_test = &r600_uvd_ring_test,
1330 .ib_test = &r600_uvd_ib_test,
1331 .is_lockup = &radeon_ring_test_lockup,
1332 .get_rptr = &radeon_ring_generic_get_rptr,
1333 .get_wptr = &radeon_ring_generic_get_wptr,
1334 .set_wptr = &radeon_ring_generic_set_wptr,
1335 }
1336 }, 1185 },
1337 .irq = { 1186 .irq = {
1338 .set = &r600_irq_set, 1187 .set = &r600_irq_set,
@@ -1405,6 +1254,32 @@ static struct radeon_asic rv770_asic = {
1405 }, 1254 },
1406}; 1255};
1407 1256
1257static struct radeon_asic_ring evergreen_gfx_ring = {
1258 .ib_execute = &evergreen_ring_ib_execute,
1259 .emit_fence = &r600_fence_ring_emit,
1260 .emit_semaphore = &r600_semaphore_ring_emit,
1261 .cs_parse = &evergreen_cs_parse,
1262 .ring_test = &r600_ring_test,
1263 .ib_test = &r600_ib_test,
1264 .is_lockup = &evergreen_gfx_is_lockup,
1265 .get_rptr = &radeon_ring_generic_get_rptr,
1266 .get_wptr = &radeon_ring_generic_get_wptr,
1267 .set_wptr = &radeon_ring_generic_set_wptr,
1268};
1269
1270static struct radeon_asic_ring evergreen_dma_ring = {
1271 .ib_execute = &evergreen_dma_ring_ib_execute,
1272 .emit_fence = &evergreen_dma_fence_ring_emit,
1273 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1274 .cs_parse = &evergreen_dma_cs_parse,
1275 .ring_test = &r600_dma_ring_test,
1276 .ib_test = &r600_dma_ib_test,
1277 .is_lockup = &evergreen_dma_is_lockup,
1278 .get_rptr = &radeon_ring_generic_get_rptr,
1279 .get_wptr = &radeon_ring_generic_get_wptr,
1280 .set_wptr = &radeon_ring_generic_set_wptr,
1281};
1282
1408static struct radeon_asic evergreen_asic = { 1283static struct radeon_asic evergreen_asic = {
1409 .init = &evergreen_init, 1284 .init = &evergreen_init,
1410 .fini = &evergreen_fini, 1285 .fini = &evergreen_fini,
@@ -1422,42 +1297,9 @@ static struct radeon_asic evergreen_asic = {
1422 .set_page = &rs600_gart_set_page, 1297 .set_page = &rs600_gart_set_page,
1423 }, 1298 },
1424 .ring = { 1299 .ring = {
1425 [RADEON_RING_TYPE_GFX_INDEX] = { 1300 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1426 .ib_execute = &evergreen_ring_ib_execute, 1301 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1427 .emit_fence = &r600_fence_ring_emit, 1302 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1428 .emit_semaphore = &r600_semaphore_ring_emit,
1429 .cs_parse = &evergreen_cs_parse,
1430 .ring_test = &r600_ring_test,
1431 .ib_test = &r600_ib_test,
1432 .is_lockup = &evergreen_gfx_is_lockup,
1433 .get_rptr = &radeon_ring_generic_get_rptr,
1434 .get_wptr = &radeon_ring_generic_get_wptr,
1435 .set_wptr = &radeon_ring_generic_set_wptr,
1436 },
1437 [R600_RING_TYPE_DMA_INDEX] = {
1438 .ib_execute = &evergreen_dma_ring_ib_execute,
1439 .emit_fence = &evergreen_dma_fence_ring_emit,
1440 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1441 .cs_parse = &evergreen_dma_cs_parse,
1442 .ring_test = &r600_dma_ring_test,
1443 .ib_test = &r600_dma_ib_test,
1444 .is_lockup = &evergreen_dma_is_lockup,
1445 .get_rptr = &radeon_ring_generic_get_rptr,
1446 .get_wptr = &radeon_ring_generic_get_wptr,
1447 .set_wptr = &radeon_ring_generic_set_wptr,
1448 },
1449 [R600_RING_TYPE_UVD_INDEX] = {
1450 .ib_execute = &r600_uvd_ib_execute,
1451 .emit_fence = &r600_uvd_fence_emit,
1452 .emit_semaphore = &r600_uvd_semaphore_emit,
1453 .cs_parse = &radeon_uvd_cs_parse,
1454 .ring_test = &r600_uvd_ring_test,
1455 .ib_test = &r600_uvd_ib_test,
1456 .is_lockup = &radeon_ring_test_lockup,
1457 .get_rptr = &radeon_ring_generic_get_rptr,
1458 .get_wptr = &radeon_ring_generic_get_wptr,
1459 .set_wptr = &radeon_ring_generic_set_wptr,
1460 }
1461 }, 1303 },
1462 .irq = { 1304 .irq = {
1463 .set = &evergreen_irq_set, 1305 .set = &evergreen_irq_set,
@@ -1547,42 +1389,9 @@ static struct radeon_asic sumo_asic = {
1547 .set_page = &rs600_gart_set_page, 1389 .set_page = &rs600_gart_set_page,
1548 }, 1390 },
1549 .ring = { 1391 .ring = {
1550 [RADEON_RING_TYPE_GFX_INDEX] = { 1392 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1551 .ib_execute = &evergreen_ring_ib_execute, 1393 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1552 .emit_fence = &r600_fence_ring_emit, 1394 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1553 .emit_semaphore = &r600_semaphore_ring_emit,
1554 .cs_parse = &evergreen_cs_parse,
1555 .ring_test = &r600_ring_test,
1556 .ib_test = &r600_ib_test,
1557 .is_lockup = &evergreen_gfx_is_lockup,
1558 .get_rptr = &radeon_ring_generic_get_rptr,
1559 .get_wptr = &radeon_ring_generic_get_wptr,
1560 .set_wptr = &radeon_ring_generic_set_wptr,
1561 },
1562 [R600_RING_TYPE_DMA_INDEX] = {
1563 .ib_execute = &evergreen_dma_ring_ib_execute,
1564 .emit_fence = &evergreen_dma_fence_ring_emit,
1565 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1566 .cs_parse = &evergreen_dma_cs_parse,
1567 .ring_test = &r600_dma_ring_test,
1568 .ib_test = &r600_dma_ib_test,
1569 .is_lockup = &evergreen_dma_is_lockup,
1570 .get_rptr = &radeon_ring_generic_get_rptr,
1571 .get_wptr = &radeon_ring_generic_get_wptr,
1572 .set_wptr = &radeon_ring_generic_set_wptr,
1573 },
1574 [R600_RING_TYPE_UVD_INDEX] = {
1575 .ib_execute = &r600_uvd_ib_execute,
1576 .emit_fence = &r600_uvd_fence_emit,
1577 .emit_semaphore = &r600_uvd_semaphore_emit,
1578 .cs_parse = &radeon_uvd_cs_parse,
1579 .ring_test = &r600_uvd_ring_test,
1580 .ib_test = &r600_uvd_ib_test,
1581 .is_lockup = &radeon_ring_test_lockup,
1582 .get_rptr = &radeon_ring_generic_get_rptr,
1583 .get_wptr = &radeon_ring_generic_get_wptr,
1584 .set_wptr = &radeon_ring_generic_set_wptr,
1585 }
1586 }, 1395 },
1587 .irq = { 1396 .irq = {
1588 .set = &evergreen_irq_set, 1397 .set = &evergreen_irq_set,
@@ -1671,42 +1480,9 @@ static struct radeon_asic btc_asic = {
1671 .set_page = &rs600_gart_set_page, 1480 .set_page = &rs600_gart_set_page,
1672 }, 1481 },
1673 .ring = { 1482 .ring = {
1674 [RADEON_RING_TYPE_GFX_INDEX] = { 1483 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1675 .ib_execute = &evergreen_ring_ib_execute, 1484 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1676 .emit_fence = &r600_fence_ring_emit, 1485 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1677 .emit_semaphore = &r600_semaphore_ring_emit,
1678 .cs_parse = &evergreen_cs_parse,
1679 .ring_test = &r600_ring_test,
1680 .ib_test = &r600_ib_test,
1681 .is_lockup = &evergreen_gfx_is_lockup,
1682 .get_rptr = &radeon_ring_generic_get_rptr,
1683 .get_wptr = &radeon_ring_generic_get_wptr,
1684 .set_wptr = &radeon_ring_generic_set_wptr,
1685 },
1686 [R600_RING_TYPE_DMA_INDEX] = {
1687 .ib_execute = &evergreen_dma_ring_ib_execute,
1688 .emit_fence = &evergreen_dma_fence_ring_emit,
1689 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1690 .cs_parse = &evergreen_dma_cs_parse,
1691 .ring_test = &r600_dma_ring_test,
1692 .ib_test = &r600_dma_ib_test,
1693 .is_lockup = &evergreen_dma_is_lockup,
1694 .get_rptr = &radeon_ring_generic_get_rptr,
1695 .get_wptr = &radeon_ring_generic_get_wptr,
1696 .set_wptr = &radeon_ring_generic_set_wptr,
1697 },
1698 [R600_RING_TYPE_UVD_INDEX] = {
1699 .ib_execute = &r600_uvd_ib_execute,
1700 .emit_fence = &r600_uvd_fence_emit,
1701 .emit_semaphore = &r600_uvd_semaphore_emit,
1702 .cs_parse = &radeon_uvd_cs_parse,
1703 .ring_test = &r600_uvd_ring_test,
1704 .ib_test = &r600_uvd_ib_test,
1705 .is_lockup = &radeon_ring_test_lockup,
1706 .get_rptr = &radeon_ring_generic_get_rptr,
1707 .get_wptr = &radeon_ring_generic_get_wptr,
1708 .set_wptr = &radeon_ring_generic_set_wptr,
1709 }
1710 }, 1486 },
1711 .irq = { 1487 .irq = {
1712 .set = &evergreen_irq_set, 1488 .set = &evergreen_irq_set,
@@ -1779,6 +1555,49 @@ static struct radeon_asic btc_asic = {
1779 }, 1555 },
1780}; 1556};
1781 1557
1558static struct radeon_asic_ring cayman_gfx_ring = {
1559 .ib_execute = &cayman_ring_ib_execute,
1560 .ib_parse = &evergreen_ib_parse,
1561 .emit_fence = &cayman_fence_ring_emit,
1562 .emit_semaphore = &r600_semaphore_ring_emit,
1563 .cs_parse = &evergreen_cs_parse,
1564 .ring_test = &r600_ring_test,
1565 .ib_test = &r600_ib_test,
1566 .is_lockup = &cayman_gfx_is_lockup,
1567 .vm_flush = &cayman_vm_flush,
1568 .get_rptr = &radeon_ring_generic_get_rptr,
1569 .get_wptr = &radeon_ring_generic_get_wptr,
1570 .set_wptr = &radeon_ring_generic_set_wptr,
1571};
1572
1573static struct radeon_asic_ring cayman_dma_ring = {
1574 .ib_execute = &cayman_dma_ring_ib_execute,
1575 .ib_parse = &evergreen_dma_ib_parse,
1576 .emit_fence = &evergreen_dma_fence_ring_emit,
1577 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1578 .cs_parse = &evergreen_dma_cs_parse,
1579 .ring_test = &r600_dma_ring_test,
1580 .ib_test = &r600_dma_ib_test,
1581 .is_lockup = &cayman_dma_is_lockup,
1582 .vm_flush = &cayman_dma_vm_flush,
1583 .get_rptr = &radeon_ring_generic_get_rptr,
1584 .get_wptr = &radeon_ring_generic_get_wptr,
1585 .set_wptr = &radeon_ring_generic_set_wptr
1586};
1587
1588static struct radeon_asic_ring cayman_uvd_ring = {
1589 .ib_execute = &r600_uvd_ib_execute,
1590 .emit_fence = &r600_uvd_fence_emit,
1591 .emit_semaphore = &cayman_uvd_semaphore_emit,
1592 .cs_parse = &radeon_uvd_cs_parse,
1593 .ring_test = &r600_uvd_ring_test,
1594 .ib_test = &r600_uvd_ib_test,
1595 .is_lockup = &radeon_ring_test_lockup,
1596 .get_rptr = &radeon_ring_generic_get_rptr,
1597 .get_wptr = &radeon_ring_generic_get_wptr,
1598 .set_wptr = &radeon_ring_generic_set_wptr,
1599};
1600
1782static struct radeon_asic cayman_asic = { 1601static struct radeon_asic cayman_asic = {
1783 .init = &cayman_init, 1602 .init = &cayman_init,
1784 .fini = &cayman_fini, 1603 .fini = &cayman_fini,
@@ -1802,88 +1621,12 @@ static struct radeon_asic cayman_asic = {
1802 .set_page = &cayman_vm_set_page, 1621 .set_page = &cayman_vm_set_page,
1803 }, 1622 },
1804 .ring = { 1623 .ring = {
1805 [RADEON_RING_TYPE_GFX_INDEX] = { 1624 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1806 .ib_execute = &cayman_ring_ib_execute, 1625 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1807 .ib_parse = &evergreen_ib_parse, 1626 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1808 .emit_fence = &cayman_fence_ring_emit, 1627 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1809 .emit_semaphore = &r600_semaphore_ring_emit, 1628 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1810 .cs_parse = &evergreen_cs_parse, 1629 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1811 .ring_test = &r600_ring_test,
1812 .ib_test = &r600_ib_test,
1813 .is_lockup = &cayman_gfx_is_lockup,
1814 .vm_flush = &cayman_vm_flush,
1815 .get_rptr = &radeon_ring_generic_get_rptr,
1816 .get_wptr = &radeon_ring_generic_get_wptr,
1817 .set_wptr = &radeon_ring_generic_set_wptr,
1818 },
1819 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1820 .ib_execute = &cayman_ring_ib_execute,
1821 .ib_parse = &evergreen_ib_parse,
1822 .emit_fence = &cayman_fence_ring_emit,
1823 .emit_semaphore = &r600_semaphore_ring_emit,
1824 .cs_parse = &evergreen_cs_parse,
1825 .ring_test = &r600_ring_test,
1826 .ib_test = &r600_ib_test,
1827 .is_lockup = &cayman_gfx_is_lockup,
1828 .vm_flush = &cayman_vm_flush,
1829 .get_rptr = &radeon_ring_generic_get_rptr,
1830 .get_wptr = &radeon_ring_generic_get_wptr,
1831 .set_wptr = &radeon_ring_generic_set_wptr,
1832 },
1833 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1834 .ib_execute = &cayman_ring_ib_execute,
1835 .ib_parse = &evergreen_ib_parse,
1836 .emit_fence = &cayman_fence_ring_emit,
1837 .emit_semaphore = &r600_semaphore_ring_emit,
1838 .cs_parse = &evergreen_cs_parse,
1839 .ring_test = &r600_ring_test,
1840 .ib_test = &r600_ib_test,
1841 .is_lockup = &cayman_gfx_is_lockup,
1842 .vm_flush = &cayman_vm_flush,
1843 .get_rptr = &radeon_ring_generic_get_rptr,
1844 .get_wptr = &radeon_ring_generic_get_wptr,
1845 .set_wptr = &radeon_ring_generic_set_wptr,
1846 },
1847 [R600_RING_TYPE_DMA_INDEX] = {
1848 .ib_execute = &cayman_dma_ring_ib_execute,
1849 .ib_parse = &evergreen_dma_ib_parse,
1850 .emit_fence = &evergreen_dma_fence_ring_emit,
1851 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1852 .cs_parse = &evergreen_dma_cs_parse,
1853 .ring_test = &r600_dma_ring_test,
1854 .ib_test = &r600_dma_ib_test,
1855 .is_lockup = &cayman_dma_is_lockup,
1856 .vm_flush = &cayman_dma_vm_flush,
1857 .get_rptr = &radeon_ring_generic_get_rptr,
1858 .get_wptr = &radeon_ring_generic_get_wptr,
1859 .set_wptr = &radeon_ring_generic_set_wptr,
1860 },
1861 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1862 .ib_execute = &cayman_dma_ring_ib_execute,
1863 .ib_parse = &evergreen_dma_ib_parse,
1864 .emit_fence = &evergreen_dma_fence_ring_emit,
1865 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1866 .cs_parse = &evergreen_dma_cs_parse,
1867 .ring_test = &r600_dma_ring_test,
1868 .ib_test = &r600_dma_ib_test,
1869 .is_lockup = &cayman_dma_is_lockup,
1870 .vm_flush = &cayman_dma_vm_flush,
1871 .get_rptr = &radeon_ring_generic_get_rptr,
1872 .get_wptr = &radeon_ring_generic_get_wptr,
1873 .set_wptr = &radeon_ring_generic_set_wptr,
1874 },
1875 [R600_RING_TYPE_UVD_INDEX] = {
1876 .ib_execute = &r600_uvd_ib_execute,
1877 .emit_fence = &r600_uvd_fence_emit,
1878 .emit_semaphore = &cayman_uvd_semaphore_emit,
1879 .cs_parse = &radeon_uvd_cs_parse,
1880 .ring_test = &r600_uvd_ring_test,
1881 .ib_test = &r600_uvd_ib_test,
1882 .is_lockup = &radeon_ring_test_lockup,
1883 .get_rptr = &radeon_ring_generic_get_rptr,
1884 .get_wptr = &radeon_ring_generic_get_wptr,
1885 .set_wptr = &radeon_ring_generic_set_wptr,
1886 }
1887 }, 1630 },
1888 .irq = { 1631 .irq = {
1889 .set = &evergreen_irq_set, 1632 .set = &evergreen_irq_set,
@@ -1979,88 +1722,12 @@ static struct radeon_asic trinity_asic = {
1979 .set_page = &cayman_vm_set_page, 1722 .set_page = &cayman_vm_set_page,
1980 }, 1723 },
1981 .ring = { 1724 .ring = {
1982 [RADEON_RING_TYPE_GFX_INDEX] = { 1725 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1983 .ib_execute = &cayman_ring_ib_execute, 1726 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1984 .ib_parse = &evergreen_ib_parse, 1727 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1985 .emit_fence = &cayman_fence_ring_emit, 1728 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1986 .emit_semaphore = &r600_semaphore_ring_emit, 1729 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1987 .cs_parse = &evergreen_cs_parse, 1730 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1988 .ring_test = &r600_ring_test,
1989 .ib_test = &r600_ib_test,
1990 .is_lockup = &cayman_gfx_is_lockup,
1991 .vm_flush = &cayman_vm_flush,
1992 .get_rptr = &radeon_ring_generic_get_rptr,
1993 .get_wptr = &radeon_ring_generic_get_wptr,
1994 .set_wptr = &radeon_ring_generic_set_wptr,
1995 },
1996 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1997 .ib_execute = &cayman_ring_ib_execute,
1998 .ib_parse = &evergreen_ib_parse,
1999 .emit_fence = &cayman_fence_ring_emit,
2000 .emit_semaphore = &r600_semaphore_ring_emit,
2001 .cs_parse = &evergreen_cs_parse,
2002 .ring_test = &r600_ring_test,
2003 .ib_test = &r600_ib_test,
2004 .is_lockup = &cayman_gfx_is_lockup,
2005 .vm_flush = &cayman_vm_flush,
2006 .get_rptr = &radeon_ring_generic_get_rptr,
2007 .get_wptr = &radeon_ring_generic_get_wptr,
2008 .set_wptr = &radeon_ring_generic_set_wptr,
2009 },
2010 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2011 .ib_execute = &cayman_ring_ib_execute,
2012 .ib_parse = &evergreen_ib_parse,
2013 .emit_fence = &cayman_fence_ring_emit,
2014 .emit_semaphore = &r600_semaphore_ring_emit,
2015 .cs_parse = &evergreen_cs_parse,
2016 .ring_test = &r600_ring_test,
2017 .ib_test = &r600_ib_test,
2018 .is_lockup = &cayman_gfx_is_lockup,
2019 .vm_flush = &cayman_vm_flush,
2020 .get_rptr = &radeon_ring_generic_get_rptr,
2021 .get_wptr = &radeon_ring_generic_get_wptr,
2022 .set_wptr = &radeon_ring_generic_set_wptr,
2023 },
2024 [R600_RING_TYPE_DMA_INDEX] = {
2025 .ib_execute = &cayman_dma_ring_ib_execute,
2026 .ib_parse = &evergreen_dma_ib_parse,
2027 .emit_fence = &evergreen_dma_fence_ring_emit,
2028 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2029 .cs_parse = &evergreen_dma_cs_parse,
2030 .ring_test = &r600_dma_ring_test,
2031 .ib_test = &r600_dma_ib_test,
2032 .is_lockup = &cayman_dma_is_lockup,
2033 .vm_flush = &cayman_dma_vm_flush,
2034 .get_rptr = &radeon_ring_generic_get_rptr,
2035 .get_wptr = &radeon_ring_generic_get_wptr,
2036 .set_wptr = &radeon_ring_generic_set_wptr,
2037 },
2038 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2039 .ib_execute = &cayman_dma_ring_ib_execute,
2040 .ib_parse = &evergreen_dma_ib_parse,
2041 .emit_fence = &evergreen_dma_fence_ring_emit,
2042 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2043 .cs_parse = &evergreen_dma_cs_parse,
2044 .ring_test = &r600_dma_ring_test,
2045 .ib_test = &r600_dma_ib_test,
2046 .is_lockup = &cayman_dma_is_lockup,
2047 .vm_flush = &cayman_dma_vm_flush,
2048 .get_rptr = &radeon_ring_generic_get_rptr,
2049 .get_wptr = &radeon_ring_generic_get_wptr,
2050 .set_wptr = &radeon_ring_generic_set_wptr,
2051 },
2052 [R600_RING_TYPE_UVD_INDEX] = {
2053 .ib_execute = &r600_uvd_ib_execute,
2054 .emit_fence = &r600_uvd_fence_emit,
2055 .emit_semaphore = &cayman_uvd_semaphore_emit,
2056 .cs_parse = &radeon_uvd_cs_parse,
2057 .ring_test = &r600_uvd_ring_test,
2058 .ib_test = &r600_uvd_ib_test,
2059 .is_lockup = &radeon_ring_test_lockup,
2060 .get_rptr = &radeon_ring_generic_get_rptr,
2061 .get_wptr = &radeon_ring_generic_get_wptr,
2062 .set_wptr = &radeon_ring_generic_set_wptr,
2063 }
2064 }, 1731 },
2065 .irq = { 1732 .irq = {
2066 .set = &evergreen_irq_set, 1733 .set = &evergreen_irq_set,
@@ -2130,6 +1797,36 @@ static struct radeon_asic trinity_asic = {
2130 }, 1797 },
2131}; 1798};
2132 1799
1800static struct radeon_asic_ring si_gfx_ring = {
1801 .ib_execute = &si_ring_ib_execute,
1802 .ib_parse = &si_ib_parse,
1803 .emit_fence = &si_fence_ring_emit,
1804 .emit_semaphore = &r600_semaphore_ring_emit,
1805 .cs_parse = NULL,
1806 .ring_test = &r600_ring_test,
1807 .ib_test = &r600_ib_test,
1808 .is_lockup = &si_gfx_is_lockup,
1809 .vm_flush = &si_vm_flush,
1810 .get_rptr = &radeon_ring_generic_get_rptr,
1811 .get_wptr = &radeon_ring_generic_get_wptr,
1812 .set_wptr = &radeon_ring_generic_set_wptr,
1813};
1814
1815static struct radeon_asic_ring si_dma_ring = {
1816 .ib_execute = &cayman_dma_ring_ib_execute,
1817 .ib_parse = &evergreen_dma_ib_parse,
1818 .emit_fence = &evergreen_dma_fence_ring_emit,
1819 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1820 .cs_parse = NULL,
1821 .ring_test = &r600_dma_ring_test,
1822 .ib_test = &r600_dma_ib_test,
1823 .is_lockup = &si_dma_is_lockup,
1824 .vm_flush = &si_dma_vm_flush,
1825 .get_rptr = &radeon_ring_generic_get_rptr,
1826 .get_wptr = &radeon_ring_generic_get_wptr,
1827 .set_wptr = &radeon_ring_generic_set_wptr,
1828};
1829
2133static struct radeon_asic si_asic = { 1830static struct radeon_asic si_asic = {
2134 .init = &si_init, 1831 .init = &si_init,
2135 .fini = &si_fini, 1832 .fini = &si_fini,
@@ -2153,88 +1850,12 @@ static struct radeon_asic si_asic = {
2153 .set_page = &si_vm_set_page, 1850 .set_page = &si_vm_set_page,
2154 }, 1851 },
2155 .ring = { 1852 .ring = {
2156 [RADEON_RING_TYPE_GFX_INDEX] = { 1853 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
2157 .ib_execute = &si_ring_ib_execute, 1854 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
2158 .ib_parse = &si_ib_parse, 1855 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
2159 .emit_fence = &si_fence_ring_emit, 1856 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
2160 .emit_semaphore = &r600_semaphore_ring_emit, 1857 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
2161 .cs_parse = NULL, 1858 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2162 .ring_test = &r600_ring_test,
2163 .ib_test = &r600_ib_test,
2164 .is_lockup = &si_gfx_is_lockup,
2165 .vm_flush = &si_vm_flush,
2166 .get_rptr = &radeon_ring_generic_get_rptr,
2167 .get_wptr = &radeon_ring_generic_get_wptr,
2168 .set_wptr = &radeon_ring_generic_set_wptr,
2169 },
2170 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2171 .ib_execute = &si_ring_ib_execute,
2172 .ib_parse = &si_ib_parse,
2173 .emit_fence = &si_fence_ring_emit,
2174 .emit_semaphore = &r600_semaphore_ring_emit,
2175 .cs_parse = NULL,
2176 .ring_test = &r600_ring_test,
2177 .ib_test = &r600_ib_test,
2178 .is_lockup = &si_gfx_is_lockup,
2179 .vm_flush = &si_vm_flush,
2180 .get_rptr = &radeon_ring_generic_get_rptr,
2181 .get_wptr = &radeon_ring_generic_get_wptr,
2182 .set_wptr = &radeon_ring_generic_set_wptr,
2183 },
2184 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2185 .ib_execute = &si_ring_ib_execute,
2186 .ib_parse = &si_ib_parse,
2187 .emit_fence = &si_fence_ring_emit,
2188 .emit_semaphore = &r600_semaphore_ring_emit,
2189 .cs_parse = NULL,
2190 .ring_test = &r600_ring_test,
2191 .ib_test = &r600_ib_test,
2192 .is_lockup = &si_gfx_is_lockup,
2193 .vm_flush = &si_vm_flush,
2194 .get_rptr = &radeon_ring_generic_get_rptr,
2195 .get_wptr = &radeon_ring_generic_get_wptr,
2196 .set_wptr = &radeon_ring_generic_set_wptr,
2197 },
2198 [R600_RING_TYPE_DMA_INDEX] = {
2199 .ib_execute = &cayman_dma_ring_ib_execute,
2200 .ib_parse = &evergreen_dma_ib_parse,
2201 .emit_fence = &evergreen_dma_fence_ring_emit,
2202 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2203 .cs_parse = NULL,
2204 .ring_test = &r600_dma_ring_test,
2205 .ib_test = &r600_dma_ib_test,
2206 .is_lockup = &si_dma_is_lockup,
2207 .vm_flush = &si_dma_vm_flush,
2208 .get_rptr = &radeon_ring_generic_get_rptr,
2209 .get_wptr = &radeon_ring_generic_get_wptr,
2210 .set_wptr = &radeon_ring_generic_set_wptr,
2211 },
2212 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2213 .ib_execute = &cayman_dma_ring_ib_execute,
2214 .ib_parse = &evergreen_dma_ib_parse,
2215 .emit_fence = &evergreen_dma_fence_ring_emit,
2216 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2217 .cs_parse = NULL,
2218 .ring_test = &r600_dma_ring_test,
2219 .ib_test = &r600_dma_ib_test,
2220 .is_lockup = &si_dma_is_lockup,
2221 .vm_flush = &si_dma_vm_flush,
2222 .get_rptr = &radeon_ring_generic_get_rptr,
2223 .get_wptr = &radeon_ring_generic_get_wptr,
2224 .set_wptr = &radeon_ring_generic_set_wptr,
2225 },
2226 [R600_RING_TYPE_UVD_INDEX] = {
2227 .ib_execute = &r600_uvd_ib_execute,
2228 .emit_fence = &r600_uvd_fence_emit,
2229 .emit_semaphore = &cayman_uvd_semaphore_emit,
2230 .cs_parse = &radeon_uvd_cs_parse,
2231 .ring_test = &r600_uvd_ring_test,
2232 .ib_test = &r600_uvd_ib_test,
2233 .is_lockup = &radeon_ring_test_lockup,
2234 .get_rptr = &radeon_ring_generic_get_rptr,
2235 .get_wptr = &radeon_ring_generic_get_wptr,
2236 .set_wptr = &radeon_ring_generic_set_wptr,
2237 }
2238 }, 1859 },
2239 .irq = { 1860 .irq = {
2240 .set = &si_irq_set, 1861 .set = &si_irq_set,
@@ -2305,6 +1926,51 @@ static struct radeon_asic si_asic = {
2305 }, 1926 },
2306}; 1927};
2307 1928
1929static struct radeon_asic_ring ci_gfx_ring = {
1930 .ib_execute = &cik_ring_ib_execute,
1931 .ib_parse = &cik_ib_parse,
1932 .emit_fence = &cik_fence_gfx_ring_emit,
1933 .emit_semaphore = &cik_semaphore_ring_emit,
1934 .cs_parse = NULL,
1935 .ring_test = &cik_ring_test,
1936 .ib_test = &cik_ib_test,
1937 .is_lockup = &cik_gfx_is_lockup,
1938 .vm_flush = &cik_vm_flush,
1939 .get_rptr = &radeon_ring_generic_get_rptr,
1940 .get_wptr = &radeon_ring_generic_get_wptr,
1941 .set_wptr = &radeon_ring_generic_set_wptr,
1942};
1943
1944static struct radeon_asic_ring ci_cp_ring = {
1945 .ib_execute = &cik_ring_ib_execute,
1946 .ib_parse = &cik_ib_parse,
1947 .emit_fence = &cik_fence_compute_ring_emit,
1948 .emit_semaphore = &cik_semaphore_ring_emit,
1949 .cs_parse = NULL,
1950 .ring_test = &cik_ring_test,
1951 .ib_test = &cik_ib_test,
1952 .is_lockup = &cik_gfx_is_lockup,
1953 .vm_flush = &cik_vm_flush,
1954 .get_rptr = &cik_compute_ring_get_rptr,
1955 .get_wptr = &cik_compute_ring_get_wptr,
1956 .set_wptr = &cik_compute_ring_set_wptr,
1957};
1958
1959static struct radeon_asic_ring ci_dma_ring = {
1960 .ib_execute = &cik_sdma_ring_ib_execute,
1961 .ib_parse = &cik_ib_parse,
1962 .emit_fence = &cik_sdma_fence_ring_emit,
1963 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1964 .cs_parse = NULL,
1965 .ring_test = &cik_sdma_ring_test,
1966 .ib_test = &cik_sdma_ib_test,
1967 .is_lockup = &cik_sdma_is_lockup,
1968 .vm_flush = &cik_dma_vm_flush,
1969 .get_rptr = &radeon_ring_generic_get_rptr,
1970 .get_wptr = &radeon_ring_generic_get_wptr,
1971 .set_wptr = &radeon_ring_generic_set_wptr,
1972};
1973
2308static struct radeon_asic ci_asic = { 1974static struct radeon_asic ci_asic = {
2309 .init = &cik_init, 1975 .init = &cik_init,
2310 .fini = &cik_fini, 1976 .fini = &cik_fini,
@@ -2328,88 +1994,12 @@ static struct radeon_asic ci_asic = {
2328 .set_page = &cik_vm_set_page, 1994 .set_page = &cik_vm_set_page,
2329 }, 1995 },
2330 .ring = { 1996 .ring = {
2331 [RADEON_RING_TYPE_GFX_INDEX] = { 1997 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2332 .ib_execute = &cik_ring_ib_execute, 1998 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2333 .ib_parse = &cik_ib_parse, 1999 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2334 .emit_fence = &cik_fence_gfx_ring_emit, 2000 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2335 .emit_semaphore = &cik_semaphore_ring_emit, 2001 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2336 .cs_parse = NULL, 2002 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2337 .ring_test = &cik_ring_test,
2338 .ib_test = &cik_ib_test,
2339 .is_lockup = &cik_gfx_is_lockup,
2340 .vm_flush = &cik_vm_flush,
2341 .get_rptr = &radeon_ring_generic_get_rptr,
2342 .get_wptr = &radeon_ring_generic_get_wptr,
2343 .set_wptr = &radeon_ring_generic_set_wptr,
2344 },
2345 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2346 .ib_execute = &cik_ring_ib_execute,
2347 .ib_parse = &cik_ib_parse,
2348 .emit_fence = &cik_fence_compute_ring_emit,
2349 .emit_semaphore = &cik_semaphore_ring_emit,
2350 .cs_parse = NULL,
2351 .ring_test = &cik_ring_test,
2352 .ib_test = &cik_ib_test,
2353 .is_lockup = &cik_gfx_is_lockup,
2354 .vm_flush = &cik_vm_flush,
2355 .get_rptr = &cik_compute_ring_get_rptr,
2356 .get_wptr = &cik_compute_ring_get_wptr,
2357 .set_wptr = &cik_compute_ring_set_wptr,
2358 },
2359 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2360 .ib_execute = &cik_ring_ib_execute,
2361 .ib_parse = &cik_ib_parse,
2362 .emit_fence = &cik_fence_compute_ring_emit,
2363 .emit_semaphore = &cik_semaphore_ring_emit,
2364 .cs_parse = NULL,
2365 .ring_test = &cik_ring_test,
2366 .ib_test = &cik_ib_test,
2367 .is_lockup = &cik_gfx_is_lockup,
2368 .vm_flush = &cik_vm_flush,
2369 .get_rptr = &cik_compute_ring_get_rptr,
2370 .get_wptr = &cik_compute_ring_get_wptr,
2371 .set_wptr = &cik_compute_ring_set_wptr,
2372 },
2373 [R600_RING_TYPE_DMA_INDEX] = {
2374 .ib_execute = &cik_sdma_ring_ib_execute,
2375 .ib_parse = &cik_ib_parse,
2376 .emit_fence = &cik_sdma_fence_ring_emit,
2377 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2378 .cs_parse = NULL,
2379 .ring_test = &cik_sdma_ring_test,
2380 .ib_test = &cik_sdma_ib_test,
2381 .is_lockup = &cik_sdma_is_lockup,
2382 .vm_flush = &cik_dma_vm_flush,
2383 .get_rptr = &radeon_ring_generic_get_rptr,
2384 .get_wptr = &radeon_ring_generic_get_wptr,
2385 .set_wptr = &radeon_ring_generic_set_wptr,
2386 },
2387 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2388 .ib_execute = &cik_sdma_ring_ib_execute,
2389 .ib_parse = &cik_ib_parse,
2390 .emit_fence = &cik_sdma_fence_ring_emit,
2391 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2392 .cs_parse = NULL,
2393 .ring_test = &cik_sdma_ring_test,
2394 .ib_test = &cik_sdma_ib_test,
2395 .is_lockup = &cik_sdma_is_lockup,
2396 .vm_flush = &cik_dma_vm_flush,
2397 .get_rptr = &radeon_ring_generic_get_rptr,
2398 .get_wptr = &radeon_ring_generic_get_wptr,
2399 .set_wptr = &radeon_ring_generic_set_wptr,
2400 },
2401 [R600_RING_TYPE_UVD_INDEX] = {
2402 .ib_execute = &r600_uvd_ib_execute,
2403 .emit_fence = &r600_uvd_fence_emit,
2404 .emit_semaphore = &cayman_uvd_semaphore_emit,
2405 .cs_parse = &radeon_uvd_cs_parse,
2406 .ring_test = &r600_uvd_ring_test,
2407 .ib_test = &r600_uvd_ib_test,
2408 .is_lockup = &radeon_ring_test_lockup,
2409 .get_rptr = &radeon_ring_generic_get_rptr,
2410 .get_wptr = &radeon_ring_generic_get_wptr,
2411 .set_wptr = &radeon_ring_generic_set_wptr,
2412 }
2413 }, 2003 },
2414 .irq = { 2004 .irq = {
2415 .set = &cik_irq_set, 2005 .set = &cik_irq_set,
@@ -2502,88 +2092,12 @@ static struct radeon_asic kv_asic = {
2502 .set_page = &cik_vm_set_page, 2092 .set_page = &cik_vm_set_page,
2503 }, 2093 },
2504 .ring = { 2094 .ring = {
2505 [RADEON_RING_TYPE_GFX_INDEX] = { 2095 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2506 .ib_execute = &cik_ring_ib_execute, 2096 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2507 .ib_parse = &cik_ib_parse, 2097 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2508 .emit_fence = &cik_fence_gfx_ring_emit, 2098 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2509 .emit_semaphore = &cik_semaphore_ring_emit, 2099 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2510 .cs_parse = NULL, 2100 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2511 .ring_test = &cik_ring_test,
2512 .ib_test = &cik_ib_test,
2513 .is_lockup = &cik_gfx_is_lockup,
2514 .vm_flush = &cik_vm_flush,
2515 .get_rptr = &radeon_ring_generic_get_rptr,
2516 .get_wptr = &radeon_ring_generic_get_wptr,
2517 .set_wptr = &radeon_ring_generic_set_wptr,
2518 },
2519 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2520 .ib_execute = &cik_ring_ib_execute,
2521 .ib_parse = &cik_ib_parse,
2522 .emit_fence = &cik_fence_compute_ring_emit,
2523 .emit_semaphore = &cik_semaphore_ring_emit,
2524 .cs_parse = NULL,
2525 .ring_test = &cik_ring_test,
2526 .ib_test = &cik_ib_test,
2527 .is_lockup = &cik_gfx_is_lockup,
2528 .vm_flush = &cik_vm_flush,
2529 .get_rptr = &cik_compute_ring_get_rptr,
2530 .get_wptr = &cik_compute_ring_get_wptr,
2531 .set_wptr = &cik_compute_ring_set_wptr,
2532 },
2533 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2534 .ib_execute = &cik_ring_ib_execute,
2535 .ib_parse = &cik_ib_parse,
2536 .emit_fence = &cik_fence_compute_ring_emit,
2537 .emit_semaphore = &cik_semaphore_ring_emit,
2538 .cs_parse = NULL,
2539 .ring_test = &cik_ring_test,
2540 .ib_test = &cik_ib_test,
2541 .is_lockup = &cik_gfx_is_lockup,
2542 .vm_flush = &cik_vm_flush,
2543 .get_rptr = &cik_compute_ring_get_rptr,
2544 .get_wptr = &cik_compute_ring_get_wptr,
2545 .set_wptr = &cik_compute_ring_set_wptr,
2546 },
2547 [R600_RING_TYPE_DMA_INDEX] = {
2548 .ib_execute = &cik_sdma_ring_ib_execute,
2549 .ib_parse = &cik_ib_parse,
2550 .emit_fence = &cik_sdma_fence_ring_emit,
2551 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2552 .cs_parse = NULL,
2553 .ring_test = &cik_sdma_ring_test,
2554 .ib_test = &cik_sdma_ib_test,
2555 .is_lockup = &cik_sdma_is_lockup,
2556 .vm_flush = &cik_dma_vm_flush,
2557 .get_rptr = &radeon_ring_generic_get_rptr,
2558 .get_wptr = &radeon_ring_generic_get_wptr,
2559 .set_wptr = &radeon_ring_generic_set_wptr,
2560 },
2561 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2562 .ib_execute = &cik_sdma_ring_ib_execute,
2563 .ib_parse = &cik_ib_parse,
2564 .emit_fence = &cik_sdma_fence_ring_emit,
2565 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2566 .cs_parse = NULL,
2567 .ring_test = &cik_sdma_ring_test,
2568 .ib_test = &cik_sdma_ib_test,
2569 .is_lockup = &cik_sdma_is_lockup,
2570 .vm_flush = &cik_dma_vm_flush,
2571 .get_rptr = &radeon_ring_generic_get_rptr,
2572 .get_wptr = &radeon_ring_generic_get_wptr,
2573 .set_wptr = &radeon_ring_generic_set_wptr,
2574 },
2575 [R600_RING_TYPE_UVD_INDEX] = {
2576 .ib_execute = &r600_uvd_ib_execute,
2577 .emit_fence = &r600_uvd_fence_emit,
2578 .emit_semaphore = &cayman_uvd_semaphore_emit,
2579 .cs_parse = &radeon_uvd_cs_parse,
2580 .ring_test = &r600_uvd_ring_test,
2581 .ib_test = &r600_uvd_ib_test,
2582 .is_lockup = &radeon_ring_test_lockup,
2583 .get_rptr = &radeon_ring_generic_get_rptr,
2584 .get_wptr = &radeon_ring_generic_get_wptr,
2585 .set_wptr = &radeon_ring_generic_set_wptr,
2586 }
2587 }, 2101 },
2588 .irq = { 2102 .irq = {
2589 .set = &cik_irq_set, 2103 .set = &cik_irq_set,
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 5384fa42c16e..a56084410372 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -268,7 +268,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
268 return -EINVAL; 268 return -EINVAL;
269 269
270 /* we only support VM on some SI+ rings */ 270 /* we only support VM on some SI+ rings */
271 if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) && 271 if ((p->rdev->asic->ring[p->ring]->cs_parse == NULL) &&
272 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { 272 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
273 DRM_ERROR("Ring %d requires VM!\n", p->ring); 273 DRM_ERROR("Ring %d requires VM!\n", p->ring);
274 return -EINVAL; 274 return -EINVAL;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 13:56:57 -0500