drm/radeon: add proper support for RADEON_VM_BLOCK_SIZE v2

This patch makes it possible to decide how many address
bits are spend on the page directory vs the page tables.

v2: remove unintended change

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

7 files changed, 9 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index dbb5b2e17c7c..8d0f1774efbc 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5378,6 +5378,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
                (u32)(rdev->dummy_page.addr >> 12));
         WREG32(VM_CONTEXT1_CNTL2, 4);
         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
+                                PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |
                                 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 213873270d5f..0b27ea08c299 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -482,6 +482,7 @@
 #define         READ_PROTECTION_FAULT_ENABLE_DEFAULT            (1 << 16)
 #define         WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT         (1 << 18)
 #define         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 19)
+#define         PAGE_TABLE_BLOCK_SIZE(x)                        (((x) & 0xF) << 24)
 #define VM_CONTEXT1_CNTL                                0x1414
 #define VM_CONTEXT0_CNTL2                               0x1430
 #define VM_CONTEXT1_CNTL2                               0x1434
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 5e8db9bccba1..1d3209ffbbdc 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1268,6 +1268,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
                (u32)(rdev->dummy_page.addr >> 12));
         WREG32(VM_CONTEXT1_CNTL2, 4);
         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
+                                PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |
                                 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index d996033c243e..2e12e4d69253 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -128,6 +128,7 @@
 #define         READ_PROTECTION_FAULT_ENABLE_DEFAULT            (1 << 16)
 #define         WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT         (1 << 18)
 #define         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 19)
+#define         PAGE_TABLE_BLOCK_SIZE(x)                        (((x) & 0xF) << 24)
 #define VM_CONTEXT1_CNTL                                0x1414
 #define VM_CONTEXT0_CNTL2                               0x1430
 #define VM_CONTEXT1_CNTL2                               0x1434
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
index f8d5b65932e5..a128a4fd64b3 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -964,6 +964,8 @@ void radeon_vm_bo_invalidate(struct radeon_device *rdev,
  */
 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
 {
+        const unsigned align = min(RADEON_VM_PTB_ALIGN_SIZE,
+                RADEON_VM_PTE_COUNT * 8);
         unsigned pd_size, pd_entries, pts_size;
         int r;
 
@@ -985,7 +987,7 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
                 return -ENOMEM;
         }
 
-        r = radeon_bo_create(rdev, pd_size, RADEON_VM_PTB_ALIGN_SIZE, false,
+        r = radeon_bo_create(rdev, pd_size, align, false,
                              RADEON_GEM_DOMAIN_VRAM, NULL,
                              &vm->page_directory);
         if (r)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 22ecbc07e9a6..9739d71cd0a2 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4095,6 +4095,7 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
                (u32)(rdev->dummy_page.addr >> 12));
         WREG32(VM_CONTEXT1_CNTL2, 4);
         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
+                                PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |
                                 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 683532f84931..da8f8674a552 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -362,6 +362,7 @@
 #define         READ_PROTECTION_FAULT_ENABLE_DEFAULT            (1 << 16)
 #define         WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT         (1 << 18)
 #define         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 19)
+#define         PAGE_TABLE_BLOCK_SIZE(x)                        (((x) & 0xF) << 24)
 #define VM_CONTEXT1_CNTL                                0x1414
 #define VM_CONTEXT0_CNTL2                               0x1430
 #define VM_CONTEXT1_CNTL2                               0x1434