aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm
diff options
context:
space:
mode:
authorAkshay Joshi <me@akshayjoshi.com>2011-08-16 15:34:10 -0400
committerKeith Packard <keithp@keithp.com>2011-09-19 21:01:47 -0400
commit0206e353a0416ad63ce07f53c807c2c725633b87 (patch)
tree4b3233535d2f3b9cf408c823b7a32773a8d971e7 /drivers/gpu/drm
parentb6fd41e29dea9c6753b1843a77e50433e6123bcb (diff)
Drivers: i915: Fix all space related issues.
Various issues involved with the space character were generating warnings in the checkpatch.pl file. This patch removes most of those warnings. Signed-off-by: Akshay Joshi <me@akshayjoshi.com> Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/dvo_ch7017.c2
-rw-r--r--drivers/gpu/drm/i915/dvo_ch7xxx.c4
-rw-r--r--drivers/gpu/drm/i915/dvo_ivch.c6
-rw-r--r--drivers/gpu/drm/i915/dvo_sil164.c2
-rw-r--r--drivers/gpu/drm/i915/dvo_tfp410.c14
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c38
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c44
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c16
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h70
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c12
-rw-r--r--drivers/gpu/drm/i915/i915_gem_debug.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem_evict.c2
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c6
-rw-r--r--drivers/gpu/drm/i915/i915_mem.c14
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h8
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c8
-rw-r--r--drivers/gpu/drm/i915/i915_trace.h46
-rw-r--r--drivers/gpu/drm/i915/intel_acpi.c2
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c4
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h2
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c222
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c26
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h12
-rw-r--r--drivers/gpu/drm/i915/intel_opregion.c90
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c146
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c6
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c76
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h8
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c228
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo_regs.h558
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c58
32 files changed, 867 insertions, 867 deletions
diff --git a/drivers/gpu/drm/i915/dvo_ch7017.c b/drivers/gpu/drm/i915/dvo_ch7017.c
index d3e8c540f778..1ca799a1e1fc 100644
--- a/drivers/gpu/drm/i915/dvo_ch7017.c
+++ b/drivers/gpu/drm/i915/dvo_ch7017.c
@@ -227,7 +227,7 @@ static bool ch7017_init(struct intel_dvo_device *dvo,
227 default: 227 default:
228 DRM_DEBUG_KMS("ch701x not detected, got %d: from %s " 228 DRM_DEBUG_KMS("ch701x not detected, got %d: from %s "
229 "slave %d.\n", 229 "slave %d.\n",
230 val, adapter->name,dvo->slave_addr); 230 val, adapter->name, dvo->slave_addr);
231 goto fail; 231 goto fail;
232 } 232 }
233 233
diff --git a/drivers/gpu/drm/i915/dvo_ch7xxx.c b/drivers/gpu/drm/i915/dvo_ch7xxx.c
index 7eaa94e4ff06..4a036600e806 100644
--- a/drivers/gpu/drm/i915/dvo_ch7xxx.c
+++ b/drivers/gpu/drm/i915/dvo_ch7xxx.c
@@ -111,7 +111,7 @@ static char *ch7xxx_get_id(uint8_t vid)
111/** Reads an 8 bit register */ 111/** Reads an 8 bit register */
112static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) 112static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
113{ 113{
114 struct ch7xxx_priv *ch7xxx= dvo->dev_priv; 114 struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
115 struct i2c_adapter *adapter = dvo->i2c_bus; 115 struct i2c_adapter *adapter = dvo->i2c_bus;
116 u8 out_buf[2]; 116 u8 out_buf[2];
117 u8 in_buf[2]; 117 u8 in_buf[2];
@@ -303,7 +303,7 @@ static void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
303 303
304 for (i = 0; i < CH7xxx_NUM_REGS; i++) { 304 for (i = 0; i < CH7xxx_NUM_REGS; i++) {
305 uint8_t val; 305 uint8_t val;
306 if ((i % 8) == 0 ) 306 if ((i % 8) == 0)
307 DRM_LOG_KMS("\n %02X: ", i); 307 DRM_LOG_KMS("\n %02X: ", i);
308 ch7xxx_readb(dvo, i, &val); 308 ch7xxx_readb(dvo, i, &val);
309 DRM_LOG_KMS("%02X ", val); 309 DRM_LOG_KMS("%02X ", val);
diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c
index a12ed9414cc7..04f2893d5e3c 100644
--- a/drivers/gpu/drm/i915/dvo_ivch.c
+++ b/drivers/gpu/drm/i915/dvo_ivch.c
@@ -344,8 +344,8 @@ static void ivch_mode_set(struct intel_dvo_device *dvo,
344 (adjusted_mode->hdisplay - 1)) >> 2; 344 (adjusted_mode->hdisplay - 1)) >> 2;
345 y_ratio = (((mode->vdisplay - 1) << 16) / 345 y_ratio = (((mode->vdisplay - 1) << 16) /
346 (adjusted_mode->vdisplay - 1)) >> 2; 346 (adjusted_mode->vdisplay - 1)) >> 2;
347 ivch_write (dvo, VR42, x_ratio); 347 ivch_write(dvo, VR42, x_ratio);
348 ivch_write (dvo, VR41, y_ratio); 348 ivch_write(dvo, VR41, y_ratio);
349 } else { 349 } else {
350 vr01 &= ~VR01_PANEL_FIT_ENABLE; 350 vr01 &= ~VR01_PANEL_FIT_ENABLE;
351 vr40 &= ~VR40_CLOCK_GATING_ENABLE; 351 vr40 &= ~VR40_CLOCK_GATING_ENABLE;
@@ -410,7 +410,7 @@ static void ivch_destroy(struct intel_dvo_device *dvo)
410 } 410 }
411} 411}
412 412
413struct intel_dvo_dev_ops ivch_ops= { 413struct intel_dvo_dev_ops ivch_ops = {
414 .init = ivch_init, 414 .init = ivch_init,
415 .dpms = ivch_dpms, 415 .dpms = ivch_dpms,
416 .mode_valid = ivch_mode_valid, 416 .mode_valid = ivch_mode_valid,
diff --git a/drivers/gpu/drm/i915/dvo_sil164.c b/drivers/gpu/drm/i915/dvo_sil164.c
index e4b4091df942..a0b13a6f619d 100644
--- a/drivers/gpu/drm/i915/dvo_sil164.c
+++ b/drivers/gpu/drm/i915/dvo_sil164.c
@@ -104,7 +104,7 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
104 104
105static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) 105static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
106{ 106{
107 struct sil164_priv *sil= dvo->dev_priv; 107 struct sil164_priv *sil = dvo->dev_priv;
108 struct i2c_adapter *adapter = dvo->i2c_bus; 108 struct i2c_adapter *adapter = dvo->i2c_bus;
109 uint8_t out_buf[2]; 109 uint8_t out_buf[2];
110 struct i2c_msg msg = { 110 struct i2c_msg msg = {
diff --git a/drivers/gpu/drm/i915/dvo_tfp410.c b/drivers/gpu/drm/i915/dvo_tfp410.c
index 8ab2855bb544..aa2cd3ec54aa 100644
--- a/drivers/gpu/drm/i915/dvo_tfp410.c
+++ b/drivers/gpu/drm/i915/dvo_tfp410.c
@@ -56,7 +56,7 @@
56#define TFP410_CTL_2_MDI (1<<0) 56#define TFP410_CTL_2_MDI (1<<0)
57 57
58#define TFP410_CTL_3 0x0A 58#define TFP410_CTL_3 0x0A
59#define TFP410_CTL_3_DK_MASK (0x7<<5) 59#define TFP410_CTL_3_DK_MASK (0x7<<5)
60#define TFP410_CTL_3_DK (1<<5) 60#define TFP410_CTL_3_DK (1<<5)
61#define TFP410_CTL_3_DKEN (1<<4) 61#define TFP410_CTL_3_DKEN (1<<4)
62#define TFP410_CTL_3_CTL_MASK (0x7<<1) 62#define TFP410_CTL_3_CTL_MASK (0x7<<1)
@@ -225,12 +225,12 @@ static void tfp410_mode_set(struct intel_dvo_device *dvo,
225 struct drm_display_mode *mode, 225 struct drm_display_mode *mode,
226 struct drm_display_mode *adjusted_mode) 226 struct drm_display_mode *adjusted_mode)
227{ 227{
228 /* As long as the basics are set up, since we don't have clock dependencies 228 /* As long as the basics are set up, since we don't have clock dependencies
229 * in the mode setup, we can just leave the registers alone and everything 229 * in the mode setup, we can just leave the registers alone and everything
230 * will work fine. 230 * will work fine.
231 */ 231 */
232 /* don't do much */ 232 /* don't do much */
233 return; 233 return;
234} 234}
235 235
236/* set the tfp410 power state */ 236/* set the tfp410 power state */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3c395a59da35..8e95d66800b0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -98,12 +98,12 @@ static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98 98
99static const char *get_tiling_flag(struct drm_i915_gem_object *obj) 99static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
100{ 100{
101 switch (obj->tiling_mode) { 101 switch (obj->tiling_mode) {
102 default: 102 default:
103 case I915_TILING_NONE: return " "; 103 case I915_TILING_NONE: return " ";
104 case I915_TILING_X: return "X"; 104 case I915_TILING_X: return "X";
105 case I915_TILING_Y: return "Y"; 105 case I915_TILING_Y: return "Y";
106 } 106 }
107} 107}
108 108
109static const char *cache_level_str(int type) 109static const char *cache_level_str(int type)
@@ -217,7 +217,7 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data)
217 ++mappable_count; \ 217 ++mappable_count; \
218 } \ 218 } \
219 } \ 219 } \
220} while(0) 220} while (0)
221 221
222static int i915_gem_object_info(struct seq_file *m, void* data) 222static int i915_gem_object_info(struct seq_file *m, void* data)
223{ 223{
@@ -1293,12 +1293,12 @@ i915_wedged_read(struct file *filp,
1293 char buf[80]; 1293 char buf[80];
1294 int len; 1294 int len;
1295 1295
1296 len = snprintf(buf, sizeof (buf), 1296 len = snprintf(buf, sizeof(buf),
1297 "wedged : %d\n", 1297 "wedged : %d\n",
1298 atomic_read(&dev_priv->mm.wedged)); 1298 atomic_read(&dev_priv->mm.wedged));
1299 1299
1300 if (len > sizeof (buf)) 1300 if (len > sizeof(buf))
1301 len = sizeof (buf); 1301 len = sizeof(buf);
1302 1302
1303 return simple_read_from_buffer(ubuf, max, ppos, buf, len); 1303 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1304} 1304}
@@ -1314,7 +1314,7 @@ i915_wedged_write(struct file *filp,
1314 int val = 1; 1314 int val = 1;
1315 1315
1316 if (cnt > 0) { 1316 if (cnt > 0) {
1317 if (cnt > sizeof (buf) - 1) 1317 if (cnt > sizeof(buf) - 1)
1318 return -EINVAL; 1318 return -EINVAL;
1319 1319
1320 if (copy_from_user(buf, ubuf, cnt)) 1320 if (copy_from_user(buf, ubuf, cnt))
@@ -1357,11 +1357,11 @@ i915_max_freq_read(struct file *filp,
1357 char buf[80]; 1357 char buf[80];
1358 int len; 1358 int len;
1359 1359
1360 len = snprintf(buf, sizeof (buf), 1360 len = snprintf(buf, sizeof(buf),
1361 "max freq: %d\n", dev_priv->max_delay * 50); 1361 "max freq: %d\n", dev_priv->max_delay * 50);
1362 1362
1363 if (len > sizeof (buf)) 1363 if (len > sizeof(buf))
1364 len = sizeof (buf); 1364 len = sizeof(buf);
1365 1365
1366 return simple_read_from_buffer(ubuf, max, ppos, buf, len); 1366 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1367} 1367}
@@ -1378,7 +1378,7 @@ i915_max_freq_write(struct file *filp,
1378 int val = 1; 1378 int val = 1;
1379 1379
1380 if (cnt > 0) { 1380 if (cnt > 0) {
1381 if (cnt > sizeof (buf) - 1) 1381 if (cnt > sizeof(buf) - 1)
1382 return -EINVAL; 1382 return -EINVAL;
1383 1383
1384 if (copy_from_user(buf, ubuf, cnt)) 1384 if (copy_from_user(buf, ubuf, cnt))
@@ -1432,12 +1432,12 @@ i915_cache_sharing_read(struct file *filp,
1432 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 1432 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1433 mutex_unlock(&dev_priv->dev->struct_mutex); 1433 mutex_unlock(&dev_priv->dev->struct_mutex);
1434 1434
1435 len = snprintf(buf, sizeof (buf), 1435 len = snprintf(buf, sizeof(buf),
1436 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >> 1436 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
1437 GEN6_MBC_SNPCR_SHIFT); 1437 GEN6_MBC_SNPCR_SHIFT);
1438 1438
1439 if (len > sizeof (buf)) 1439 if (len > sizeof(buf))
1440 len = sizeof (buf); 1440 len = sizeof(buf);
1441 1441
1442 return simple_read_from_buffer(ubuf, max, ppos, buf, len); 1442 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1443} 1443}
@@ -1455,7 +1455,7 @@ i915_cache_sharing_write(struct file *filp,
1455 int val = 1; 1455 int val = 1;
1456 1456
1457 if (cnt > 0) { 1457 if (cnt > 0) {
1458 if (cnt > sizeof (buf) - 1) 1458 if (cnt > sizeof(buf) - 1)
1459 return -EINVAL; 1459 return -EINVAL;
1460 1460
1461 if (copy_from_user(buf, ubuf, cnt)) 1461 if (copy_from_user(buf, ubuf, cnt))
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 8a3942c4f099..d76da389f521 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -884,7 +884,7 @@ static int i915_get_bridge_dev(struct drm_device *dev)
884{ 884{
885 struct drm_i915_private *dev_priv = dev->dev_private; 885 struct drm_i915_private *dev_priv = dev->dev_private;
886 886
887 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); 887 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
888 if (!dev_priv->bridge_dev) { 888 if (!dev_priv->bridge_dev) {
889 DRM_ERROR("bridge device not found\n"); 889 DRM_ERROR("bridge device not found\n");
890 return -1; 890 return -1;
@@ -1730,10 +1730,10 @@ static DEFINE_SPINLOCK(mchdev_lock);
1730 */ 1730 */
1731unsigned long i915_read_mch_val(void) 1731unsigned long i915_read_mch_val(void)
1732{ 1732{
1733 struct drm_i915_private *dev_priv; 1733 struct drm_i915_private *dev_priv;
1734 unsigned long chipset_val, graphics_val, ret = 0; 1734 unsigned long chipset_val, graphics_val, ret = 0;
1735 1735
1736 spin_lock(&mchdev_lock); 1736 spin_lock(&mchdev_lock);
1737 if (!i915_mch_dev) 1737 if (!i915_mch_dev)
1738 goto out_unlock; 1738 goto out_unlock;
1739 dev_priv = i915_mch_dev; 1739 dev_priv = i915_mch_dev;
@@ -1744,9 +1744,9 @@ unsigned long i915_read_mch_val(void)
1744 ret = chipset_val + graphics_val; 1744 ret = chipset_val + graphics_val;
1745 1745
1746out_unlock: 1746out_unlock:
1747 spin_unlock(&mchdev_lock); 1747 spin_unlock(&mchdev_lock);
1748 1748
1749 return ret; 1749 return ret;
1750} 1750}
1751EXPORT_SYMBOL_GPL(i915_read_mch_val); 1751EXPORT_SYMBOL_GPL(i915_read_mch_val);
1752 1752
@@ -1757,10 +1757,10 @@ EXPORT_SYMBOL_GPL(i915_read_mch_val);
1757 */ 1757 */
1758bool i915_gpu_raise(void) 1758bool i915_gpu_raise(void)
1759{ 1759{
1760 struct drm_i915_private *dev_priv; 1760 struct drm_i915_private *dev_priv;
1761 bool ret = true; 1761 bool ret = true;
1762 1762
1763 spin_lock(&mchdev_lock); 1763 spin_lock(&mchdev_lock);
1764 if (!i915_mch_dev) { 1764 if (!i915_mch_dev) {
1765 ret = false; 1765 ret = false;
1766 goto out_unlock; 1766 goto out_unlock;
@@ -1771,9 +1771,9 @@ bool i915_gpu_raise(void)
1771 dev_priv->max_delay--; 1771 dev_priv->max_delay--;
1772 1772
1773out_unlock: 1773out_unlock:
1774 spin_unlock(&mchdev_lock); 1774 spin_unlock(&mchdev_lock);
1775 1775
1776 return ret; 1776 return ret;
1777} 1777}
1778EXPORT_SYMBOL_GPL(i915_gpu_raise); 1778EXPORT_SYMBOL_GPL(i915_gpu_raise);
1779 1779
@@ -1785,10 +1785,10 @@ EXPORT_SYMBOL_GPL(i915_gpu_raise);
1785 */ 1785 */
1786bool i915_gpu_lower(void) 1786bool i915_gpu_lower(void)
1787{ 1787{
1788 struct drm_i915_private *dev_priv; 1788 struct drm_i915_private *dev_priv;
1789 bool ret = true; 1789 bool ret = true;
1790 1790
1791 spin_lock(&mchdev_lock); 1791 spin_lock(&mchdev_lock);
1792 if (!i915_mch_dev) { 1792 if (!i915_mch_dev) {
1793 ret = false; 1793 ret = false;
1794 goto out_unlock; 1794 goto out_unlock;
@@ -1799,9 +1799,9 @@ bool i915_gpu_lower(void)
1799 dev_priv->max_delay++; 1799 dev_priv->max_delay++;
1800 1800
1801out_unlock: 1801out_unlock:
1802 spin_unlock(&mchdev_lock); 1802 spin_unlock(&mchdev_lock);
1803 1803
1804 return ret; 1804 return ret;
1805} 1805}
1806EXPORT_SYMBOL_GPL(i915_gpu_lower); 1806EXPORT_SYMBOL_GPL(i915_gpu_lower);
1807 1807
@@ -1812,10 +1812,10 @@ EXPORT_SYMBOL_GPL(i915_gpu_lower);
1812 */ 1812 */
1813bool i915_gpu_busy(void) 1813bool i915_gpu_busy(void)
1814{ 1814{
1815 struct drm_i915_private *dev_priv; 1815 struct drm_i915_private *dev_priv;
1816 bool ret = false; 1816 bool ret = false;
1817 1817
1818 spin_lock(&mchdev_lock); 1818 spin_lock(&mchdev_lock);
1819 if (!i915_mch_dev) 1819 if (!i915_mch_dev)
1820 goto out_unlock; 1820 goto out_unlock;
1821 dev_priv = i915_mch_dev; 1821 dev_priv = i915_mch_dev;
@@ -1823,9 +1823,9 @@ bool i915_gpu_busy(void)
1823 ret = dev_priv->busy; 1823 ret = dev_priv->busy;
1824 1824
1825out_unlock: 1825out_unlock:
1826 spin_unlock(&mchdev_lock); 1826 spin_unlock(&mchdev_lock);
1827 1827
1828 return ret; 1828 return ret;
1829} 1829}
1830EXPORT_SYMBOL_GPL(i915_gpu_busy); 1830EXPORT_SYMBOL_GPL(i915_gpu_busy);
1831 1831
@@ -1837,10 +1837,10 @@ EXPORT_SYMBOL_GPL(i915_gpu_busy);
1837 */ 1837 */
1838bool i915_gpu_turbo_disable(void) 1838bool i915_gpu_turbo_disable(void)
1839{ 1839{
1840 struct drm_i915_private *dev_priv; 1840 struct drm_i915_private *dev_priv;
1841 bool ret = true; 1841 bool ret = true;
1842 1842
1843 spin_lock(&mchdev_lock); 1843 spin_lock(&mchdev_lock);
1844 if (!i915_mch_dev) { 1844 if (!i915_mch_dev) {
1845 ret = false; 1845 ret = false;
1846 goto out_unlock; 1846 goto out_unlock;
@@ -1853,9 +1853,9 @@ bool i915_gpu_turbo_disable(void)
1853 ret = false; 1853 ret = false;
1854 1854
1855out_unlock: 1855out_unlock:
1856 spin_unlock(&mchdev_lock); 1856 spin_unlock(&mchdev_lock);
1857 1857
1858 return ret; 1858 return ret;
1859} 1859}
1860EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 1860EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1861 1861
@@ -1948,7 +1948,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1948 1948
1949 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; 1949 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1950 1950
1951 dev_priv->mm.gtt_mapping = 1951 dev_priv->mm.gtt_mapping =
1952 io_mapping_create_wc(dev->agp->base, agp_size); 1952 io_mapping_create_wc(dev->agp->base, agp_size);
1953 if (dev_priv->mm.gtt_mapping == NULL) { 1953 if (dev_priv->mm.gtt_mapping == NULL) {
1954 ret = -EIO; 1954 ret = -EIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ce045a8cf82c..b79c6f14fb72 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -294,7 +294,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
294#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 294#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
295#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 295#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
296 296
297void intel_detect_pch (struct drm_device *dev) 297void intel_detect_pch(struct drm_device *dev)
298{ 298{
299 struct drm_i915_private *dev_priv = dev->dev_private; 299 struct drm_i915_private *dev_priv = dev->dev_private;
300 struct pci_dev *pch; 300 struct pci_dev *pch;
@@ -377,7 +377,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
377 377
378void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 378void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
379{ 379{
380 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES ) { 380 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
381 int loop = 500; 381 int loop = 500;
382 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 382 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
383 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 383 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
@@ -770,12 +770,12 @@ static int i915_pm_poweroff(struct device *dev)
770} 770}
771 771
772static const struct dev_pm_ops i915_pm_ops = { 772static const struct dev_pm_ops i915_pm_ops = {
773 .suspend = i915_pm_suspend, 773 .suspend = i915_pm_suspend,
774 .resume = i915_pm_resume, 774 .resume = i915_pm_resume,
775 .freeze = i915_pm_freeze, 775 .freeze = i915_pm_freeze,
776 .thaw = i915_pm_thaw, 776 .thaw = i915_pm_thaw,
777 .poweroff = i915_pm_poweroff, 777 .poweroff = i915_pm_poweroff,
778 .restore = i915_pm_resume, 778 .restore = i915_pm_resume,
779}; 779};
780 780
781static struct vm_operations_struct i915_gem_vm_ops = { 781static struct vm_operations_struct i915_gem_vm_ops = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7916bd97d5c1..32de06f0b172 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -226,26 +226,26 @@ struct drm_i915_display_funcs {
226 226
227struct intel_device_info { 227struct intel_device_info {
228 u8 gen; 228 u8 gen;
229 u8 is_mobile : 1; 229 u8 is_mobile:1;
230 u8 is_i85x : 1; 230 u8 is_i85x:1;
231 u8 is_i915g : 1; 231 u8 is_i915g:1;
232 u8 is_i945gm : 1; 232 u8 is_i945gm:1;
233 u8 is_g33 : 1; 233 u8 is_g33:1;
234 u8 need_gfx_hws : 1; 234 u8 need_gfx_hws:1;
235 u8 is_g4x : 1; 235 u8 is_g4x:1;
236 u8 is_pineview : 1; 236 u8 is_pineview:1;
237 u8 is_broadwater : 1; 237 u8 is_broadwater:1;
238 u8 is_crestline : 1; 238 u8 is_crestline:1;
239 u8 is_ivybridge : 1; 239 u8 is_ivybridge:1;
240 u8 has_fbc : 1; 240 u8 has_fbc:1;
241 u8 has_pipe_cxsr : 1; 241 u8 has_pipe_cxsr:1;
242 u8 has_hotplug : 1; 242 u8 has_hotplug:1;
243 u8 cursor_needs_physical : 1; 243 u8 cursor_needs_physical:1;
244 u8 has_overlay : 1; 244 u8 has_overlay:1;
245 u8 overlay_needs_physical : 1; 245 u8 overlay_needs_physical:1;
246 u8 supports_tv : 1; 246 u8 supports_tv:1;
247 u8 has_bsd_ring : 1; 247 u8 has_bsd_ring:1;
248 u8 has_blt_ring : 1; 248 u8 has_blt_ring:1;
249}; 249};
250 250
251enum no_fbc_reason { 251enum no_fbc_reason {
@@ -759,19 +759,19 @@ struct drm_i915_gem_object {
759 * (has pending rendering), and is not set if it's on inactive (ready 759 * (has pending rendering), and is not set if it's on inactive (ready
760 * to be unbound). 760 * to be unbound).
761 */ 761 */
762 unsigned int active : 1; 762 unsigned int active:1;
763 763
764 /** 764 /**
765 * This is set if the object has been written to since last bound 765 * This is set if the object has been written to since last bound
766 * to the GTT 766 * to the GTT
767 */ 767 */
768 unsigned int dirty : 1; 768 unsigned int dirty:1;
769 769
770 /** 770 /**
771 * This is set if the object has been written to since the last 771 * This is set if the object has been written to since the last
772 * GPU flush. 772 * GPU flush.
773 */ 773 */
774 unsigned int pending_gpu_write : 1; 774 unsigned int pending_gpu_write:1;
775 775
776 /** 776 /**
777 * Fence register bits (if any) for this object. Will be set 777 * Fence register bits (if any) for this object. Will be set
@@ -780,18 +780,18 @@ struct drm_i915_gem_object {
780 * 780 *
781 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) 781 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
782 */ 782 */
783 signed int fence_reg : 5; 783 signed int fence_reg:5;
784 784
785 /** 785 /**
786 * Advice: are the backing pages purgeable? 786 * Advice: are the backing pages purgeable?
787 */ 787 */
788 unsigned int madv : 2; 788 unsigned int madv:2;
789 789
790 /** 790 /**
791 * Current tiling mode for the object. 791 * Current tiling mode for the object.
792 */ 792 */
793 unsigned int tiling_mode : 2; 793 unsigned int tiling_mode:2;
794 unsigned int tiling_changed : 1; 794 unsigned int tiling_changed:1;
795 795
796 /** How many users have pinned this object in GTT space. The following 796 /** How many users have pinned this object in GTT space. The following
797 * users can each hold at most one reference: pwrite/pread, pin_ioctl 797 * users can each hold at most one reference: pwrite/pread, pin_ioctl
@@ -802,22 +802,22 @@ struct drm_i915_gem_object {
802 * 802 *
803 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 803 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
804 * bits with absolutely no headroom. So use 4 bits. */ 804 * bits with absolutely no headroom. So use 4 bits. */
805 unsigned int pin_count : 4; 805 unsigned int pin_count:4;
806#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 806#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
807 807
808 /** 808 /**
809 * Is the object at the current location in the gtt mappable and 809 * Is the object at the current location in the gtt mappable and
810 * fenceable? Used to avoid costly recalculations. 810 * fenceable? Used to avoid costly recalculations.
811 */ 811 */
812 unsigned int map_and_fenceable : 1; 812 unsigned int map_and_fenceable:1;
813 813
814 /** 814 /**
815 * Whether the current gtt mapping needs to be mappable (and isn't just 815 * Whether the current gtt mapping needs to be mappable (and isn't just
816 * mappable by accident). Track pin and fault separate for a more 816 * mappable by accident). Track pin and fault separate for a more
817 * accurate mappable working set. 817 * accurate mappable working set.
818 */ 818 */
819 unsigned int fault_mappable : 1; 819 unsigned int fault_mappable:1;
820 unsigned int pin_mappable : 1; 820 unsigned int pin_mappable:1;
821 821
822 /* 822 /*
823 * Is the GPU currently using a fence to access this buffer, 823 * Is the GPU currently using a fence to access this buffer,
@@ -1056,7 +1056,7 @@ i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1056void 1056void
1057i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1057i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1058 1058
1059void intel_enable_asle (struct drm_device *dev); 1059void intel_enable_asle(struct drm_device *dev);
1060 1060
1061#ifdef CONFIG_DEBUG_FS 1061#ifdef CONFIG_DEBUG_FS
1062extern void i915_destroy_error_state(struct drm_device *dev); 1062extern void i915_destroy_error_state(struct drm_device *dev);
@@ -1146,7 +1146,7 @@ int i915_gem_dumb_create(struct drm_file *file_priv,
1146int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1146int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1147 uint32_t handle, uint64_t *offset); 1147 uint32_t handle, uint64_t *offset);
1148int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1148int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1149 uint32_t handle); 1149 uint32_t handle);
1150/** 1150/**
1151 * Returns true if seq1 is later than seq2. 1151 * Returns true if seq1 is later than seq2.
1152 */ 1152 */
@@ -1303,8 +1303,8 @@ extern void intel_disable_fbc(struct drm_device *dev);
1303extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1303extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1304extern void ironlake_enable_rc6(struct drm_device *dev); 1304extern void ironlake_enable_rc6(struct drm_device *dev);
1305extern void gen6_set_rps(struct drm_device *dev, u8 val); 1305extern void gen6_set_rps(struct drm_device *dev, u8 val);
1306extern void intel_detect_pch (struct drm_device *dev); 1306extern void intel_detect_pch(struct drm_device *dev);
1307extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); 1307extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1308 1308
1309/* overlay */ 1309/* overlay */
1310#ifdef CONFIG_DEBUG_FS 1310#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a546a71fb060..179642e38e3a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -179,7 +179,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
179 mutex_unlock(&dev->struct_mutex); 179 mutex_unlock(&dev->struct_mutex);
180 180
181 args->aper_size = dev_priv->mm.gtt_total; 181 args->aper_size = dev_priv->mm.gtt_total;
182 args->aper_available_size = args->aper_size -pinned; 182 args->aper_available_size = args->aper_size - pinned;
183 183
184 return 0; 184 return 0;
185} 185}
@@ -1856,7 +1856,7 @@ void i915_gem_reset(struct drm_device *dev)
1856 * lost bo to the inactive list. 1856 * lost bo to the inactive list.
1857 */ 1857 */
1858 while (!list_empty(&dev_priv->mm.flushing_list)) { 1858 while (!list_empty(&dev_priv->mm.flushing_list)) {
1859 obj= list_first_entry(&dev_priv->mm.flushing_list, 1859 obj = list_first_entry(&dev_priv->mm.flushing_list,
1860 struct drm_i915_gem_object, 1860 struct drm_i915_gem_object,
1861 mm_list); 1861 mm_list);
1862 1862
@@ -1922,7 +1922,7 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1922 while (!list_empty(&ring->active_list)) { 1922 while (!list_empty(&ring->active_list)) {
1923 struct drm_i915_gem_object *obj; 1923 struct drm_i915_gem_object *obj;
1924 1924
1925 obj= list_first_entry(&ring->active_list, 1925 obj = list_first_entry(&ring->active_list,
1926 struct drm_i915_gem_object, 1926 struct drm_i915_gem_object,
1927 ring_list); 1927 ring_list);
1928 1928
@@ -2882,7 +2882,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2882 2882
2883 fenceable = 2883 fenceable =
2884 obj->gtt_space->size == fence_size && 2884 obj->gtt_space->size == fence_size &&
2885 (obj->gtt_space->start & (fence_alignment -1)) == 0; 2885 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2886 2886
2887 mappable = 2887 mappable =
2888 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; 2888 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
@@ -3598,7 +3598,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3598 */ 3598 */
3599 request = kzalloc(sizeof(*request), GFP_KERNEL); 3599 request = kzalloc(sizeof(*request), GFP_KERNEL);
3600 if (request) 3600 if (request)
3601 ret = i915_add_request(obj->ring, NULL,request); 3601 ret = i915_add_request(obj->ring, NULL, request);
3602 else 3602 else
3603 ret = -ENOMEM; 3603 ret = -ENOMEM;
3604 } 3604 }
@@ -3623,7 +3623,7 @@ int
3623i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 3623i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3624 struct drm_file *file_priv) 3624 struct drm_file *file_priv)
3625{ 3625{
3626 return i915_gem_ring_throttle(dev, file_priv); 3626 return i915_gem_ring_throttle(dev, file_priv);
3627} 3627}
3628 3628
3629int 3629int
diff --git a/drivers/gpu/drm/i915/i915_gem_debug.c b/drivers/gpu/drm/i915/i915_gem_debug.c
index 8da1899bd24f..ac908757e176 100644
--- a/drivers/gpu/drm/i915/i915_gem_debug.c
+++ b/drivers/gpu/drm/i915/i915_gem_debug.c
@@ -72,7 +72,7 @@ i915_verify_lists(struct drm_device *dev)
72 break; 72 break;
73 } else if (!obj->active || 73 } else if (!obj->active ||
74 (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 || 74 (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 ||
75 list_empty(&obj->gpu_write_list)){ 75 list_empty(&obj->gpu_write_list)) {
76 DRM_ERROR("invalid flushing %p (a %d w %x gwl %d)\n", 76 DRM_ERROR("invalid flushing %p (a %d w %x gwl %d)\n",
77 obj, 77 obj,
78 obj->active, 78 obj->active,
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index da05a2692a75..ead5d00f91b0 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -122,7 +122,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size,
122 goto found; 122 goto found;
123 } 123 }
124 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { 124 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
125 if (! obj->base.write_domain || obj->pin_count) 125 if (!obj->base.write_domain || obj->pin_count)
126 continue; 126 continue;
127 127
128 if (mark_free(obj, &unwind_list)) 128 if (mark_free(obj, &unwind_list))
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9cbb0cd8f46a..012732b6ec25 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -711,7 +711,7 @@ i915_error_object_create(struct drm_i915_private *dev_priv,
711 711
712 page_count = src->base.size / PAGE_SIZE; 712 page_count = src->base.size / PAGE_SIZE;
713 713
714 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); 714 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
715 if (dst == NULL) 715 if (dst == NULL)
716 return NULL; 716 return NULL;
717 717
@@ -1493,7 +1493,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1493 1493
1494 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1494 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1495 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1495 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1496 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); 1496 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1497 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1497 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1498 1498
1499 return 0; 1499 return 0;
@@ -1541,7 +1541,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1541 1541
1542 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1542 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1543 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1543 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1544 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); 1544 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1545 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1545 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1546} 1546}
1547 1547
diff --git a/drivers/gpu/drm/i915/i915_mem.c b/drivers/gpu/drm/i915/i915_mem.c
index 83b7b81bb2b8..cc8f6d49cf20 100644
--- a/drivers/gpu/drm/i915/i915_mem.c
+++ b/drivers/gpu/drm/i915/i915_mem.c
@@ -202,7 +202,7 @@ static int init_heap(struct mem_block **heap, int start, int size)
202 blocks->next = blocks->prev = *heap; 202 blocks->next = blocks->prev = *heap;
203 203
204 memset(*heap, 0, sizeof(**heap)); 204 memset(*heap, 0, sizeof(**heap));
205 (*heap)->file_priv = (struct drm_file *) - 1; 205 (*heap)->file_priv = (struct drm_file *) -1;
206 (*heap)->next = (*heap)->prev = blocks; 206 (*heap)->next = (*heap)->prev = blocks;
207 return 0; 207 return 0;
208} 208}
@@ -359,19 +359,19 @@ int i915_mem_init_heap(struct drm_device *dev, void *data,
359 return init_heap(heap, initheap->start, initheap->size); 359 return init_heap(heap, initheap->start, initheap->size);
360} 360}
361 361
362int i915_mem_destroy_heap( struct drm_device *dev, void *data, 362int i915_mem_destroy_heap(struct drm_device *dev, void *data,
363 struct drm_file *file_priv ) 363 struct drm_file *file_priv)
364{ 364{
365 drm_i915_private_t *dev_priv = dev->dev_private; 365 drm_i915_private_t *dev_priv = dev->dev_private;
366 drm_i915_mem_destroy_heap_t *destroyheap = data; 366 drm_i915_mem_destroy_heap_t *destroyheap = data;
367 struct mem_block **heap; 367 struct mem_block **heap;
368 368
369 if ( !dev_priv ) { 369 if (!dev_priv) {
370 DRM_ERROR( "called with no initialization\n" ); 370 DRM_ERROR("called with no initialization\n");
371 return -EINVAL; 371 return -EINVAL;
372 } 372 }
373 373
374 heap = get_heap( dev_priv, destroyheap->region ); 374 heap = get_heap(dev_priv, destroyheap->region);
375 if (!heap) { 375 if (!heap) {
376 DRM_ERROR("get_heap failed"); 376 DRM_ERROR("get_heap failed");
377 return -EFAULT; 377 return -EFAULT;
@@ -382,6 +382,6 @@ int i915_mem_destroy_heap( struct drm_device *dev, void *data,
382 return -EFAULT; 382 return -EFAULT;
383 } 383 }
384 384
385 i915_mem_takedown( heap ); 385 i915_mem_takedown(heap);
386 return 0; 386 return 0;
387} 387}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 542453f7498c..8d9fce1ef0b0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -156,7 +156,7 @@
156#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 156#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
157#define MI_SUSPEND_FLUSH_EN (1<<0) 157#define MI_SUSPEND_FLUSH_EN (1<<0)
158#define MI_REPORT_HEAD MI_INSTR(0x07, 0) 158#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
159#define MI_OVERLAY_FLIP MI_INSTR(0x11,0) 159#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
160#define MI_OVERLAY_CONTINUE (0x0<<21) 160#define MI_OVERLAY_CONTINUE (0x0<<21)
161#define MI_OVERLAY_ON (0x1<<21) 161#define MI_OVERLAY_ON (0x1<<21)
162#define MI_OVERLAY_OFF (0x2<<21) 162#define MI_OVERLAY_OFF (0x2<<21)
@@ -470,7 +470,7 @@
470 470
471/* Enables non-sequential data reads through arbiter 471/* Enables non-sequential data reads through arbiter
472 */ 472 */
473#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 473#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
474 474
475/* Disable FSB snooping of cacheable write cycles from binner/render 475/* Disable FSB snooping of cacheable write cycles from binner/render
476 * command stream 476 * command stream
@@ -626,7 +626,7 @@
626 626
627#define ILK_DISPLAY_CHICKEN1 0x42000 627#define ILK_DISPLAY_CHICKEN1 0x42000
628#define ILK_FBCQ_DIS (1<<22) 628#define ILK_FBCQ_DIS (1<<22)
629#define ILK_PABSTRETCH_DIS (1<<21) 629#define ILK_PABSTRETCH_DIS (1<<21)
630 630
631 631
632/* 632/*
@@ -2358,7 +2358,7 @@
2358 2358
2359#define DSPFW1 0x70034 2359#define DSPFW1 0x70034
2360#define DSPFW_SR_SHIFT 23 2360#define DSPFW_SR_SHIFT 23
2361#define DSPFW_SR_MASK (0x1ff<<23) 2361#define DSPFW_SR_MASK (0x1ff<<23)
2362#define DSPFW_CURSORB_SHIFT 16 2362#define DSPFW_CURSORB_SHIFT 16
2363#define DSPFW_CURSORB_MASK (0x3f<<16) 2363#define DSPFW_CURSORB_MASK (0x3f<<16)
2364#define DSPFW_PLANEB_SHIFT 8 2364#define DSPFW_PLANEB_SHIFT 8
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index f10742359ec9..f8f602d76650 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -60,7 +60,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
60 else 60 else
61 array = dev_priv->save_palette_b; 61 array = dev_priv->save_palette_b;
62 62
63 for(i = 0; i < 256; i++) 63 for (i = 0; i < 256; i++)
64 array[i] = I915_READ(reg + (i << 2)); 64 array[i] = I915_READ(reg + (i << 2));
65} 65}
66 66
@@ -82,7 +82,7 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
82 else 82 else
83 array = dev_priv->save_palette_b; 83 array = dev_priv->save_palette_b;
84 84
85 for(i = 0; i < 256; i++) 85 for (i = 0; i < 256; i++)
86 I915_WRITE(reg + (i << 2), array[i]); 86 I915_WRITE(reg + (i << 2), array[i]);
87} 87}
88 88
@@ -887,10 +887,10 @@ int i915_restore_state(struct drm_device *dev)
887 mutex_lock(&dev->struct_mutex); 887 mutex_lock(&dev->struct_mutex);
888 888
889 /* Cache mode state */ 889 /* Cache mode state */
890 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 890 I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
891 891
892 /* Memory arbitration state */ 892 /* Memory arbitration state */
893 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); 893 I915_WRITE(MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
894 894
895 for (i = 0; i < 16; i++) { 895 for (i = 0; i < 16; i++) {
896 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); 896 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index d623fefbfaca..dac7bba4d9da 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -385,29 +385,29 @@ TRACE_EVENT(i915_flip_complete,
385); 385);
386 386
387TRACE_EVENT(i915_reg_rw, 387TRACE_EVENT(i915_reg_rw,
388 TP_PROTO(bool write, u32 reg, u64 val, int len), 388 TP_PROTO(bool write, u32 reg, u64 val, int len),
389 389
390 TP_ARGS(write, reg, val, len), 390 TP_ARGS(write, reg, val, len),
391 391
392 TP_STRUCT__entry( 392 TP_STRUCT__entry(
393 __field(u64, val) 393 __field(u64, val)
394 __field(u32, reg) 394 __field(u32, reg)
395 __field(u16, write) 395 __field(u16, write)
396 __field(u16, len) 396 __field(u16, len)
397 ), 397 ),
398 398
399 TP_fast_assign( 399 TP_fast_assign(
400 __entry->val = (u64)val; 400 __entry->val = (u64)val;
401 __entry->reg = reg; 401 __entry->reg = reg;
402 __entry->write = write; 402 __entry->write = write;
403 __entry->len = len; 403 __entry->len = len;
404 ), 404 ),
405 405
406 TP_printk("%s reg=0x%x, len=%d, val=(0x%x, 0x%x)", 406 TP_printk("%s reg=0x%x, len=%d, val=(0x%x, 0x%x)",
407 __entry->write ? "write" : "read", 407 __entry->write ? "write" : "read",
408 __entry->reg, __entry->len, 408 __entry->reg, __entry->len,
409 (u32)(__entry->val & 0xffffffff), 409 (u32)(__entry->val & 0xffffffff),
410 (u32)(__entry->val >> 32)) 410 (u32)(__entry->val >> 32))
411); 411);
412 412
413#endif /* _I915_TRACE_H_ */ 413#endif /* _I915_TRACE_H_ */
diff --git a/drivers/gpu/drm/i915/intel_acpi.c b/drivers/gpu/drm/i915/intel_acpi.c
index 2cb8e0b9f1ee..cb912106d1a2 100644
--- a/drivers/gpu/drm/i915/intel_acpi.c
+++ b/drivers/gpu/drm/i915/intel_acpi.c
@@ -64,7 +64,7 @@ static int intel_dsm(acpi_handle handle, int func, int arg)
64 64
65 case ACPI_TYPE_BUFFER: 65 case ACPI_TYPE_BUFFER:
66 if (obj->buffer.length == 4) { 66 if (obj->buffer.length == 4) {
67 result =(obj->buffer.pointer[0] | 67 result = (obj->buffer.pointer[0] |
68 (obj->buffer.pointer[1] << 8) | 68 (obj->buffer.pointer[1] << 8) |
69 (obj->buffer.pointer[2] << 16) | 69 (obj->buffer.pointer[2] << 16) |
70 (obj->buffer.pointer[3] << 24)); 70 (obj->buffer.pointer[3] << 24));
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 61abef8a8119..33378da63fdb 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -381,7 +381,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
381 if (p_child->dvo_port != DEVICE_PORT_DVOB && 381 if (p_child->dvo_port != DEVICE_PORT_DVOB &&
382 p_child->dvo_port != DEVICE_PORT_DVOC) { 382 p_child->dvo_port != DEVICE_PORT_DVOC) {
383 /* skip the incorrect SDVO port */ 383 /* skip the incorrect SDVO port */
384 DRM_DEBUG_KMS("Incorrect SDVO port. Skip it \n"); 384 DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n");
385 continue; 385 continue;
386 } 386 }
387 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on" 387 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
@@ -564,7 +564,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
564 count++; 564 count++;
565 } 565 }
566 if (!count) { 566 if (!count) {
567 DRM_DEBUG_KMS("no child dev is parsed from VBT \n"); 567 DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
568 return; 568 return;
569 } 569 }
570 dev_priv->child_dev = kzalloc(sizeof(*p_child) * count, GFP_KERNEL); 570 dev_priv->child_dev = kzalloc(sizeof(*p_child) * count, GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 5f8e4edcbbb9..c2e38feb7899 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -240,7 +240,7 @@ struct bdb_general_definitions {
240 * And the device num is related with the size of general definition 240 * And the device num is related with the size of general definition
241 * block. It is obtained by using the following formula: 241 * block. It is obtained by using the following formula:
242 * number = (block_size - sizeof(bdb_general_definitions))/ 242 * number = (block_size - sizeof(bdb_general_definitions))/
243 * sizeof(child_device_config); 243 * sizeof(child_device_config);
244 */ 244 */
245 struct child_device_config devices[0]; 245 struct child_device_config devices[0];
246} __attribute__((packed)); 246} __attribute__((packed));
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 0979d8877880..451534cb44de 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -69,7 +69,7 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
69 temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 69 temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
70 temp &= ~ADPA_DAC_ENABLE; 70 temp &= ~ADPA_DAC_ENABLE;
71 71
72 switch(mode) { 72 switch (mode) {
73 case DRM_MODE_DPMS_ON: 73 case DRM_MODE_DPMS_ON:
74 temp |= ADPA_DAC_ENABLE; 74 temp |= ADPA_DAC_ENABLE;
75 break; 75 break;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 56a8554d9039..c829875ac63f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -42,39 +42,39 @@
42 42
43#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) 43#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 44
45bool intel_pipe_has_type (struct drm_crtc *crtc, int type); 45bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
46static void intel_update_watermarks(struct drm_device *dev); 46static void intel_update_watermarks(struct drm_device *dev);
47static void intel_increase_pllclock(struct drm_crtc *crtc); 47static void intel_increase_pllclock(struct drm_crtc *crtc);
48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49 49
50typedef struct { 50typedef struct {
51 /* given values */ 51 /* given values */
52 int n; 52 int n;
53 int m1, m2; 53 int m1, m2;
54 int p1, p2; 54 int p1, p2;
55 /* derived values */ 55 /* derived values */
56 int dot; 56 int dot;
57 int vco; 57 int vco;
58 int m; 58 int m;
59 int p; 59 int p;
60} intel_clock_t; 60} intel_clock_t;
61 61
62typedef struct { 62typedef struct {
63 int min, max; 63 int min, max;
64} intel_range_t; 64} intel_range_t;
65 65
66typedef struct { 66typedef struct {
67 int dot_limit; 67 int dot_limit;
68 int p2_slow, p2_fast; 68 int p2_slow, p2_fast;
69} intel_p2_t; 69} intel_p2_t;
70 70
71#define INTEL_P2_NUM 2 71#define INTEL_P2_NUM 2
72typedef struct intel_limit intel_limit_t; 72typedef struct intel_limit intel_limit_t;
73struct intel_limit { 73struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1; 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2; 75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, 76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *); 77 int, int, intel_clock_t *);
78}; 78};
79 79
80/* FDI */ 80/* FDI */
@@ -105,56 +105,56 @@ intel_fdi_link_freq(struct drm_device *dev)
105} 105}
106 106
107static const intel_limit_t intel_limits_i8xx_dvo = { 107static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 }, 108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 }, 109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 }, 110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 }, 111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 }, 112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 }, 113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 }, 114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 }, 115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000, 116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 }, 117 .p2_slow = 4, .p2_fast = 2 },
118 .find_pll = intel_find_best_PLL, 118 .find_pll = intel_find_best_PLL,
119}; 119};
120 120
121static const intel_limit_t intel_limits_i8xx_lvds = { 121static const intel_limit_t intel_limits_i8xx_lvds = {
122 .dot = { .min = 25000, .max = 350000 }, 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 }, 123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 }, 124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 }, 125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 }, 126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 }, 127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 }, 128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 }, 129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000, 130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 }, 131 .p2_slow = 14, .p2_fast = 7 },
132 .find_pll = intel_find_best_PLL, 132 .find_pll = intel_find_best_PLL,
133}; 133};
134 134
135static const intel_limit_t intel_limits_i9xx_sdvo = { 135static const intel_limit_t intel_limits_i9xx_sdvo = {
136 .dot = { .min = 20000, .max = 400000 }, 136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 }, 137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 }, 138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 }, 139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 }, 140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 }, 141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 }, 142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 }, 143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000, 144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 }, 145 .p2_slow = 10, .p2_fast = 5 },
146 .find_pll = intel_find_best_PLL, 146 .find_pll = intel_find_best_PLL,
147}; 147};
148 148
149static const intel_limit_t intel_limits_i9xx_lvds = { 149static const intel_limit_t intel_limits_i9xx_lvds = {
150 .dot = { .min = 20000, .max = 400000 }, 150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 }, 151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 }, 152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 }, 153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 }, 154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 }, 155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 }, 156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 }, 157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000, 158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 }, 159 .p2_slow = 14, .p2_fast = 7 },
160 .find_pll = intel_find_best_PLL, 160 .find_pll = intel_find_best_PLL,
@@ -222,44 +222,44 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
222}; 222};
223 223
224static const intel_limit_t intel_limits_g4x_display_port = { 224static const intel_limit_t intel_limits_g4x_display_port = {
225 .dot = { .min = 161670, .max = 227000 }, 225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000}, 226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 }, 227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 }, 228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 }, 229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 }, 230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 }, 231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2}, 232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0, 233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 }, 234 .p2_slow = 10, .p2_fast = 10 },
235 .find_pll = intel_find_pll_g4x_dp, 235 .find_pll = intel_find_pll_g4x_dp,
236}; 236};
237 237
238static const intel_limit_t intel_limits_pineview_sdvo = { 238static const intel_limit_t intel_limits_pineview_sdvo = {
239 .dot = { .min = 20000, .max = 400000}, 239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 }, 240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */ 241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 }, 242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 }, 243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */ 244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 }, 245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 }, 246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 }, 247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 }, 248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000, 249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 }, 250 .p2_slow = 10, .p2_fast = 5 },
251 .find_pll = intel_find_best_PLL, 251 .find_pll = intel_find_best_PLL,
252}; 252};
253 253
254static const intel_limit_t intel_limits_pineview_lvds = { 254static const intel_limit_t intel_limits_pineview_lvds = {
255 .dot = { .min = 20000, .max = 400000 }, 255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 }, 256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 }, 257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 }, 258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 }, 259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 }, 260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 }, 261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 }, 262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000, 263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 }, 264 .p2_slow = 14, .p2_fast = 14 },
265 .find_pll = intel_find_best_PLL, 265 .find_pll = intel_find_best_PLL,
@@ -321,7 +321,7 @@ static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
321 .m1 = { .min = 12, .max = 22 }, 321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 }, 322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 }, 323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 }, 324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000, 325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 }, 326 .p2_slow = 14, .p2_fast = 14 },
327 .find_pll = intel_g4x_find_best_PLL, 327 .find_pll = intel_g4x_find_best_PLL,
@@ -335,24 +335,24 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
335 .m1 = { .min = 12, .max = 22 }, 335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 }, 336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 }, 337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 }, 338 .p1 = { .min = 2, .max = 6 },
339 .p2 = { .dot_limit = 225000, 339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 }, 340 .p2_slow = 7, .p2_fast = 7 },
341 .find_pll = intel_g4x_find_best_PLL, 341 .find_pll = intel_g4x_find_best_PLL,
342}; 342};
343 343
344static const intel_limit_t intel_limits_ironlake_display_port = { 344static const intel_limit_t intel_limits_ironlake_display_port = {
345 .dot = { .min = 25000, .max = 350000 }, 345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000}, 346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 }, 347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 }, 348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 }, 349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 }, 350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 }, 351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2}, 352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0, 353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 }, 354 .p2_slow = 10, .p2_fast = 10 },
355 .find_pll = intel_find_pll_ironlake_dp, 355 .find_pll = intel_find_pll_ironlake_dp,
356}; 356};
357 357
358static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, 358static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
@@ -404,7 +404,7 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
404 limit = &intel_limits_g4x_hdmi; 404 limit = &intel_limits_g4x_hdmi;
405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { 405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
406 limit = &intel_limits_g4x_sdvo; 406 limit = &intel_limits_g4x_sdvo;
407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { 407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
408 limit = &intel_limits_g4x_display_port; 408 limit = &intel_limits_g4x_display_port;
409 } else /* The option is for other outputs */ 409 } else /* The option is for other outputs */
410 limit = &intel_limits_i9xx_sdvo; 410 limit = &intel_limits_i9xx_sdvo;
@@ -488,26 +488,26 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_clock_t *clock) 488 const intel_clock_t *clock)
489{ 489{
490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n"); 491 INTELPllInvalid("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p) 492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n"); 493 INTELPllInvalid("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n"); 495 INTELPllInvalid("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n"); 497 INTELPllInvalid("m1 out of range\n");
498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) 498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
499 INTELPllInvalid ("m1 <= m2\n"); 499 INTELPllInvalid("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m) 500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n"); 501 INTELPllInvalid("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n) 502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n"); 503 INTELPllInvalid("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n"); 505 INTELPllInvalid("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range. 507 * connector, etc., rather than just a single range.
508 */ 508 */
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n"); 510 INTELPllInvalid("dot out of range\n");
511 511
512 return true; 512 return true;
513} 513}
@@ -542,7 +542,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
542 clock.p2 = limit->p2.p2_fast; 542 clock.p2 = limit->p2.p2_fast;
543 } 543 }
544 544
545 memset (best_clock, 0, sizeof (*best_clock)); 545 memset(best_clock, 0, sizeof(*best_clock));
546 546
547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548 clock.m1++) { 548 clock.m1++) {
@@ -2432,7 +2432,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2432 2432
2433} 2433}
2434 2434
2435static const int snb_b_fdi_train_param [] = { 2435static const int snb_b_fdi_train_param[] = {
2436 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 2436 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2437 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 2437 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2438 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 2438 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
@@ -2488,7 +2488,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
2488 if (HAS_PCH_CPT(dev)) 2488 if (HAS_PCH_CPT(dev))
2489 cpt_phase_pointer_enable(dev, pipe); 2489 cpt_phase_pointer_enable(dev, pipe);
2490 2490
2491 for (i = 0; i < 4; i++ ) { 2491 for (i = 0; i < 4; i++) {
2492 reg = FDI_TX_CTL(pipe); 2492 reg = FDI_TX_CTL(pipe);
2493 temp = I915_READ(reg); 2493 temp = I915_READ(reg);
2494 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2494 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2537,7 +2537,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
2537 POSTING_READ(reg); 2537 POSTING_READ(reg);
2538 udelay(150); 2538 udelay(150);
2539 2539
2540 for (i = 0; i < 4; i++ ) { 2540 for (i = 0; i < 4; i++) {
2541 reg = FDI_TX_CTL(pipe); 2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg); 2542 temp = I915_READ(reg);
2543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2607,7 +2607,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2607 if (HAS_PCH_CPT(dev)) 2607 if (HAS_PCH_CPT(dev))
2608 cpt_phase_pointer_enable(dev, pipe); 2608 cpt_phase_pointer_enable(dev, pipe);
2609 2609
2610 for (i = 0; i < 4; i++ ) { 2610 for (i = 0; i < 4; i++) {
2611 reg = FDI_TX_CTL(pipe); 2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg); 2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -2649,7 +2649,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2649 POSTING_READ(reg); 2649 POSTING_READ(reg);
2650 udelay(150); 2650 udelay(150);
2651 2651
2652 for (i = 0; i < 4; i++ ) { 2652 for (i = 0; i < 4; i++) {
2653 reg = FDI_TX_CTL(pipe); 2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg); 2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -3285,14 +3285,14 @@ static void ironlake_crtc_commit(struct drm_crtc *crtc)
3285 ironlake_crtc_enable(crtc); 3285 ironlake_crtc_enable(crtc);
3286} 3286}
3287 3287
3288void intel_encoder_prepare (struct drm_encoder *encoder) 3288void intel_encoder_prepare(struct drm_encoder *encoder)
3289{ 3289{
3290 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3290 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3291 /* lvds has its own version of prepare see intel_lvds_prepare */ 3291 /* lvds has its own version of prepare see intel_lvds_prepare */
3292 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 3292 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3293} 3293}
3294 3294
3295void intel_encoder_commit (struct drm_encoder *encoder) 3295void intel_encoder_commit(struct drm_encoder *encoder)
3296{ 3296{
3297 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3297 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3298 /* lvds has its own version of commit see intel_lvds_commit */ 3298 /* lvds has its own version of commit see intel_lvds_commit */
@@ -8144,7 +8144,7 @@ static void intel_init_display(struct drm_device *dev)
8144 } 8144 }
8145 8145
8146 /* Returns the core display clock speed */ 8146 /* Returns the core display clock speed */
8147 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev))) 8147 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8148 dev_priv->display.get_display_clock_speed = 8148 dev_priv->display.get_display_clock_speed =
8149 i945_get_display_clock_speed; 8149 i945_get_display_clock_speed;
8150 else if (IS_I915G(dev)) 8150 else if (IS_I915G(dev))
@@ -8215,7 +8215,7 @@ static void intel_init_display(struct drm_device *dev)
8215 DRM_INFO("failed to find known CxSR latency " 8215 DRM_INFO("failed to find known CxSR latency "
8216 "(found ddr%s fsb freq %d, mem freq %d), " 8216 "(found ddr%s fsb freq %d, mem freq %d), "
8217 "disabling CxSR\n", 8217 "disabling CxSR\n",
8218 (dev_priv->is_ddr3 == 1) ? "3": "2", 8218 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8219 dev_priv->fsb_freq, dev_priv->mem_freq); 8219 dev_priv->fsb_freq, dev_priv->mem_freq);
8220 /* Disable CxSR and never update its watermark again */ 8220 /* Disable CxSR and never update its watermark again */
8221 pineview_disable_cxsr(dev); 8221 pineview_disable_cxsr(dev);
@@ -8284,7 +8284,7 @@ static void intel_init_display(struct drm_device *dev)
8284 * resume, or other times. This quirk makes sure that's the case for 8284 * resume, or other times. This quirk makes sure that's the case for
8285 * affected systems. 8285 * affected systems.
8286 */ 8286 */
8287static void quirk_pipea_force (struct drm_device *dev) 8287static void quirk_pipea_force(struct drm_device *dev)
8288{ 8288{
8289 struct drm_i915_private *dev_priv = dev->dev_private; 8289 struct drm_i915_private *dev_priv = dev->dev_private;
8290 8290
@@ -8312,7 +8312,7 @@ struct intel_quirk intel_quirks[] = {
8312 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ 8312 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8313 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, 8313 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8314 /* HP Mini needs pipe A force quirk (LP: #322104) */ 8314 /* HP Mini needs pipe A force quirk (LP: #322104) */
8315 { 0x27ae,0x103c, 0x361a, quirk_pipea_force }, 8315 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8316 8316
8317 /* Thinkpad R31 needs pipe A force quirk */ 8317 /* Thinkpad R31 needs pipe A force quirk */
8318 { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, 8318 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
@@ -8563,7 +8563,7 @@ struct intel_display_error_state {
8563struct intel_display_error_state * 8563struct intel_display_error_state *
8564intel_display_capture_error_state(struct drm_device *dev) 8564intel_display_capture_error_state(struct drm_device *dev)
8565{ 8565{
8566 drm_i915_private_t *dev_priv = dev->dev_private; 8566 drm_i915_private_t *dev_priv = dev->dev_private;
8567 struct intel_display_error_state *error; 8567 struct intel_display_error_state *error;
8568 int i; 8568 int i;
8569 8569
@@ -8579,7 +8579,7 @@ intel_display_capture_error_state(struct drm_device *dev)
8579 error->plane[i].control = I915_READ(DSPCNTR(i)); 8579 error->plane[i].control = I915_READ(DSPCNTR(i));
8580 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); 8580 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8581 error->plane[i].size = I915_READ(DSPSIZE(i)); 8581 error->plane[i].size = I915_READ(DSPSIZE(i));
8582 error->plane[i].pos= I915_READ(DSPPOS(i)); 8582 error->plane[i].pos = I915_READ(DSPPOS(i));
8583 error->plane[i].addr = I915_READ(DSPADDR(i)); 8583 error->plane[i].addr = I915_READ(DSPADDR(i));
8584 if (INTEL_INFO(dev)->gen >= 4) { 8584 if (INTEL_INFO(dev)->gen >= 4) {
8585 error->plane[i].surface = I915_READ(DSPSURF(i)); 8585 error->plane[i].surface = I915_READ(DSPSURF(i));
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 44fef5e1c490..4091f2182e6d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -121,7 +121,7 @@ static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
121static void intel_dp_link_down(struct intel_dp *intel_dp); 121static void intel_dp_link_down(struct intel_dp *intel_dp);
122 122
123void 123void
124intel_edp_link_config (struct intel_encoder *intel_encoder, 124intel_edp_link_config(struct intel_encoder *intel_encoder,
125 int *lane_num, int *link_bw) 125 int *lane_num, int *link_bw)
126{ 126{
127 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 127 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
@@ -337,7 +337,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
337 for (i = 0; i < send_bytes; i += 4) 337 for (i = 0; i < send_bytes; i += 4)
338 I915_WRITE(ch_data + i, 338 I915_WRITE(ch_data + i,
339 pack_aux(send + i, send_bytes - i)); 339 pack_aux(send + i, send_bytes - i));
340 340
341 /* Send the command and wait for it to complete */ 341 /* Send the command and wait for it to complete */
342 I915_WRITE(ch_ctl, 342 I915_WRITE(ch_ctl,
343 DP_AUX_CH_CTL_SEND_BUSY | 343 DP_AUX_CH_CTL_SEND_BUSY |
@@ -354,7 +354,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
354 break; 354 break;
355 udelay(100); 355 udelay(100);
356 } 356 }
357 357
358 /* Clear done status and any errors */ 358 /* Clear done status and any errors */
359 I915_WRITE(ch_ctl, 359 I915_WRITE(ch_ctl,
360 status | 360 status |
@@ -390,7 +390,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
390 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 390 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
391 if (recv_bytes > recv_size) 391 if (recv_bytes > recv_size)
392 recv_bytes = recv_size; 392 recv_bytes = recv_size;
393 393
394 for (i = 0; i < recv_bytes; i += 4) 394 for (i = 0; i < recv_bytes; i += 4)
395 unpack_aux(I915_READ(ch_data + i), 395 unpack_aux(I915_READ(ch_data + i),
396 recv + i, recv_bytes - i); 396 recv + i, recv_bytes - i);
@@ -582,10 +582,10 @@ intel_dp_i2c_init(struct intel_dp *intel_dp,
582 intel_dp->algo.address = 0; 582 intel_dp->algo.address = 0;
583 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 583 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
584 584
585 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 585 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
586 intel_dp->adapter.owner = THIS_MODULE; 586 intel_dp->adapter.owner = THIS_MODULE;
587 intel_dp->adapter.class = I2C_CLASS_DDC; 587 intel_dp->adapter.class = I2C_CLASS_DDC;
588 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 588 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
589 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 589 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
590 intel_dp->adapter.algo_data = &intel_dp->algo; 590 intel_dp->adapter.algo_data = &intel_dp->algo;
591 intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 591 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
@@ -839,7 +839,7 @@ static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
839} 839}
840 840
841/* Returns true if the panel was already on when called */ 841/* Returns true if the panel was already on when called */
842static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) 842static bool ironlake_edp_panel_on(struct intel_dp *intel_dp)
843{ 843{
844 struct drm_device *dev = intel_dp->base.base.dev; 844 struct drm_device *dev = intel_dp->base.base.dev;
845 struct drm_i915_private *dev_priv = dev->dev_private; 845 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -871,7 +871,7 @@ static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
871 return false; 871 return false;
872} 872}
873 873
874static void ironlake_edp_panel_off (struct drm_device *dev) 874static void ironlake_edp_panel_off(struct drm_device *dev)
875{ 875{
876 struct drm_i915_private *dev_priv = dev->dev_private; 876 struct drm_i915_private *dev_priv = dev->dev_private;
877 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | 877 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
@@ -897,7 +897,7 @@ static void ironlake_edp_panel_off (struct drm_device *dev)
897 POSTING_READ(PCH_PP_CONTROL); 897 POSTING_READ(PCH_PP_CONTROL);
898} 898}
899 899
900static void ironlake_edp_backlight_on (struct drm_device *dev) 900static void ironlake_edp_backlight_on(struct drm_device *dev)
901{ 901{
902 struct drm_i915_private *dev_priv = dev->dev_private; 902 struct drm_i915_private *dev_priv = dev->dev_private;
903 u32 pp; 903 u32 pp;
@@ -915,7 +915,7 @@ static void ironlake_edp_backlight_on (struct drm_device *dev)
915 I915_WRITE(PCH_PP_CONTROL, pp); 915 I915_WRITE(PCH_PP_CONTROL, pp);
916} 916}
917 917
918static void ironlake_edp_backlight_off (struct drm_device *dev) 918static void ironlake_edp_backlight_off(struct drm_device *dev)
919{ 919{
920 struct drm_i915_private *dev_priv = dev->dev_private; 920 struct drm_i915_private *dev_priv = dev->dev_private;
921 u32 pp; 921 u32 pp;
@@ -1584,7 +1584,7 @@ static bool
1584intel_dp_get_dpcd(struct intel_dp *intel_dp) 1584intel_dp_get_dpcd(struct intel_dp *intel_dp)
1585{ 1585{
1586 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 1586 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1587 sizeof (intel_dp->dpcd)) && 1587 sizeof(intel_dp->dpcd)) &&
1588 (intel_dp->dpcd[DP_DPCD_REV] != 0)) { 1588 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1589 return true; 1589 return true;
1590 } 1590 }
@@ -1839,7 +1839,7 @@ done:
1839} 1839}
1840 1840
1841static void 1841static void
1842intel_dp_destroy (struct drm_connector *connector) 1842intel_dp_destroy(struct drm_connector *connector)
1843{ 1843{
1844 struct drm_device *dev = connector->dev; 1844 struct drm_device *dev = connector->dev;
1845 1845
@@ -1896,7 +1896,7 @@ intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1896 1896
1897/* Return which DP Port should be selected for Transcoder DP control */ 1897/* Return which DP Port should be selected for Transcoder DP control */
1898int 1898int
1899intel_trans_dp_port_sel (struct drm_crtc *crtc) 1899intel_trans_dp_port_sel(struct drm_crtc *crtc)
1900{ 1900{
1901 struct drm_device *dev = crtc->dev; 1901 struct drm_device *dev = crtc->dev;
1902 struct drm_mode_config *mode_config = &dev->mode_config; 1902 struct drm_mode_config *mode_config = &dev->mode_config;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0b2ee9d39980..375690b21624 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -34,7 +34,7 @@
34#define _wait_for(COND, MS, W) ({ \ 34#define _wait_for(COND, MS, W) ({ \
35 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 35 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
36 int ret__ = 0; \ 36 int ret__ = 0; \
37 while (! (COND)) { \ 37 while (!(COND)) { \
38 if (time_after(jiffies, timeout__)) { \ 38 if (time_after(jiffies, timeout__)) { \
39 ret__ = -ETIMEDOUT; \ 39 ret__ = -ETIMEDOUT; \
40 break; \ 40 break; \
@@ -49,10 +49,10 @@
49 49
50#define MSLEEP(x) do { \ 50#define MSLEEP(x) do { \
51 if (in_dbg_master()) \ 51 if (in_dbg_master()) \
52 mdelay(x); \ 52 mdelay(x); \
53 else \ 53 else \
54 msleep(x); \ 54 msleep(x); \
55} while(0) 55} while (0)
56 56
57#define KHz(x) (1000*x) 57#define KHz(x) (1000*x)
58#define MHz(x) KHz(1000*x) 58#define MHz(x) KHz(1000*x)
@@ -284,7 +284,7 @@ void
284intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 284intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
285 struct drm_display_mode *adjusted_mode); 285 struct drm_display_mode *adjusted_mode);
286extern bool intel_dpd_is_edp(struct drm_device *dev); 286extern bool intel_dpd_is_edp(struct drm_device *dev);
287extern void intel_edp_link_config (struct intel_encoder *, int *, int *); 287extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
288extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); 288extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
289 289
290/* intel_panel.c */ 290/* intel_panel.c */
@@ -304,8 +304,8 @@ extern void intel_panel_destroy_backlight(struct drm_device *dev);
304extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); 304extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
305 305
306extern void intel_crtc_load_lut(struct drm_crtc *crtc); 306extern void intel_crtc_load_lut(struct drm_crtc *crtc);
307extern void intel_encoder_prepare (struct drm_encoder *encoder); 307extern void intel_encoder_prepare(struct drm_encoder *encoder);
308extern void intel_encoder_commit (struct drm_encoder *encoder); 308extern void intel_encoder_commit(struct drm_encoder *encoder);
309extern void intel_encoder_destroy(struct drm_encoder *encoder); 309extern void intel_encoder_destroy(struct drm_encoder *encoder);
310 310
311static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) 311static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index b8e8158bb16e..289140bc83cb 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -51,61 +51,61 @@
51#define MBOX_ASLE (1<<2) 51#define MBOX_ASLE (1<<2)
52 52
53struct opregion_header { 53struct opregion_header {
54 u8 signature[16]; 54 u8 signature[16];
55 u32 size; 55 u32 size;
56 u32 opregion_ver; 56 u32 opregion_ver;
57 u8 bios_ver[32]; 57 u8 bios_ver[32];
58 u8 vbios_ver[16]; 58 u8 vbios_ver[16];
59 u8 driver_ver[16]; 59 u8 driver_ver[16];
60 u32 mboxes; 60 u32 mboxes;
61 u8 reserved[164]; 61 u8 reserved[164];
62} __attribute__((packed)); 62} __attribute__((packed));
63 63
64/* OpRegion mailbox #1: public ACPI methods */ 64/* OpRegion mailbox #1: public ACPI methods */
65struct opregion_acpi { 65struct opregion_acpi {
66 u32 drdy; /* driver readiness */ 66 u32 drdy; /* driver readiness */
67 u32 csts; /* notification status */ 67 u32 csts; /* notification status */
68 u32 cevt; /* current event */ 68 u32 cevt; /* current event */
69 u8 rsvd1[20]; 69 u8 rsvd1[20];
70 u32 didl[8]; /* supported display devices ID list */ 70 u32 didl[8]; /* supported display devices ID list */
71 u32 cpdl[8]; /* currently presented display list */ 71 u32 cpdl[8]; /* currently presented display list */
72 u32 cadl[8]; /* currently active display list */ 72 u32 cadl[8]; /* currently active display list */
73 u32 nadl[8]; /* next active devices list */ 73 u32 nadl[8]; /* next active devices list */
74 u32 aslp; /* ASL sleep time-out */ 74 u32 aslp; /* ASL sleep time-out */
75 u32 tidx; /* toggle table index */ 75 u32 tidx; /* toggle table index */
76 u32 chpd; /* current hotplug enable indicator */ 76 u32 chpd; /* current hotplug enable indicator */
77 u32 clid; /* current lid state*/ 77 u32 clid; /* current lid state*/
78 u32 cdck; /* current docking state */ 78 u32 cdck; /* current docking state */
79 u32 sxsw; /* Sx state resume */ 79 u32 sxsw; /* Sx state resume */
80 u32 evts; /* ASL supported events */ 80 u32 evts; /* ASL supported events */
81 u32 cnot; /* current OS notification */ 81 u32 cnot; /* current OS notification */
82 u32 nrdy; /* driver status */ 82 u32 nrdy; /* driver status */
83 u8 rsvd2[60]; 83 u8 rsvd2[60];
84} __attribute__((packed)); 84} __attribute__((packed));
85 85
86/* OpRegion mailbox #2: SWSCI */ 86/* OpRegion mailbox #2: SWSCI */
87struct opregion_swsci { 87struct opregion_swsci {
88 u32 scic; /* SWSCI command|status|data */ 88 u32 scic; /* SWSCI command|status|data */
89 u32 parm; /* command parameters */ 89 u32 parm; /* command parameters */
90 u32 dslp; /* driver sleep time-out */ 90 u32 dslp; /* driver sleep time-out */
91 u8 rsvd[244]; 91 u8 rsvd[244];
92} __attribute__((packed)); 92} __attribute__((packed));
93 93
94/* OpRegion mailbox #3: ASLE */ 94/* OpRegion mailbox #3: ASLE */
95struct opregion_asle { 95struct opregion_asle {
96 u32 ardy; /* driver readiness */ 96 u32 ardy; /* driver readiness */
97 u32 aslc; /* ASLE interrupt command */ 97 u32 aslc; /* ASLE interrupt command */
98 u32 tche; /* technology enabled indicator */ 98 u32 tche; /* technology enabled indicator */
99 u32 alsi; /* current ALS illuminance reading */ 99 u32 alsi; /* current ALS illuminance reading */
100 u32 bclp; /* backlight brightness to set */ 100 u32 bclp; /* backlight brightness to set */
101 u32 pfit; /* panel fitting state */ 101 u32 pfit; /* panel fitting state */
102 u32 cblv; /* current brightness level */ 102 u32 cblv; /* current brightness level */
103 u16 bclm[20]; /* backlight level duty cycle mapping table */ 103 u16 bclm[20]; /* backlight level duty cycle mapping table */
104 u32 cpfm; /* current panel fitting mode */ 104 u32 cpfm; /* current panel fitting mode */
105 u32 epfm; /* enabled panel fitting modes */ 105 u32 epfm; /* enabled panel fitting modes */
106 u8 plut[74]; /* panel LUT and identifier */ 106 u8 plut[74]; /* panel LUT and identifier */
107 u32 pfmb; /* PWM freq and min brightness */ 107 u32 pfmb; /* PWM freq and min brightness */
108 u8 rsvd[102]; 108 u8 rsvd[102];
109} __attribute__((packed)); 109} __attribute__((packed));
110 110
111/* ASLE irq request bits */ 111/* ASLE irq request bits */
@@ -361,7 +361,7 @@ static void intel_didl_outputs(struct drm_device *dev)
361 361
362 list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) { 362 list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) {
363 if (i >= 8) { 363 if (i >= 8) {
364 dev_printk (KERN_ERR, &dev->pdev->dev, 364 dev_printk(KERN_ERR, &dev->pdev->dev,
365 "More than 8 outputs detected\n"); 365 "More than 8 outputs detected\n");
366 return; 366 return;
367 } 367 }
@@ -387,7 +387,7 @@ blind_set:
387 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 387 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
388 int output_type = ACPI_OTHER_OUTPUT; 388 int output_type = ACPI_OTHER_OUTPUT;
389 if (i >= 8) { 389 if (i >= 8) {
390 dev_printk (KERN_ERR, &dev->pdev->dev, 390 dev_printk(KERN_ERR, &dev->pdev->dev,
391 "More than 8 outputs detected\n"); 391 "More than 8 outputs detected\n");
392 return; 392 return;
393 } 393 }
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index d36038086826..cdf17d4cc1f7 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -117,57 +117,57 @@
117 117
118/* memory bufferd overlay registers */ 118/* memory bufferd overlay registers */
119struct overlay_registers { 119struct overlay_registers {
120 u32 OBUF_0Y; 120 u32 OBUF_0Y;
121 u32 OBUF_1Y; 121 u32 OBUF_1Y;
122 u32 OBUF_0U; 122 u32 OBUF_0U;
123 u32 OBUF_0V; 123 u32 OBUF_0V;
124 u32 OBUF_1U; 124 u32 OBUF_1U;
125 u32 OBUF_1V; 125 u32 OBUF_1V;
126 u32 OSTRIDE; 126 u32 OSTRIDE;
127 u32 YRGB_VPH; 127 u32 YRGB_VPH;
128 u32 UV_VPH; 128 u32 UV_VPH;
129 u32 HORZ_PH; 129 u32 HORZ_PH;
130 u32 INIT_PHS; 130 u32 INIT_PHS;
131 u32 DWINPOS; 131 u32 DWINPOS;
132 u32 DWINSZ; 132 u32 DWINSZ;
133 u32 SWIDTH; 133 u32 SWIDTH;
134 u32 SWIDTHSW; 134 u32 SWIDTHSW;
135 u32 SHEIGHT; 135 u32 SHEIGHT;
136 u32 YRGBSCALE; 136 u32 YRGBSCALE;
137 u32 UVSCALE; 137 u32 UVSCALE;
138 u32 OCLRC0; 138 u32 OCLRC0;
139 u32 OCLRC1; 139 u32 OCLRC1;
140 u32 DCLRKV; 140 u32 DCLRKV;
141 u32 DCLRKM; 141 u32 DCLRKM;
142 u32 SCLRKVH; 142 u32 SCLRKVH;
143 u32 SCLRKVL; 143 u32 SCLRKVL;
144 u32 SCLRKEN; 144 u32 SCLRKEN;
145 u32 OCONFIG; 145 u32 OCONFIG;
146 u32 OCMD; 146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */ 147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y; 148 u32 OSTART_0Y;
149 u32 OSTART_1Y; 149 u32 OSTART_1Y;
150 u32 OSTART_0U; 150 u32 OSTART_0U;
151 u32 OSTART_0V; 151 u32 OSTART_0V;
152 u32 OSTART_1U; 152 u32 OSTART_1U;
153 u32 OSTART_1V; 153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y; 154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y; 155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U; 156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V; 157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U; 158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V; 159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */ 160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */ 161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171}; 171};
172 172
173struct intel_overlay { 173struct intel_overlay {
@@ -192,7 +192,7 @@ struct intel_overlay {
192static struct overlay_registers * 192static struct overlay_registers *
193intel_overlay_map_regs(struct intel_overlay *overlay) 193intel_overlay_map_regs(struct intel_overlay *overlay)
194{ 194{
195 drm_i915_private_t *dev_priv = overlay->dev->dev_private; 195 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
196 struct overlay_registers *regs; 196 struct overlay_registers *regs;
197 197
198 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev)) 198 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
@@ -264,7 +264,7 @@ i830_activate_pipe_a(struct drm_device *dev)
264 264
265 mode = drm_mode_duplicate(dev, &vesa_640x480); 265 mode = drm_mode_duplicate(dev, &vesa_640x480);
266 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); 266 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
267 if(!drm_crtc_helper_set_mode(&crtc->base, mode, 267 if (!drm_crtc_helper_set_mode(&crtc->base, mode,
268 crtc->base.x, crtc->base.y, 268 crtc->base.x, crtc->base.y,
269 crtc->base.fb)) 269 crtc->base.fb))
270 return 0; 270 return 0;
@@ -332,7 +332,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
332 bool load_polyphase_filter) 332 bool load_polyphase_filter)
333{ 333{
334 struct drm_device *dev = overlay->dev; 334 struct drm_device *dev = overlay->dev;
335 drm_i915_private_t *dev_priv = dev->dev_private; 335 drm_i915_private_t *dev_priv = dev->dev_private;
336 struct drm_i915_gem_request *request; 336 struct drm_i915_gem_request *request;
337 u32 flip_addr = overlay->flip_addr; 337 u32 flip_addr = overlay->flip_addr;
338 u32 tmp; 338 u32 tmp;
@@ -359,7 +359,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
359 } 359 }
360 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); 360 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
361 OUT_RING(flip_addr); 361 OUT_RING(flip_addr);
362 ADVANCE_LP_RING(); 362 ADVANCE_LP_RING();
363 363
364 ret = i915_add_request(LP_RING(dev_priv), NULL, request); 364 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
365 if (ret) { 365 if (ret) {
@@ -583,7 +583,7 @@ static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
583 ret = ((offset + width + mask) >> shift) - (offset >> shift); 583 ret = ((offset + width + mask) >> shift) - (offset >> shift);
584 if (!IS_GEN2(dev)) 584 if (!IS_GEN2(dev))
585 ret <<= 1; 585 ret <<= 1;
586 ret -=1; 586 ret -= 1;
587 return ret << 2; 587 return ret << 2;
588} 588}
589 589
@@ -817,7 +817,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
817 regs->SWIDTHSW = calc_swidthsw(overlay->dev, 817 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
818 params->offset_Y, tmp_width); 818 params->offset_Y, tmp_width);
819 regs->SHEIGHT = params->src_h; 819 regs->SHEIGHT = params->src_h;
820 regs->OBUF_0Y = new_bo->gtt_offset + params-> offset_Y; 820 regs->OBUF_0Y = new_bo->gtt_offset + params->offset_Y;
821 regs->OSTRIDE = params->stride_Y; 821 regs->OSTRIDE = params->stride_Y;
822 822
823 if (params->format & I915_OVERLAY_YUV_PLANAR) { 823 if (params->format & I915_OVERLAY_YUV_PLANAR) {
@@ -917,7 +917,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
917 * line with the intel documentation for the i965 917 * line with the intel documentation for the i965
918 */ 918 */
919 if (INTEL_INFO(dev)->gen >= 4) { 919 if (INTEL_INFO(dev)->gen >= 4) {
920 /* on i965 use the PGM reg to read out the autoscaler values */ 920 /* on i965 use the PGM reg to read out the autoscaler values */
921 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 921 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
922 } else { 922 } else {
923 if (pfit_control & VERT_AUTO_SCALE) 923 if (pfit_control & VERT_AUTO_SCALE)
@@ -1098,7 +1098,7 @@ static int intel_panel_fitter_pipe(struct drm_device *dev)
1098} 1098}
1099 1099
1100int intel_overlay_put_image(struct drm_device *dev, void *data, 1100int intel_overlay_put_image(struct drm_device *dev, void *data,
1101 struct drm_file *file_priv) 1101 struct drm_file *file_priv)
1102{ 1102{
1103 struct drm_intel_overlay_put_image *put_image_rec = data; 1103 struct drm_intel_overlay_put_image *put_image_rec = data;
1104 drm_i915_private_t *dev_priv = dev->dev_private; 1104 drm_i915_private_t *dev_priv = dev->dev_private;
@@ -1301,10 +1301,10 @@ static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1301} 1301}
1302 1302
1303int intel_overlay_attrs(struct drm_device *dev, void *data, 1303int intel_overlay_attrs(struct drm_device *dev, void *data,
1304 struct drm_file *file_priv) 1304 struct drm_file *file_priv)
1305{ 1305{
1306 struct drm_intel_overlay_attrs *attrs = data; 1306 struct drm_intel_overlay_attrs *attrs = data;
1307 drm_i915_private_t *dev_priv = dev->dev_private; 1307 drm_i915_private_t *dev_priv = dev->dev_private;
1308 struct intel_overlay *overlay; 1308 struct intel_overlay *overlay;
1309 struct overlay_registers *regs; 1309 struct overlay_registers *regs;
1310 int ret; 1310 int ret;
@@ -1393,7 +1393,7 @@ out_unlock:
1393 1393
1394void intel_setup_overlay(struct drm_device *dev) 1394void intel_setup_overlay(struct drm_device *dev)
1395{ 1395{
1396 drm_i915_private_t *dev_priv = dev->dev_private; 1396 drm_i915_private_t *dev_priv = dev->dev_private;
1397 struct intel_overlay *overlay; 1397 struct intel_overlay *overlay;
1398 struct drm_i915_gem_object *reg_bo; 1398 struct drm_i915_gem_object *reg_bo;
1399 struct overlay_registers *regs; 1399 struct overlay_registers *regs;
@@ -1421,24 +1421,24 @@ void intel_setup_overlay(struct drm_device *dev)
1421 ret = i915_gem_attach_phys_object(dev, reg_bo, 1421 ret = i915_gem_attach_phys_object(dev, reg_bo,
1422 I915_GEM_PHYS_OVERLAY_REGS, 1422 I915_GEM_PHYS_OVERLAY_REGS,
1423 PAGE_SIZE); 1423 PAGE_SIZE);
1424 if (ret) { 1424 if (ret) {
1425 DRM_ERROR("failed to attach phys overlay regs\n"); 1425 DRM_ERROR("failed to attach phys overlay regs\n");
1426 goto out_free_bo; 1426 goto out_free_bo;
1427 } 1427 }
1428 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr; 1428 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
1429 } else { 1429 } else {
1430 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true); 1430 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true);
1431 if (ret) { 1431 if (ret) {
1432 DRM_ERROR("failed to pin overlay register bo\n"); 1432 DRM_ERROR("failed to pin overlay register bo\n");
1433 goto out_free_bo; 1433 goto out_free_bo;
1434 } 1434 }
1435 overlay->flip_addr = reg_bo->gtt_offset; 1435 overlay->flip_addr = reg_bo->gtt_offset;
1436 1436
1437 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true); 1437 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1438 if (ret) { 1438 if (ret) {
1439 DRM_ERROR("failed to move overlay register bo into the GTT\n"); 1439 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1440 goto out_unpin_bo; 1440 goto out_unpin_bo;
1441 } 1441 }
1442 } 1442 }
1443 1443
1444 /* init all values */ 1444 /* init all values */
@@ -1525,7 +1525,7 @@ static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1525struct intel_overlay_error_state * 1525struct intel_overlay_error_state *
1526intel_overlay_capture_error_state(struct drm_device *dev) 1526intel_overlay_capture_error_state(struct drm_device *dev)
1527{ 1527{
1528 drm_i915_private_t *dev_priv = dev->dev_private; 1528 drm_i915_private_t *dev_priv = dev->dev_private;
1529 struct intel_overlay *overlay = dev_priv->overlay; 1529 struct intel_overlay *overlay = dev_priv->overlay;
1530 struct intel_overlay_error_state *error; 1530 struct intel_overlay_error_state *error;
1531 struct overlay_registers __iomem *regs; 1531 struct overlay_registers __iomem *regs;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index a9e0c7bcd317..03500e94a73f 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -84,7 +84,7 @@ intel_pch_panel_fitting(struct drm_device *dev,
84 if (scaled_width > scaled_height) { /* pillar */ 84 if (scaled_width > scaled_height) { /* pillar */
85 width = scaled_height / mode->vdisplay; 85 width = scaled_height / mode->vdisplay;
86 if (width & 1) 86 if (width & 1)
87 width++; 87 width++;
88 x = (adjusted_mode->hdisplay - width + 1) / 2; 88 x = (adjusted_mode->hdisplay - width + 1) / 2;
89 y = 0; 89 y = 0;
90 height = adjusted_mode->vdisplay; 90 height = adjusted_mode->vdisplay;
@@ -206,7 +206,7 @@ u32 intel_panel_get_backlight(struct drm_device *dev)
206 if (IS_PINEVIEW(dev)) 206 if (IS_PINEVIEW(dev))
207 val >>= 1; 207 val >>= 1;
208 208
209 if (is_backlight_combination_mode(dev)){ 209 if (is_backlight_combination_mode(dev)) {
210 u8 lbpc; 210 u8 lbpc;
211 211
212 val &= ~1; 212 val &= ~1;
@@ -236,7 +236,7 @@ void intel_panel_set_backlight(struct drm_device *dev, u32 level)
236 if (HAS_PCH_SPLIT(dev)) 236 if (HAS_PCH_SPLIT(dev))
237 return intel_pch_panel_set_backlight(dev, level); 237 return intel_pch_panel_set_backlight(dev, level);
238 238
239 if (is_backlight_combination_mode(dev)){ 239 if (is_backlight_combination_mode(dev)) {
240 u32 max = intel_panel_get_max_backlight(dev); 240 u32 max = intel_panel_get_max_backlight(dev);
241 u8 lbpc; 241 u8 lbpc;
242 242
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c30626ea9f93..a40f3456448d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1026,7 +1026,7 @@ static const struct intel_ring_buffer render_ring = {
1026 .irq_get = render_ring_get_irq, 1026 .irq_get = render_ring_get_irq,
1027 .irq_put = render_ring_put_irq, 1027 .irq_put = render_ring_put_irq,
1028 .dispatch_execbuffer = render_ring_dispatch_execbuffer, 1028 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
1029 .cleanup = render_ring_cleanup, 1029 .cleanup = render_ring_cleanup,
1030}; 1030};
1031 1031
1032/* ring buffer for bit-stream decoder */ 1032/* ring buffer for bit-stream decoder */
@@ -1050,23 +1050,23 @@ static const struct intel_ring_buffer bsd_ring = {
1050static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, 1050static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1051 u32 value) 1051 u32 value)
1052{ 1052{
1053 drm_i915_private_t *dev_priv = ring->dev->dev_private; 1053 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1054 1054
1055 /* Every tail move must follow the sequence below */ 1055 /* Every tail move must follow the sequence below */
1056 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, 1056 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1057 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | 1057 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1058 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); 1058 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1059 I915_WRITE(GEN6_BSD_RNCID, 0x0); 1059 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1060 1060
1061 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & 1061 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1062 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, 1062 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1063 50)) 1063 50))
1064 DRM_ERROR("timed out waiting for IDLE Indicator\n"); 1064 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1065 1065
1066 I915_WRITE_TAIL(ring, value); 1066 I915_WRITE_TAIL(ring, value);
1067 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, 1067 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1068 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | 1068 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1069 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); 1069 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1070} 1070}
1071 1071
1072static int gen6_ring_flush(struct intel_ring_buffer *ring, 1072static int gen6_ring_flush(struct intel_ring_buffer *ring,
@@ -1094,18 +1094,18 @@ static int
1094gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, 1094gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1095 u32 offset, u32 len) 1095 u32 offset, u32 len)
1096{ 1096{
1097 int ret; 1097 int ret;
1098 1098
1099 ret = intel_ring_begin(ring, 2); 1099 ret = intel_ring_begin(ring, 2);
1100 if (ret) 1100 if (ret)
1101 return ret; 1101 return ret;
1102 1102
1103 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); 1103 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1104 /* bit0-7 is the length on GEN6+ */ 1104 /* bit0-7 is the length on GEN6+ */
1105 intel_ring_emit(ring, offset); 1105 intel_ring_emit(ring, offset);
1106 intel_ring_advance(ring); 1106 intel_ring_advance(ring);
1107 1107
1108 return 0; 1108 return 0;
1109} 1109}
1110 1110
1111static bool 1111static bool
@@ -1272,19 +1272,19 @@ static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1272} 1272}
1273 1273
1274static const struct intel_ring_buffer gen6_blt_ring = { 1274static const struct intel_ring_buffer gen6_blt_ring = {
1275 .name = "blt ring", 1275 .name = "blt ring",
1276 .id = RING_BLT, 1276 .id = RING_BLT,
1277 .mmio_base = BLT_RING_BASE, 1277 .mmio_base = BLT_RING_BASE,
1278 .size = 32 * PAGE_SIZE, 1278 .size = 32 * PAGE_SIZE,
1279 .init = blt_ring_init, 1279 .init = blt_ring_init,
1280 .write_tail = ring_write_tail, 1280 .write_tail = ring_write_tail,
1281 .flush = blt_ring_flush, 1281 .flush = blt_ring_flush,
1282 .add_request = gen6_add_request, 1282 .add_request = gen6_add_request,
1283 .get_seqno = ring_get_seqno, 1283 .get_seqno = ring_get_seqno,
1284 .irq_get = blt_ring_get_irq, 1284 .irq_get = blt_ring_get_irq,
1285 .irq_put = blt_ring_put_irq, 1285 .irq_put = blt_ring_put_irq,
1286 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, 1286 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1287 .cleanup = blt_ring_cleanup, 1287 .cleanup = blt_ring_cleanup,
1288}; 1288};
1289 1289
1290int intel_init_render_ring_buffer(struct drm_device *dev) 1290int intel_init_render_ring_buffer(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 39ac2b634ae5..600e67abd8d0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -2,10 +2,10 @@
2#define _INTEL_RINGBUFFER_H_ 2#define _INTEL_RINGBUFFER_H_
3 3
4enum { 4enum {
5 RCS = 0x0, 5 RCS = 0x0,
6 VCS, 6 VCS,
7 BCS, 7 BCS,
8 I915_NUM_RINGS, 8 I915_NUM_RINGS,
9}; 9};
10 10
11struct intel_hw_status_page { 11struct intel_hw_status_page {
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 30fe554d8936..aa94110f0be4 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -43,7 +43,7 @@
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK) 46 SDVO_TV_MASK)
47 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
@@ -283,117 +283,117 @@ static const struct _sdvo_cmd_name {
283 u8 cmd; 283 u8 cmd;
284 const char *name; 284 const char *name;
285} sdvo_cmd_names[] = { 285} sdvo_cmd_names[] = {
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
329 329
330 /* Add the op code for SDVO enhancements */ 330 /* Add the op code for SDVO enhancements */
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
375 375
376 /* HDMI op code */ 376 /* HDMI op code */
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
397}; 397};
398 398
399#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) 399#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
@@ -2313,7 +2313,7 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2313 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2313 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2314 data_value[0], data_value[1], response); \ 2314 data_value[0], data_value[1], response); \
2315 } \ 2315 } \
2316} while(0) 2316} while (0)
2317 2317
2318static bool 2318static bool
2319intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2319intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
@@ -2480,7 +2480,7 @@ static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2480 2480
2481 if (IS_TV(intel_sdvo_connector)) 2481 if (IS_TV(intel_sdvo_connector))
2482 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2482 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2483 else if(IS_LVDS(intel_sdvo_connector)) 2483 else if (IS_LVDS(intel_sdvo_connector))
2484 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2484 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2485 else 2485 else
2486 return true; 2486 return true;
diff --git a/drivers/gpu/drm/i915/intel_sdvo_regs.h b/drivers/gpu/drm/i915/intel_sdvo_regs.h
index 4f4e23bc2d16..4aa6f343e49a 100644
--- a/drivers/gpu/drm/i915/intel_sdvo_regs.h
+++ b/drivers/gpu/drm/i915/intel_sdvo_regs.h
@@ -46,63 +46,63 @@
46#define SDVO_OUTPUT_LAST (14) 46#define SDVO_OUTPUT_LAST (14)
47 47
48struct intel_sdvo_caps { 48struct intel_sdvo_caps {
49 u8 vendor_id; 49 u8 vendor_id;
50 u8 device_id; 50 u8 device_id;
51 u8 device_rev_id; 51 u8 device_rev_id;
52 u8 sdvo_version_major; 52 u8 sdvo_version_major;
53 u8 sdvo_version_minor; 53 u8 sdvo_version_minor;
54 unsigned int sdvo_inputs_mask:2; 54 unsigned int sdvo_inputs_mask:2;
55 unsigned int smooth_scaling:1; 55 unsigned int smooth_scaling:1;
56 unsigned int sharp_scaling:1; 56 unsigned int sharp_scaling:1;
57 unsigned int up_scaling:1; 57 unsigned int up_scaling:1;
58 unsigned int down_scaling:1; 58 unsigned int down_scaling:1;
59 unsigned int stall_support:1; 59 unsigned int stall_support:1;
60 unsigned int pad:1; 60 unsigned int pad:1;
61 u16 output_flags; 61 u16 output_flags;
62} __attribute__((packed)); 62} __attribute__((packed));
63 63
64/** This matches the EDID DTD structure, more or less */ 64/** This matches the EDID DTD structure, more or less */
65struct intel_sdvo_dtd { 65struct intel_sdvo_dtd {
66 struct { 66 struct {
67 u16 clock; /**< pixel clock, in 10kHz units */ 67 u16 clock; /**< pixel clock, in 10kHz units */
68 u8 h_active; /**< lower 8 bits (pixels) */ 68 u8 h_active; /**< lower 8 bits (pixels) */
69 u8 h_blank; /**< lower 8 bits (pixels) */ 69 u8 h_blank; /**< lower 8 bits (pixels) */
70 u8 h_high; /**< upper 4 bits each h_active, h_blank */ 70 u8 h_high; /**< upper 4 bits each h_active, h_blank */
71 u8 v_active; /**< lower 8 bits (lines) */ 71 u8 v_active; /**< lower 8 bits (lines) */
72 u8 v_blank; /**< lower 8 bits (lines) */ 72 u8 v_blank; /**< lower 8 bits (lines) */
73 u8 v_high; /**< upper 4 bits each v_active, v_blank */ 73 u8 v_high; /**< upper 4 bits each v_active, v_blank */
74 } part1; 74 } part1;
75 75
76 struct { 76 struct {
77 u8 h_sync_off; /**< lower 8 bits, from hblank start */ 77 u8 h_sync_off; /**< lower 8 bits, from hblank start */
78 u8 h_sync_width; /**< lower 8 bits (pixels) */ 78 u8 h_sync_width; /**< lower 8 bits (pixels) */
79 /** lower 4 bits each vsync offset, vsync width */ 79 /** lower 4 bits each vsync offset, vsync width */
80 u8 v_sync_off_width; 80 u8 v_sync_off_width;
81 /** 81 /**
82 * 2 high bits of hsync offset, 2 high bits of hsync width, 82 * 2 high bits of hsync offset, 2 high bits of hsync width,
83 * bits 4-5 of vsync offset, and 2 high bits of vsync width. 83 * bits 4-5 of vsync offset, and 2 high bits of vsync width.
84 */ 84 */
85 u8 sync_off_width_high; 85 u8 sync_off_width_high;
86 u8 dtd_flags; 86 u8 dtd_flags;
87 u8 sdvo_flags; 87 u8 sdvo_flags;
88 /** bits 6-7 of vsync offset at bits 6-7 */ 88 /** bits 6-7 of vsync offset at bits 6-7 */
89 u8 v_sync_off_high; 89 u8 v_sync_off_high;
90 u8 reserved; 90 u8 reserved;
91 } part2; 91 } part2;
92} __attribute__((packed)); 92} __attribute__((packed));
93 93
94struct intel_sdvo_pixel_clock_range { 94struct intel_sdvo_pixel_clock_range {
95 u16 min; /**< pixel clock, in 10kHz units */ 95 u16 min; /**< pixel clock, in 10kHz units */
96 u16 max; /**< pixel clock, in 10kHz units */ 96 u16 max; /**< pixel clock, in 10kHz units */
97} __attribute__((packed)); 97} __attribute__((packed));
98 98
99struct intel_sdvo_preferred_input_timing_args { 99struct intel_sdvo_preferred_input_timing_args {
100 u16 clock; 100 u16 clock;
101 u16 width; 101 u16 width;
102 u16 height; 102 u16 height;
103 u8 interlace:1; 103 u8 interlace:1;
104 u8 scaled:1; 104 u8 scaled:1;
105 u8 pad:6; 105 u8 pad:6;
106} __attribute__((packed)); 106} __attribute__((packed));
107 107
108/* I2C registers for SDVO */ 108/* I2C registers for SDVO */
@@ -154,9 +154,9 @@ struct intel_sdvo_preferred_input_timing_args {
154 */ 154 */
155#define SDVO_CMD_GET_TRAINED_INPUTS 0x03 155#define SDVO_CMD_GET_TRAINED_INPUTS 0x03
156struct intel_sdvo_get_trained_inputs_response { 156struct intel_sdvo_get_trained_inputs_response {
157 unsigned int input0_trained:1; 157 unsigned int input0_trained:1;
158 unsigned int input1_trained:1; 158 unsigned int input1_trained:1;
159 unsigned int pad:6; 159 unsigned int pad:6;
160} __attribute__((packed)); 160} __attribute__((packed));
161 161
162/** Returns a struct intel_sdvo_output_flags of active outputs. */ 162/** Returns a struct intel_sdvo_output_flags of active outputs. */
@@ -177,7 +177,7 @@ struct intel_sdvo_get_trained_inputs_response {
177 */ 177 */
178#define SDVO_CMD_GET_IN_OUT_MAP 0x06 178#define SDVO_CMD_GET_IN_OUT_MAP 0x06
179struct intel_sdvo_in_out_map { 179struct intel_sdvo_in_out_map {
180 u16 in0, in1; 180 u16 in0, in1;
181}; 181};
182 182
183/** 183/**
@@ -210,10 +210,10 @@ struct intel_sdvo_in_out_map {
210 210
211#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f 211#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f
212struct intel_sdvo_get_interrupt_event_source_response { 212struct intel_sdvo_get_interrupt_event_source_response {
213 u16 interrupt_status; 213 u16 interrupt_status;
214 unsigned int ambient_light_interrupt:1; 214 unsigned int ambient_light_interrupt:1;
215 unsigned int hdmi_audio_encrypt_change:1; 215 unsigned int hdmi_audio_encrypt_change:1;
216 unsigned int pad:6; 216 unsigned int pad:6;
217} __attribute__((packed)); 217} __attribute__((packed));
218 218
219/** 219/**
@@ -225,8 +225,8 @@ struct intel_sdvo_get_interrupt_event_source_response {
225 */ 225 */
226#define SDVO_CMD_SET_TARGET_INPUT 0x10 226#define SDVO_CMD_SET_TARGET_INPUT 0x10
227struct intel_sdvo_set_target_input_args { 227struct intel_sdvo_set_target_input_args {
228 unsigned int target_1:1; 228 unsigned int target_1:1;
229 unsigned int pad:7; 229 unsigned int pad:7;
230} __attribute__((packed)); 230} __attribute__((packed));
231 231
232/** 232/**
@@ -314,57 +314,57 @@ struct intel_sdvo_set_target_input_args {
314#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 314#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
315/** 6 bytes of bit flags for TV formats shared by all TV format functions */ 315/** 6 bytes of bit flags for TV formats shared by all TV format functions */
316struct intel_sdvo_tv_format { 316struct intel_sdvo_tv_format {
317 unsigned int ntsc_m:1; 317 unsigned int ntsc_m:1;
318 unsigned int ntsc_j:1; 318 unsigned int ntsc_j:1;
319 unsigned int ntsc_443:1; 319 unsigned int ntsc_443:1;
320 unsigned int pal_b:1; 320 unsigned int pal_b:1;
321 unsigned int pal_d:1; 321 unsigned int pal_d:1;
322 unsigned int pal_g:1; 322 unsigned int pal_g:1;
323 unsigned int pal_h:1; 323 unsigned int pal_h:1;
324 unsigned int pal_i:1; 324 unsigned int pal_i:1;
325 325
326 unsigned int pal_m:1; 326 unsigned int pal_m:1;
327 unsigned int pal_n:1; 327 unsigned int pal_n:1;
328 unsigned int pal_nc:1; 328 unsigned int pal_nc:1;
329 unsigned int pal_60:1; 329 unsigned int pal_60:1;
330 unsigned int secam_b:1; 330 unsigned int secam_b:1;
331 unsigned int secam_d:1; 331 unsigned int secam_d:1;
332 unsigned int secam_g:1; 332 unsigned int secam_g:1;
333 unsigned int secam_k:1; 333 unsigned int secam_k:1;
334 334
335 unsigned int secam_k1:1; 335 unsigned int secam_k1:1;
336 unsigned int secam_l:1; 336 unsigned int secam_l:1;
337 unsigned int secam_60:1; 337 unsigned int secam_60:1;
338 unsigned int hdtv_std_smpte_240m_1080i_59:1; 338 unsigned int hdtv_std_smpte_240m_1080i_59:1;
339 unsigned int hdtv_std_smpte_240m_1080i_60:1; 339 unsigned int hdtv_std_smpte_240m_1080i_60:1;
340 unsigned int hdtv_std_smpte_260m_1080i_59:1; 340 unsigned int hdtv_std_smpte_260m_1080i_59:1;
341 unsigned int hdtv_std_smpte_260m_1080i_60:1; 341 unsigned int hdtv_std_smpte_260m_1080i_60:1;
342 unsigned int hdtv_std_smpte_274m_1080i_50:1; 342 unsigned int hdtv_std_smpte_274m_1080i_50:1;
343 343
344 unsigned int hdtv_std_smpte_274m_1080i_59:1; 344 unsigned int hdtv_std_smpte_274m_1080i_59:1;
345 unsigned int hdtv_std_smpte_274m_1080i_60:1; 345 unsigned int hdtv_std_smpte_274m_1080i_60:1;
346 unsigned int hdtv_std_smpte_274m_1080p_23:1; 346 unsigned int hdtv_std_smpte_274m_1080p_23:1;
347 unsigned int hdtv_std_smpte_274m_1080p_24:1; 347 unsigned int hdtv_std_smpte_274m_1080p_24:1;
348 unsigned int hdtv_std_smpte_274m_1080p_25:1; 348 unsigned int hdtv_std_smpte_274m_1080p_25:1;
349 unsigned int hdtv_std_smpte_274m_1080p_29:1; 349 unsigned int hdtv_std_smpte_274m_1080p_29:1;
350 unsigned int hdtv_std_smpte_274m_1080p_30:1; 350 unsigned int hdtv_std_smpte_274m_1080p_30:1;
351 unsigned int hdtv_std_smpte_274m_1080p_50:1; 351 unsigned int hdtv_std_smpte_274m_1080p_50:1;
352 352
353 unsigned int hdtv_std_smpte_274m_1080p_59:1; 353 unsigned int hdtv_std_smpte_274m_1080p_59:1;
354 unsigned int hdtv_std_smpte_274m_1080p_60:1; 354 unsigned int hdtv_std_smpte_274m_1080p_60:1;
355 unsigned int hdtv_std_smpte_295m_1080i_50:1; 355 unsigned int hdtv_std_smpte_295m_1080i_50:1;
356 unsigned int hdtv_std_smpte_295m_1080p_50:1; 356 unsigned int hdtv_std_smpte_295m_1080p_50:1;
357 unsigned int hdtv_std_smpte_296m_720p_59:1; 357 unsigned int hdtv_std_smpte_296m_720p_59:1;
358 unsigned int hdtv_std_smpte_296m_720p_60:1; 358 unsigned int hdtv_std_smpte_296m_720p_60:1;
359 unsigned int hdtv_std_smpte_296m_720p_50:1; 359 unsigned int hdtv_std_smpte_296m_720p_50:1;
360 unsigned int hdtv_std_smpte_293m_480p_59:1; 360 unsigned int hdtv_std_smpte_293m_480p_59:1;
361 361
362 unsigned int hdtv_std_smpte_170m_480i_59:1; 362 unsigned int hdtv_std_smpte_170m_480i_59:1;
363 unsigned int hdtv_std_iturbt601_576i_50:1; 363 unsigned int hdtv_std_iturbt601_576i_50:1;
364 unsigned int hdtv_std_iturbt601_576p_50:1; 364 unsigned int hdtv_std_iturbt601_576p_50:1;
365 unsigned int hdtv_std_eia_7702a_480i_60:1; 365 unsigned int hdtv_std_eia_7702a_480i_60:1;
366 unsigned int hdtv_std_eia_7702a_480p_60:1; 366 unsigned int hdtv_std_eia_7702a_480p_60:1;
367 unsigned int pad:3; 367 unsigned int pad:3;
368} __attribute__((packed)); 368} __attribute__((packed));
369 369
370#define SDVO_CMD_GET_TV_FORMAT 0x28 370#define SDVO_CMD_GET_TV_FORMAT 0x28
@@ -374,53 +374,53 @@ struct intel_sdvo_tv_format {
374/** Returns the resolutiosn that can be used with the given TV format */ 374/** Returns the resolutiosn that can be used with the given TV format */
375#define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83 375#define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83
376struct intel_sdvo_sdtv_resolution_request { 376struct intel_sdvo_sdtv_resolution_request {
377 unsigned int ntsc_m:1; 377 unsigned int ntsc_m:1;
378 unsigned int ntsc_j:1; 378 unsigned int ntsc_j:1;
379 unsigned int ntsc_443:1; 379 unsigned int ntsc_443:1;
380 unsigned int pal_b:1; 380 unsigned int pal_b:1;
381 unsigned int pal_d:1; 381 unsigned int pal_d:1;
382 unsigned int pal_g:1; 382 unsigned int pal_g:1;
383 unsigned int pal_h:1; 383 unsigned int pal_h:1;
384 unsigned int pal_i:1; 384 unsigned int pal_i:1;
385 385
386 unsigned int pal_m:1; 386 unsigned int pal_m:1;
387 unsigned int pal_n:1; 387 unsigned int pal_n:1;
388 unsigned int pal_nc:1; 388 unsigned int pal_nc:1;
389 unsigned int pal_60:1; 389 unsigned int pal_60:1;
390 unsigned int secam_b:1; 390 unsigned int secam_b:1;
391 unsigned int secam_d:1; 391 unsigned int secam_d:1;
392 unsigned int secam_g:1; 392 unsigned int secam_g:1;
393 unsigned int secam_k:1; 393 unsigned int secam_k:1;
394 394
395 unsigned int secam_k1:1; 395 unsigned int secam_k1:1;
396 unsigned int secam_l:1; 396 unsigned int secam_l:1;
397 unsigned int secam_60:1; 397 unsigned int secam_60:1;
398 unsigned int pad:5; 398 unsigned int pad:5;
399} __attribute__((packed)); 399} __attribute__((packed));
400 400
401struct intel_sdvo_sdtv_resolution_reply { 401struct intel_sdvo_sdtv_resolution_reply {
402 unsigned int res_320x200:1; 402 unsigned int res_320x200:1;
403 unsigned int res_320x240:1; 403 unsigned int res_320x240:1;
404 unsigned int res_400x300:1; 404 unsigned int res_400x300:1;
405 unsigned int res_640x350:1; 405 unsigned int res_640x350:1;
406 unsigned int res_640x400:1; 406 unsigned int res_640x400:1;
407 unsigned int res_640x480:1; 407 unsigned int res_640x480:1;
408 unsigned int res_704x480:1; 408 unsigned int res_704x480:1;
409 unsigned int res_704x576:1; 409 unsigned int res_704x576:1;
410 410
411 unsigned int res_720x350:1; 411 unsigned int res_720x350:1;
412 unsigned int res_720x400:1; 412 unsigned int res_720x400:1;
413 unsigned int res_720x480:1; 413 unsigned int res_720x480:1;
414 unsigned int res_720x540:1; 414 unsigned int res_720x540:1;
415 unsigned int res_720x576:1; 415 unsigned int res_720x576:1;
416 unsigned int res_768x576:1; 416 unsigned int res_768x576:1;
417 unsigned int res_800x600:1; 417 unsigned int res_800x600:1;
418 unsigned int res_832x624:1; 418 unsigned int res_832x624:1;
419 419
420 unsigned int res_920x766:1; 420 unsigned int res_920x766:1;
421 unsigned int res_1024x768:1; 421 unsigned int res_1024x768:1;
422 unsigned int res_1280x1024:1; 422 unsigned int res_1280x1024:1;
423 unsigned int pad:5; 423 unsigned int pad:5;
424} __attribute__((packed)); 424} __attribute__((packed));
425 425
426/* Get supported resolution with squire pixel aspect ratio that can be 426/* Get supported resolution with squire pixel aspect ratio that can be
@@ -428,90 +428,90 @@ struct intel_sdvo_sdtv_resolution_reply {
428#define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85 428#define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85
429 429
430struct intel_sdvo_hdtv_resolution_request { 430struct intel_sdvo_hdtv_resolution_request {
431 unsigned int hdtv_std_smpte_240m_1080i_59:1; 431 unsigned int hdtv_std_smpte_240m_1080i_59:1;
432 unsigned int hdtv_std_smpte_240m_1080i_60:1; 432 unsigned int hdtv_std_smpte_240m_1080i_60:1;
433 unsigned int hdtv_std_smpte_260m_1080i_59:1; 433 unsigned int hdtv_std_smpte_260m_1080i_59:1;
434 unsigned int hdtv_std_smpte_260m_1080i_60:1; 434 unsigned int hdtv_std_smpte_260m_1080i_60:1;
435 unsigned int hdtv_std_smpte_274m_1080i_50:1; 435 unsigned int hdtv_std_smpte_274m_1080i_50:1;
436 unsigned int hdtv_std_smpte_274m_1080i_59:1; 436 unsigned int hdtv_std_smpte_274m_1080i_59:1;
437 unsigned int hdtv_std_smpte_274m_1080i_60:1; 437 unsigned int hdtv_std_smpte_274m_1080i_60:1;
438 unsigned int hdtv_std_smpte_274m_1080p_23:1; 438 unsigned int hdtv_std_smpte_274m_1080p_23:1;
439 439
440 unsigned int hdtv_std_smpte_274m_1080p_24:1; 440 unsigned int hdtv_std_smpte_274m_1080p_24:1;
441 unsigned int hdtv_std_smpte_274m_1080p_25:1; 441 unsigned int hdtv_std_smpte_274m_1080p_25:1;
442 unsigned int hdtv_std_smpte_274m_1080p_29:1; 442 unsigned int hdtv_std_smpte_274m_1080p_29:1;
443 unsigned int hdtv_std_smpte_274m_1080p_30:1; 443 unsigned int hdtv_std_smpte_274m_1080p_30:1;
444 unsigned int hdtv_std_smpte_274m_1080p_50:1; 444 unsigned int hdtv_std_smpte_274m_1080p_50:1;
445 unsigned int hdtv_std_smpte_274m_1080p_59:1; 445 unsigned int hdtv_std_smpte_274m_1080p_59:1;
446 unsigned int hdtv_std_smpte_274m_1080p_60:1; 446 unsigned int hdtv_std_smpte_274m_1080p_60:1;
447 unsigned int hdtv_std_smpte_295m_1080i_50:1; 447 unsigned int hdtv_std_smpte_295m_1080i_50:1;
448 448
449 unsigned int hdtv_std_smpte_295m_1080p_50:1; 449 unsigned int hdtv_std_smpte_295m_1080p_50:1;
450 unsigned int hdtv_std_smpte_296m_720p_59:1; 450 unsigned int hdtv_std_smpte_296m_720p_59:1;
451 unsigned int hdtv_std_smpte_296m_720p_60:1; 451 unsigned int hdtv_std_smpte_296m_720p_60:1;
452 unsigned int hdtv_std_smpte_296m_720p_50:1; 452 unsigned int hdtv_std_smpte_296m_720p_50:1;
453 unsigned int hdtv_std_smpte_293m_480p_59:1; 453 unsigned int hdtv_std_smpte_293m_480p_59:1;
454 unsigned int hdtv_std_smpte_170m_480i_59:1; 454 unsigned int hdtv_std_smpte_170m_480i_59:1;
455 unsigned int hdtv_std_iturbt601_576i_50:1; 455 unsigned int hdtv_std_iturbt601_576i_50:1;
456 unsigned int hdtv_std_iturbt601_576p_50:1; 456 unsigned int hdtv_std_iturbt601_576p_50:1;
457 457
458 unsigned int hdtv_std_eia_7702a_480i_60:1; 458 unsigned int hdtv_std_eia_7702a_480i_60:1;
459 unsigned int hdtv_std_eia_7702a_480p_60:1; 459 unsigned int hdtv_std_eia_7702a_480p_60:1;
460 unsigned int pad:6; 460 unsigned int pad:6;
461} __attribute__((packed)); 461} __attribute__((packed));
462 462
463struct intel_sdvo_hdtv_resolution_reply { 463struct intel_sdvo_hdtv_resolution_reply {
464 unsigned int res_640x480:1; 464 unsigned int res_640x480:1;
465 unsigned int res_800x600:1; 465 unsigned int res_800x600:1;
466 unsigned int res_1024x768:1; 466 unsigned int res_1024x768:1;
467 unsigned int res_1280x960:1; 467 unsigned int res_1280x960:1;
468 unsigned int res_1400x1050:1; 468 unsigned int res_1400x1050:1;
469 unsigned int res_1600x1200:1; 469 unsigned int res_1600x1200:1;
470 unsigned int res_1920x1440:1; 470 unsigned int res_1920x1440:1;
471 unsigned int res_2048x1536:1; 471 unsigned int res_2048x1536:1;
472 472
473 unsigned int res_2560x1920:1; 473 unsigned int res_2560x1920:1;
474 unsigned int res_3200x2400:1; 474 unsigned int res_3200x2400:1;
475 unsigned int res_3840x2880:1; 475 unsigned int res_3840x2880:1;
476 unsigned int pad1:5; 476 unsigned int pad1:5;
477 477
478 unsigned int res_848x480:1; 478 unsigned int res_848x480:1;
479 unsigned int res_1064x600:1; 479 unsigned int res_1064x600:1;
480 unsigned int res_1280x720:1; 480 unsigned int res_1280x720:1;
481 unsigned int res_1360x768:1; 481 unsigned int res_1360x768:1;
482 unsigned int res_1704x960:1; 482 unsigned int res_1704x960:1;
483 unsigned int res_1864x1050:1; 483 unsigned int res_1864x1050:1;
484 unsigned int res_1920x1080:1; 484 unsigned int res_1920x1080:1;
485 unsigned int res_2128x1200:1; 485 unsigned int res_2128x1200:1;
486 486
487 unsigned int res_2560x1400:1; 487 unsigned int res_2560x1400:1;
488 unsigned int res_2728x1536:1; 488 unsigned int res_2728x1536:1;
489 unsigned int res_3408x1920:1; 489 unsigned int res_3408x1920:1;
490 unsigned int res_4264x2400:1; 490 unsigned int res_4264x2400:1;
491 unsigned int res_5120x2880:1; 491 unsigned int res_5120x2880:1;
492 unsigned int pad2:3; 492 unsigned int pad2:3;
493 493
494 unsigned int res_768x480:1; 494 unsigned int res_768x480:1;
495 unsigned int res_960x600:1; 495 unsigned int res_960x600:1;
496 unsigned int res_1152x720:1; 496 unsigned int res_1152x720:1;
497 unsigned int res_1124x768:1; 497 unsigned int res_1124x768:1;
498 unsigned int res_1536x960:1; 498 unsigned int res_1536x960:1;
499 unsigned int res_1680x1050:1; 499 unsigned int res_1680x1050:1;
500 unsigned int res_1728x1080:1; 500 unsigned int res_1728x1080:1;
501 unsigned int res_1920x1200:1; 501 unsigned int res_1920x1200:1;
502 502
503 unsigned int res_2304x1440:1; 503 unsigned int res_2304x1440:1;
504 unsigned int res_2456x1536:1; 504 unsigned int res_2456x1536:1;
505 unsigned int res_3072x1920:1; 505 unsigned int res_3072x1920:1;
506 unsigned int res_3840x2400:1; 506 unsigned int res_3840x2400:1;
507 unsigned int res_4608x2880:1; 507 unsigned int res_4608x2880:1;
508 unsigned int pad3:3; 508 unsigned int pad3:3;
509 509
510 unsigned int res_1280x1024:1; 510 unsigned int res_1280x1024:1;
511 unsigned int pad4:7; 511 unsigned int pad4:7;
512 512
513 unsigned int res_1280x768:1; 513 unsigned int res_1280x768:1;
514 unsigned int pad5:7; 514 unsigned int pad5:7;
515} __attribute__((packed)); 515} __attribute__((packed));
516 516
517/* Get supported power state returns info for encoder and monitor, rely on 517/* Get supported power state returns info for encoder and monitor, rely on
@@ -539,25 +539,25 @@ struct intel_sdvo_hdtv_resolution_reply {
539 * The high fields are bits 8:9 of the 10-bit values. 539 * The high fields are bits 8:9 of the 10-bit values.
540 */ 540 */
541struct sdvo_panel_power_sequencing { 541struct sdvo_panel_power_sequencing {
542 u8 t0; 542 u8 t0;
543 u8 t1; 543 u8 t1;
544 u8 t2; 544 u8 t2;
545 u8 t3; 545 u8 t3;
546 u8 t4; 546 u8 t4;
547 547
548 unsigned int t0_high:2; 548 unsigned int t0_high:2;
549 unsigned int t1_high:2; 549 unsigned int t1_high:2;
550 unsigned int t2_high:2; 550 unsigned int t2_high:2;
551 unsigned int t3_high:2; 551 unsigned int t3_high:2;
552 552
553 unsigned int t4_high:2; 553 unsigned int t4_high:2;
554 unsigned int pad:6; 554 unsigned int pad:6;
555} __attribute__((packed)); 555} __attribute__((packed));
556 556
557#define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30 557#define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30
558struct sdvo_max_backlight_reply { 558struct sdvo_max_backlight_reply {
559 u8 max_value; 559 u8 max_value;
560 u8 default_value; 560 u8 default_value;
561} __attribute__((packed)); 561} __attribute__((packed));
562 562
563#define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31 563#define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31
@@ -565,16 +565,16 @@ struct sdvo_max_backlight_reply {
565 565
566#define SDVO_CMD_GET_AMBIENT_LIGHT 0x33 566#define SDVO_CMD_GET_AMBIENT_LIGHT 0x33
567struct sdvo_get_ambient_light_reply { 567struct sdvo_get_ambient_light_reply {
568 u16 trip_low; 568 u16 trip_low;
569 u16 trip_high; 569 u16 trip_high;
570 u16 value; 570 u16 value;
571} __attribute__((packed)); 571} __attribute__((packed));
572#define SDVO_CMD_SET_AMBIENT_LIGHT 0x34 572#define SDVO_CMD_SET_AMBIENT_LIGHT 0x34
573struct sdvo_set_ambient_light_reply { 573struct sdvo_set_ambient_light_reply {
574 u16 trip_low; 574 u16 trip_low;
575 u16 trip_high; 575 u16 trip_high;
576 unsigned int enable:1; 576 unsigned int enable:1;
577 unsigned int pad:7; 577 unsigned int pad:7;
578} __attribute__((packed)); 578} __attribute__((packed));
579 579
580/* Set display power state */ 580/* Set display power state */
@@ -586,23 +586,23 @@ struct sdvo_set_ambient_light_reply {
586 586
587#define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84 587#define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84
588struct intel_sdvo_enhancements_reply { 588struct intel_sdvo_enhancements_reply {
589 unsigned int flicker_filter:1; 589 unsigned int flicker_filter:1;
590 unsigned int flicker_filter_adaptive:1; 590 unsigned int flicker_filter_adaptive:1;
591 unsigned int flicker_filter_2d:1; 591 unsigned int flicker_filter_2d:1;
592 unsigned int saturation:1; 592 unsigned int saturation:1;
593 unsigned int hue:1; 593 unsigned int hue:1;
594 unsigned int brightness:1; 594 unsigned int brightness:1;
595 unsigned int contrast:1; 595 unsigned int contrast:1;
596 unsigned int overscan_h:1; 596 unsigned int overscan_h:1;
597 597
598 unsigned int overscan_v:1; 598 unsigned int overscan_v:1;
599 unsigned int hpos:1; 599 unsigned int hpos:1;
600 unsigned int vpos:1; 600 unsigned int vpos:1;
601 unsigned int sharpness:1; 601 unsigned int sharpness:1;
602 unsigned int dot_crawl:1; 602 unsigned int dot_crawl:1;
603 unsigned int dither:1; 603 unsigned int dither:1;
604 unsigned int tv_chroma_filter:1; 604 unsigned int tv_chroma_filter:1;
605 unsigned int tv_luma_filter:1; 605 unsigned int tv_luma_filter:1;
606} __attribute__((packed)); 606} __attribute__((packed));
607 607
608/* Picture enhancement limits below are dependent on the current TV format, 608/* Picture enhancement limits below are dependent on the current TV format,
@@ -623,8 +623,8 @@ struct intel_sdvo_enhancements_reply {
623#define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74 623#define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74
624#define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77 624#define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77
625struct intel_sdvo_enhancement_limits_reply { 625struct intel_sdvo_enhancement_limits_reply {
626 u16 max_value; 626 u16 max_value;
627 u16 default_value; 627 u16 default_value;
628} __attribute__((packed)); 628} __attribute__((packed));
629 629
630#define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f 630#define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f
@@ -665,8 +665,8 @@ struct intel_sdvo_enhancement_limits_reply {
665#define SDVO_CMD_GET_TV_LUMA_FILTER 0x78 665#define SDVO_CMD_GET_TV_LUMA_FILTER 0x78
666#define SDVO_CMD_SET_TV_LUMA_FILTER 0x79 666#define SDVO_CMD_SET_TV_LUMA_FILTER 0x79
667struct intel_sdvo_enhancements_arg { 667struct intel_sdvo_enhancements_arg {
668 u16 value; 668 u16 value;
669}__attribute__((packed)); 669} __attribute__((packed));
670 670
671#define SDVO_CMD_GET_DOT_CRAWL 0x70 671#define SDVO_CMD_GET_DOT_CRAWL 0x70
672#define SDVO_CMD_SET_DOT_CRAWL 0x71 672#define SDVO_CMD_SET_DOT_CRAWL 0x71
@@ -717,7 +717,7 @@ struct intel_sdvo_enhancements_arg {
717#define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c 717#define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c
718#define SDVO_NEED_TO_STALL (1 << 7) 718#define SDVO_NEED_TO_STALL (1 << 7)
719 719
720struct intel_sdvo_encode{ 720struct intel_sdvo_encode {
721 u8 dvi_rev; 721 u8 dvi_rev;
722 u8 hdmi_rev; 722 u8 hdmi_rev;
723} __attribute__ ((packed)); 723} __attribute__ ((packed));
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 210d570fd516..f3c6a9a8b081 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -194,10 +194,10 @@ static const u32 filter_table[] = {
194 * 194 *
195 * if (f >= 1) { 195 * if (f >= 1) {
196 * exp = 0x7; 196 * exp = 0x7;
197 * mant = 1 << 8; 197 * mant = 1 << 8;
198 * } else { 198 * } else {
199 * for (exp = 0; exp < 3 && f < 0.5; exp++) 199 * for (exp = 0; exp < 3 && f < 0.5; exp++)
200 * f *= 2.0; 200 * f *= 2.0;
201 * mant = (f * (1 << 9) + 0.5); 201 * mant = (f * (1 << 9) + 0.5);
202 * if (mant >= (1 << 9)) 202 * if (mant >= (1 << 9))
203 * mant = (1 << 9) - 1; 203 * mant = (1 << 9) - 1;
@@ -430,7 +430,7 @@ static const struct tv_mode tv_modes[] = {
430 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 430 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
431 .vsync_len = 6, 431 .vsync_len = 6,
432 432
433 .veq_ena = true, .veq_start_f1 = 0, 433 .veq_ena = true, .veq_start_f1 = 0,
434 .veq_start_f2 = 1, .veq_len = 18, 434 .veq_start_f2 = 1, .veq_len = 18,
435 435
436 .vi_end_f1 = 20, .vi_end_f2 = 21, 436 .vi_end_f1 = 20, .vi_end_f2 = 21,
@@ -472,7 +472,7 @@ static const struct tv_mode tv_modes[] = {
472 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 472 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
473 .vsync_len = 6, 473 .vsync_len = 6,
474 474
475 .veq_ena = true, .veq_start_f1 = 0, 475 .veq_ena = true, .veq_start_f1 = 0,
476 .veq_start_f2 = 1, .veq_len = 18, 476 .veq_start_f2 = 1, .veq_len = 18,
477 477
478 .vi_end_f1 = 20, .vi_end_f2 = 21, 478 .vi_end_f1 = 20, .vi_end_f2 = 21,
@@ -515,7 +515,7 @@ static const struct tv_mode tv_modes[] = {
515 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 515 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
516 .vsync_len = 6, 516 .vsync_len = 6,
517 517
518 .veq_ena = true, .veq_start_f1 = 0, 518 .veq_ena = true, .veq_start_f1 = 0,
519 .veq_start_f2 = 1, .veq_len = 18, 519 .veq_start_f2 = 1, .veq_len = 18,
520 520
521 .vi_end_f1 = 20, .vi_end_f2 = 21, 521 .vi_end_f1 = 20, .vi_end_f2 = 21,
@@ -558,7 +558,7 @@ static const struct tv_mode tv_modes[] = {
558 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 558 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
559 .vsync_len = 6, 559 .vsync_len = 6,
560 560
561 .veq_ena = true, .veq_start_f1 = 0, 561 .veq_ena = true, .veq_start_f1 = 0,
562 .veq_start_f2 = 1, .veq_len = 18, 562 .veq_start_f2 = 1, .veq_len = 18,
563 563
564 .vi_end_f1 = 20, .vi_end_f2 = 21, 564 .vi_end_f1 = 20, .vi_end_f2 = 21,
@@ -602,14 +602,14 @@ static const struct tv_mode tv_modes[] = {
602 .vsync_start_f1 = 6, .vsync_start_f2 = 7, 602 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
603 .vsync_len = 6, 603 .vsync_len = 6,
604 604
605 .veq_ena = true, .veq_start_f1 = 0, 605 .veq_ena = true, .veq_start_f1 = 0,
606 .veq_start_f2 = 1, .veq_len = 18, 606 .veq_start_f2 = 1, .veq_len = 18,
607 607
608 .vi_end_f1 = 24, .vi_end_f2 = 25, 608 .vi_end_f1 = 24, .vi_end_f2 = 25,
609 .nbr_end = 286, 609 .nbr_end = 286,
610 610
611 .burst_ena = true, 611 .burst_ena = true,
612 .hburst_start = 73, .hburst_len = 34, 612 .hburst_start = 73, .hburst_len = 34,
613 .vburst_start_f1 = 8, .vburst_end_f1 = 285, 613 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
614 .vburst_start_f2 = 8, .vburst_end_f2 = 286, 614 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
615 .vburst_start_f3 = 9, .vburst_end_f3 = 286, 615 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
@@ -646,7 +646,7 @@ static const struct tv_mode tv_modes[] = {
646 .vsync_start_f1 = 5, .vsync_start_f2 = 6, 646 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
647 .vsync_len = 5, 647 .vsync_len = 5,
648 648
649 .veq_ena = true, .veq_start_f1 = 0, 649 .veq_ena = true, .veq_start_f1 = 0,
650 .veq_start_f2 = 1, .veq_len = 15, 650 .veq_start_f2 = 1, .veq_len = 15,
651 651
652 .vi_end_f1 = 24, .vi_end_f2 = 25, 652 .vi_end_f1 = 24, .vi_end_f2 = 25,
@@ -675,7 +675,7 @@ static const struct tv_mode tv_modes[] = {
675 }, 675 },
676 { 676 {
677 .name = "480p@59.94Hz", 677 .name = "480p@59.94Hz",
678 .clock = 107520, 678 .clock = 107520,
679 .refresh = 59940, 679 .refresh = 59940,
680 .oversample = TV_OVERSAMPLE_4X, 680 .oversample = TV_OVERSAMPLE_4X,
681 .component_only = 1, 681 .component_only = 1,
@@ -683,7 +683,7 @@ static const struct tv_mode tv_modes[] = {
683 .hsync_end = 64, .hblank_end = 122, 683 .hsync_end = 64, .hblank_end = 122,
684 .hblank_start = 842, .htotal = 857, 684 .hblank_start = 842, .htotal = 857,
685 685
686 .progressive = true,.trilevel_sync = false, 686 .progressive = true, .trilevel_sync = false,
687 687
688 .vsync_start_f1 = 12, .vsync_start_f2 = 12, 688 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
689 .vsync_len = 12, 689 .vsync_len = 12,
@@ -699,7 +699,7 @@ static const struct tv_mode tv_modes[] = {
699 }, 699 },
700 { 700 {
701 .name = "480p@60Hz", 701 .name = "480p@60Hz",
702 .clock = 107520, 702 .clock = 107520,
703 .refresh = 60000, 703 .refresh = 60000,
704 .oversample = TV_OVERSAMPLE_4X, 704 .oversample = TV_OVERSAMPLE_4X,
705 .component_only = 1, 705 .component_only = 1,
@@ -707,7 +707,7 @@ static const struct tv_mode tv_modes[] = {
707 .hsync_end = 64, .hblank_end = 122, 707 .hsync_end = 64, .hblank_end = 122,
708 .hblank_start = 842, .htotal = 856, 708 .hblank_start = 842, .htotal = 856,
709 709
710 .progressive = true,.trilevel_sync = false, 710 .progressive = true, .trilevel_sync = false,
711 711
712 .vsync_start_f1 = 12, .vsync_start_f2 = 12, 712 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
713 .vsync_len = 12, 713 .vsync_len = 12,
@@ -723,7 +723,7 @@ static const struct tv_mode tv_modes[] = {
723 }, 723 },
724 { 724 {
725 .name = "576p", 725 .name = "576p",
726 .clock = 107520, 726 .clock = 107520,
727 .refresh = 50000, 727 .refresh = 50000,
728 .oversample = TV_OVERSAMPLE_4X, 728 .oversample = TV_OVERSAMPLE_4X,
729 .component_only = 1, 729 .component_only = 1,
@@ -755,7 +755,7 @@ static const struct tv_mode tv_modes[] = {
755 .hsync_end = 80, .hblank_end = 300, 755 .hsync_end = 80, .hblank_end = 300,
756 .hblank_start = 1580, .htotal = 1649, 756 .hblank_start = 1580, .htotal = 1649,
757 757
758 .progressive = true, .trilevel_sync = true, 758 .progressive = true, .trilevel_sync = true,
759 759
760 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 760 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
761 .vsync_len = 10, 761 .vsync_len = 10,
@@ -779,7 +779,7 @@ static const struct tv_mode tv_modes[] = {
779 .hsync_end = 80, .hblank_end = 300, 779 .hsync_end = 80, .hblank_end = 300,
780 .hblank_start = 1580, .htotal = 1651, 780 .hblank_start = 1580, .htotal = 1651,
781 781
782 .progressive = true, .trilevel_sync = true, 782 .progressive = true, .trilevel_sync = true,
783 783
784 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 784 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
785 .vsync_len = 10, 785 .vsync_len = 10,
@@ -803,7 +803,7 @@ static const struct tv_mode tv_modes[] = {
803 .hsync_end = 80, .hblank_end = 300, 803 .hsync_end = 80, .hblank_end = 300,
804 .hblank_start = 1580, .htotal = 1979, 804 .hblank_start = 1580, .htotal = 1979,
805 805
806 .progressive = true, .trilevel_sync = true, 806 .progressive = true, .trilevel_sync = true,
807 807
808 .vsync_start_f1 = 10, .vsync_start_f2 = 10, 808 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
809 .vsync_len = 10, 809 .vsync_len = 10,
@@ -828,12 +828,12 @@ static const struct tv_mode tv_modes[] = {
828 .hsync_end = 88, .hblank_end = 235, 828 .hsync_end = 88, .hblank_end = 235,
829 .hblank_start = 2155, .htotal = 2639, 829 .hblank_start = 2155, .htotal = 2639,
830 830
831 .progressive = false, .trilevel_sync = true, 831 .progressive = false, .trilevel_sync = true,
832 832
833 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 833 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
834 .vsync_len = 10, 834 .vsync_len = 10,
835 835
836 .veq_ena = true, .veq_start_f1 = 4, 836 .veq_ena = true, .veq_start_f1 = 4,
837 .veq_start_f2 = 4, .veq_len = 10, 837 .veq_start_f2 = 4, .veq_len = 10,
838 838
839 839
@@ -854,12 +854,12 @@ static const struct tv_mode tv_modes[] = {
854 .hsync_end = 88, .hblank_end = 235, 854 .hsync_end = 88, .hblank_end = 235,
855 .hblank_start = 2155, .htotal = 2199, 855 .hblank_start = 2155, .htotal = 2199,
856 856
857 .progressive = false, .trilevel_sync = true, 857 .progressive = false, .trilevel_sync = true,
858 858
859 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 859 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
860 .vsync_len = 10, 860 .vsync_len = 10,
861 861
862 .veq_ena = true, .veq_start_f1 = 4, 862 .veq_ena = true, .veq_start_f1 = 4,
863 .veq_start_f2 = 4, .veq_len = 10, 863 .veq_start_f2 = 4, .veq_len = 10,
864 864
865 865
@@ -880,16 +880,16 @@ static const struct tv_mode tv_modes[] = {
880 .hsync_end = 88, .hblank_end = 235, 880 .hsync_end = 88, .hblank_end = 235,
881 .hblank_start = 2155, .htotal = 2201, 881 .hblank_start = 2155, .htotal = 2201,
882 882
883 .progressive = false, .trilevel_sync = true, 883 .progressive = false, .trilevel_sync = true,
884 884
885 .vsync_start_f1 = 4, .vsync_start_f2 = 5, 885 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
886 .vsync_len = 10, 886 .vsync_len = 10,
887 887
888 .veq_ena = true, .veq_start_f1 = 4, 888 .veq_ena = true, .veq_start_f1 = 4,
889 .veq_start_f2 = 4, .veq_len = 10, 889 .veq_start_f2 = 4, .veq_len = 10,
890 890
891 891
892 .vi_end_f1 = 21, .vi_end_f2 = 22, 892 .vi_end_f1 = 21, .vi_end_f2 = 22,
893 .nbr_end = 539, 893 .nbr_end = 539,
894 894
895 .burst_ena = false, 895 .burst_ena = false,
@@ -916,7 +916,7 @@ intel_tv_dpms(struct drm_encoder *encoder, int mode)
916 struct drm_device *dev = encoder->dev; 916 struct drm_device *dev = encoder->dev;
917 struct drm_i915_private *dev_priv = dev->dev_private; 917 struct drm_i915_private *dev_priv = dev->dev_private;
918 918
919 switch(mode) { 919 switch (mode) {
920 case DRM_MODE_DPMS_ON: 920 case DRM_MODE_DPMS_ON:
921 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); 921 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
922 break; 922 break;
@@ -933,7 +933,7 @@ intel_tv_mode_lookup(const char *tv_format)
933{ 933{
934 int i; 934 int i;
935 935
936 for (i = 0; i < sizeof(tv_modes) / sizeof (tv_modes[0]); i++) { 936 for (i = 0; i < sizeof(tv_modes) / sizeof(tv_modes[0]); i++) {
937 const struct tv_mode *tv_mode = &tv_modes[i]; 937 const struct tv_mode *tv_mode = &tv_modes[i];
938 938
939 if (!strcmp(tv_format, tv_mode->name)) 939 if (!strcmp(tv_format, tv_mode->name))
@@ -1128,7 +1128,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1128 if (color_conversion) { 1128 if (color_conversion) {
1129 I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) | 1129 I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
1130 color_conversion->gy); 1130 color_conversion->gy);
1131 I915_WRITE(TV_CSC_Y2,(color_conversion->by << 16) | 1131 I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
1132 color_conversion->ay); 1132 color_conversion->ay);
1133 I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) | 1133 I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
1134 color_conversion->gu); 1134 color_conversion->gu);
@@ -1232,7 +1232,7 @@ static const struct drm_display_mode reported_modes[] = {
1232 * \return false if TV is disconnected. 1232 * \return false if TV is disconnected.
1233 */ 1233 */
1234static int 1234static int
1235intel_tv_detect_type (struct intel_tv *intel_tv, 1235intel_tv_detect_type(struct intel_tv *intel_tv,
1236 struct drm_connector *connector) 1236 struct drm_connector *connector)
1237{ 1237{
1238 struct drm_encoder *encoder = &intel_tv->base.base; 1238 struct drm_encoder *encoder = &intel_tv->base.base;
@@ -1486,7 +1486,7 @@ intel_tv_get_modes(struct drm_connector *connector)
1486} 1486}
1487 1487
1488static void 1488static void
1489intel_tv_destroy (struct drm_connector *connector) 1489intel_tv_destroy(struct drm_connector *connector)
1490{ 1490{
1491 drm_sysfs_connector_remove(connector); 1491 drm_sysfs_connector_remove(connector);
1492 drm_connector_cleanup(connector); 1492 drm_connector_cleanup(connector);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 17:34:35 -0500