drm/i915: Extract intel_prepare_shared_dpll

This is the last piece of code which write state to the hardware in
the ironalake ->crtc_mode_set callback.

I think we could merge this with the pll->enable hook, but otoh the
ordering requirements with the ldvs port are really tricky. Doing the
FP0/1 writes up-front before we even prepare the lvds port (in the
pre_pll_enable hook) like on i9xx seems safest.

With this ilk+ platforms are now ready for runtime PM with DPMS. Since
hsw/bdw also support runtime pm besides snb we need to first make the
haswell code save before we can touch the core code.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 19 insertions, 7 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 88d47d531bf0..7def8dd0e8a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1739,6 +1739,22 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
                      port_name(dport->port), I915_READ(dpll_reg));
 }
 
+static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
+{
+        struct drm_device *dev = crtc->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+
+        WARN_ON(!pll->refcount);
+        if (pll->active == 0) {
+                DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
+                WARN_ON(pll->on);
+                assert_shared_dpll_disabled(dev_priv, pll);
+
+                pll->mode_set(dev_priv, pll);
+        }
+}
+
 /**
  * ironlake_enable_shared_dpll - enable PCH PLL
  * @dev_priv: i915 private structure
@@ -3644,13 +3660,6 @@ found:
         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
                          pipe_name(crtc->pipe));
 
-        if (pll->active == 0) {
-                DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
-                WARN_ON(pll->on);
-                assert_shared_dpll_disabled(dev_priv, pll);
-
-                pll->mode_set(dev_priv, pll);
-        }
         pll->refcount++;
 
         return pll;
@@ -3926,6 +3935,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
         if (intel_crtc->active)
                 return;
 
+        if (intel_crtc->config.has_pch_encoder)
+                intel_prepare_shared_dpll(intel_crtc);
+
         if (intel_crtc->config.has_dp_encoder)
                 intel_dp_set_m_n(intel_crtc);