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authorDaniel Vetter <daniel.vetter@ffwll.ch>2010-09-24 15:14:22 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-25 07:23:15 -0400
commit3d281d8cca1acb2483444e0d1519c8ab6dda3a47 (patch)
tree9d40394e09361254aa1c8208f5b56dfbd1a31cf1 /drivers/gpu/drm
parentbf7e0e1268f72ea1687140603a910eeaca031fa1 (diff)
drm/i915: kill per-ring macros
Two macros that use a base address for HWS_PGA were missing, add them. Also switch the remaining users of *_ACTHD to the ring-base one. Kill the other ring-specific macros because they're now unused. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [ickle: And silence checkpatch whilst in the vicinity] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h35
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c25
2 files changed, 21 insertions, 39 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 605db647e920..ddbcd8c109e0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -253,11 +253,13 @@
253#define RENDER_RING_BASE 0x02000 253#define RENDER_RING_BASE 0x02000
254#define BSD_RING_BASE 0x04000 254#define BSD_RING_BASE 0x04000
255#define GEN6_BSD_RING_BASE 0x12000 255#define GEN6_BSD_RING_BASE 0x12000
256#define RING_TAIL(base) (base)+0x30 256#define RING_TAIL(base) ((base)+0x30)
257#define RING_HEAD(base) (base)+0x34 257#define RING_HEAD(base) ((base)+0x34)
258#define RING_START(base) (base)+0x38 258#define RING_START(base) ((base)+0x38)
259#define RING_CTL(base) (base)+0x3c 259#define RING_CTL(base) ((base)+0x3c)
260#define RING_HWS_PGA(base) (base)+0x80 260#define RING_HWS_PGA(base) ((base)+0x80)
261#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
262#define RING_ACTHD(base) ((base)+0x74)
261#define TAIL_ADDR 0x001FFFF8 263#define TAIL_ADDR 0x001FFFF8
262#define HEAD_WRAP_COUNT 0xFFE00000 264#define HEAD_WRAP_COUNT 0xFFE00000
263#define HEAD_WRAP_ONE 0x00200000 265#define HEAD_WRAP_ONE 0x00200000
@@ -283,7 +285,6 @@
283#define INSTDONE1 0x0207c /* 965+ only */ 285#define INSTDONE1 0x0207c /* 965+ only */
284#define ACTHD_I965 0x02074 286#define ACTHD_I965 0x02074
285#define HWS_PGA 0x02080 287#define HWS_PGA 0x02080
286#define HWS_PGA_GEN6 0x04080
287#define HWS_ADDRESS_MASK 0xfffff000 288#define HWS_ADDRESS_MASK 0xfffff000
288#define HWS_START_ADDRESS_SHIFT 4 289#define HWS_START_ADDRESS_SHIFT 4
289#define PWRCTXA 0x2088 /* 965GM+ only */ 290#define PWRCTXA 0x2088 /* 965GM+ only */
@@ -441,28 +442,6 @@
441#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) 442#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
442#define GEN6_BLITTER_SYNC_STATUS (1 << 24) 443#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
443#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) 444#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
444/*
445 * BSD (bit stream decoder instruction and interrupt control register defines
446 * (G4X and Ironlake only)
447 */
448
449#define BSD_RING_TAIL 0x04030
450#define BSD_RING_HEAD 0x04034
451#define BSD_RING_START 0x04038
452#define BSD_RING_CTL 0x0403c
453#define BSD_RING_ACTHD 0x04074
454#define BSD_HWS_PGA 0x04080
455
456/*
457 * video command stream instruction and interrupt control register defines
458 * for GEN6
459 */
460#define GEN6_BSD_RING_TAIL 0x12030
461#define GEN6_BSD_RING_HEAD 0x12034
462#define GEN6_BSD_RING_START 0x12038
463#define GEN6_BSD_RING_CTL 0x1203c
464#define GEN6_BSD_RING_ACTHD 0x12074
465#define GEN6_BSD_HWS_PGA 0x14080
466 445
467#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 446#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
468#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) 447#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ede436ba22d2..487575f2340d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -131,7 +131,8 @@ static unsigned int render_ring_get_active_head(struct drm_device *dev,
131 struct intel_ring_buffer *ring) 131 struct intel_ring_buffer *ring)
132{ 132{
133 drm_i915_private_t *dev_priv = dev->dev_private; 133 drm_i915_private_t *dev_priv = dev->dev_private;
134 u32 acthd_reg = INTEL_INFO(dev)->gen >= 4 ? ACTHD_I965 : ACTHD; 134 u32 acthd_reg = INTEL_INFO(dev)->gen >= 4 ?
135 RING_ACTHD(ring->mmio_base) : ACTHD;
135 136
136 return I915_READ(acthd_reg); 137 return I915_READ(acthd_reg);
137} 138}
@@ -352,11 +353,13 @@ static void render_setup_status_page(struct drm_device *dev,
352{ 353{
353 drm_i915_private_t *dev_priv = dev->dev_private; 354 drm_i915_private_t *dev_priv = dev->dev_private;
354 if (IS_GEN6(dev)) { 355 if (IS_GEN6(dev)) {
355 I915_WRITE(HWS_PGA_GEN6, ring->status_page.gfx_addr); 356 I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base),
356 I915_READ(HWS_PGA_GEN6); /* posting read */ 357 ring->status_page.gfx_addr);
358 I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base)); /* posting read */
357 } else { 359 } else {
358 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); 360 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
359 I915_READ(HWS_PGA); /* posting read */ 361 ring->status_page.gfx_addr);
362 I915_READ(RING_HWS_PGA(ring->mmio_base)); /* posting read */
360 } 363 }
361 364
362} 365}
@@ -377,7 +380,7 @@ static unsigned int bsd_ring_get_active_head(struct drm_device *dev,
377 struct intel_ring_buffer *ring) 380 struct intel_ring_buffer *ring)
378{ 381{
379 drm_i915_private_t *dev_priv = dev->dev_private; 382 drm_i915_private_t *dev_priv = dev->dev_private;
380 return I915_READ(BSD_RING_ACTHD); 383 return I915_READ(RING_ACTHD(ring->mmio_base));
381} 384}
382 385
383static int init_bsd_ring(struct drm_device *dev, 386static int init_bsd_ring(struct drm_device *dev,
@@ -412,8 +415,8 @@ static void bsd_setup_status_page(struct drm_device *dev,
412 struct intel_ring_buffer *ring) 415 struct intel_ring_buffer *ring)
413{ 416{
414 drm_i915_private_t *dev_priv = dev->dev_private; 417 drm_i915_private_t *dev_priv = dev->dev_private;
415 I915_WRITE(BSD_HWS_PGA, ring->status_page.gfx_addr); 418 I915_WRITE(RING_HWS_PGA(ring->mmio_base), ring->status_page.gfx_addr);
416 I915_READ(BSD_HWS_PGA); 419 I915_READ(RING_HWS_PGA(ring->mmio_base));
417} 420}
418 421
419static void 422static void
@@ -801,8 +804,8 @@ static void gen6_bsd_setup_status_page(struct drm_device *dev,
801 struct intel_ring_buffer *ring) 804 struct intel_ring_buffer *ring)
802{ 805{
803 drm_i915_private_t *dev_priv = dev->dev_private; 806 drm_i915_private_t *dev_priv = dev->dev_private;
804 I915_WRITE(GEN6_BSD_HWS_PGA, ring->status_page.gfx_addr); 807 I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base), ring->status_page.gfx_addr);
805 I915_READ(GEN6_BSD_HWS_PGA); 808 I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base));
806} 809}
807 810
808static void gen6_bsd_ring_set_tail(struct drm_device *dev, 811static void gen6_bsd_ring_set_tail(struct drm_device *dev,
@@ -832,7 +835,7 @@ static unsigned int gen6_bsd_ring_get_active_head(struct drm_device *dev,
832 struct intel_ring_buffer *ring) 835 struct intel_ring_buffer *ring)
833{ 836{
834 drm_i915_private_t *dev_priv = dev->dev_private; 837 drm_i915_private_t *dev_priv = dev->dev_private;
835 return I915_READ(GEN6_BSD_RING_ACTHD); 838 return I915_READ(RING_ACTHD(ring->mmio_base));
836} 839}
837 840
838static void gen6_bsd_ring_flush(struct drm_device *dev, 841static void gen6_bsd_ring_flush(struct drm_device *dev,