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authorAlan Cox <alan@linux.intel.com>2012-08-08 09:54:15 -0400
committerDave Airlie <airlied@redhat.com>2012-08-23 19:29:06 -0400
commit8695b612943561478fd22f28f45e5692e5d078db (patch)
treed14c00e7f9390a548b80265399acb776f82f2ec9 /drivers/gpu/drm
parentd66760962d75af12697d5197b3e97d51fe64169c (diff)
gma500: Add the support of display port on CDV
Import the pieces we need in order to do DisplayPort. Don't wire them up yet as there is work to do to integrate them. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/gma500/cdv_intel_dp.c1504
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_drv.h6
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_reg.h155
3 files changed, 1661 insertions, 4 deletions
diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c
new file mode 100644
index 000000000000..c6d545d42923
--- /dev/null
+++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
@@ -0,0 +1,1504 @@
1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include <linux/slab.h>
30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
34#include "psb_drv.h"
35#include "psb_intel_drv.h"
36#include "psb_drm.h"
37#include "psb_intel_reg.h"
38#include "drm_dp_helper.h"
39
40
41#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44#define DP_LINK_CONFIGURATION_SIZE 9
45
46#define CDV_FAST_LINK_TRAIN 1
47
48struct psb_intel_dp {
49 uint32_t output_reg;
50 uint32_t DP;
51 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
52 bool has_audio;
53 int force_audio;
54 uint32_t color_range;
55 uint8_t link_bw;
56 uint8_t lane_count;
57 uint8_t dpcd[4];
58 struct psb_intel_output *output;
59 struct i2c_adapter adapter;
60 struct i2c_algo_dp_aux_data algo;
61 uint8_t train_set[4];
62 uint8_t link_status[DP_LINK_STATUS_SIZE];
63};
64
65struct ddi_regoff {
66 uint32_t PreEmph1;
67 uint32_t PreEmph2;
68 uint32_t VSwing1;
69 uint32_t VSwing2;
70 uint32_t VSwing3;
71 uint32_t VSwing4;
72 uint32_t VSwing5;
73};
74
75static struct ddi_regoff ddi_DP_train_table[] = {
76 {.PreEmph1 = 0x812c, .PreEmph2 = 0x8124, .VSwing1 = 0x8154,
77 .VSwing2 = 0x8148, .VSwing3 = 0x814C, .VSwing4 = 0x8150,
78 .VSwing5 = 0x8158,},
79 {.PreEmph1 = 0x822c, .PreEmph2 = 0x8224, .VSwing1 = 0x8254,
80 .VSwing2 = 0x8248, .VSwing3 = 0x824C, .VSwing4 = 0x8250,
81 .VSwing5 = 0x8258,},
82};
83
84static uint32_t dp_vswing_premph_table[] = {
85 0x55338954, 0x4000,
86 0x554d8954, 0x2000,
87 0x55668954, 0,
88 0x559ac0d4, 0x6000,
89};
90/**
91 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
92 * @intel_dp: DP struct
93 *
94 * If a CPU or PCH DP output is attached to an eDP panel, this function
95 * will return true, and false otherwise.
96 */
97static bool is_edp(struct psb_intel_output *output)
98{
99 return output->type == INTEL_OUTPUT_EDP;
100}
101
102
103static void psb_intel_dp_start_link_train(struct psb_intel_output *output);
104static void psb_intel_dp_complete_link_train(struct psb_intel_output *output);
105static void psb_intel_dp_link_down(struct psb_intel_output *output);
106
107static int
108psb_intel_dp_max_lane_count(struct psb_intel_output *output)
109{
110 struct psb_intel_dp *intel_dp = output->dev_priv;
111 int max_lane_count = 4;
112
113 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
114 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
115 switch (max_lane_count) {
116 case 1: case 2: case 4:
117 break;
118 default:
119 max_lane_count = 4;
120 }
121 }
122 return max_lane_count;
123}
124
125static int
126psb_intel_dp_max_link_bw(struct psb_intel_output *output)
127{
128 struct psb_intel_dp *intel_dp = output->dev_priv;
129 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
130
131 switch (max_link_bw) {
132 case DP_LINK_BW_1_62:
133 case DP_LINK_BW_2_7:
134 break;
135 default:
136 max_link_bw = DP_LINK_BW_1_62;
137 break;
138 }
139 return max_link_bw;
140}
141
142static int
143psb_intel_dp_link_clock(uint8_t link_bw)
144{
145 if (link_bw == DP_LINK_BW_2_7)
146 return 270000;
147 else
148 return 162000;
149}
150
151static int
152psb_intel_dp_link_required(int pixel_clock, int bpp)
153{
154 return (pixel_clock * bpp + 7) / 8;
155}
156
157static int
158psb_intel_dp_max_data_rate(int max_link_clock, int max_lanes)
159{
160 return (max_link_clock * max_lanes * 19) / 20;
161}
162
163static int
164psb_intel_dp_mode_valid(struct drm_connector *connector,
165 struct drm_display_mode *mode)
166{
167 struct psb_intel_output *output = to_psb_intel_output(connector);
168 struct drm_device *dev = connector->dev;
169 struct drm_psb_private *dev_priv = dev->dev_private;
170 int max_link_clock = psb_intel_dp_link_clock(psb_intel_dp_max_link_bw(output));
171 int max_lanes = psb_intel_dp_max_lane_count(output);
172
173 if (is_edp(output) && dev_priv->panel_fixed_mode) {
174 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
175 return MODE_PANEL;
176
177 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
178 return MODE_PANEL;
179 }
180
181 /* only refuse the mode on non eDP since we have seen some weird eDP panels
182 which are outside spec tolerances but somehow work by magic */
183 if (!is_edp(output) &&
184 (psb_intel_dp_link_required(mode->clock, 24)
185 > psb_intel_dp_max_data_rate(max_link_clock, max_lanes)))
186 return MODE_CLOCK_HIGH;
187
188 if (mode->clock < 10000)
189 return MODE_CLOCK_LOW;
190
191 return MODE_OK;
192}
193
194static uint32_t
195pack_aux(uint8_t *src, int src_bytes)
196{
197 int i;
198 uint32_t v = 0;
199
200 if (src_bytes > 4)
201 src_bytes = 4;
202 for (i = 0; i < src_bytes; i++)
203 v |= ((uint32_t) src[i]) << ((3-i) * 8);
204 return v;
205}
206
207static void
208unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
209{
210 int i;
211 if (dst_bytes > 4)
212 dst_bytes = 4;
213 for (i = 0; i < dst_bytes; i++)
214 dst[i] = src >> ((3-i) * 8);
215}
216
217static int
218psb_intel_dp_aux_ch(struct psb_intel_output *output,
219 uint8_t *send, int send_bytes,
220 uint8_t *recv, int recv_size)
221{
222 struct psb_intel_dp *intel_dp = output->dev_priv;
223 uint32_t output_reg = intel_dp->output_reg;
224 struct drm_device *dev = output->base.dev;
225 uint32_t ch_ctl = output_reg + 0x10;
226 uint32_t ch_data = ch_ctl + 4;
227 int i;
228 int recv_bytes;
229 uint32_t status;
230 uint32_t aux_clock_divider;
231 int try, precharge;
232
233 /* The clock divider is based off the hrawclk,
234 * and would like to run at 2MHz. So, take the
235 * hrawclk value and divide by 2 and use that
236 * On CDV platform it uses 200MHz as hrawclk.
237 *
238 */
239 aux_clock_divider = 200 / 2;
240
241 precharge = 4;
242
243 if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
244 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
245 REG_READ(ch_ctl));
246 return -EBUSY;
247 }
248
249 /* Must try at least 3 times according to DP spec */
250 for (try = 0; try < 5; try++) {
251 /* Load the send data into the aux channel data registers */
252 for (i = 0; i < send_bytes; i += 4)
253 REG_WRITE(ch_data + i,
254 pack_aux(send + i, send_bytes - i));
255
256 /* Send the command and wait for it to complete */
257 REG_WRITE(ch_ctl,
258 DP_AUX_CH_CTL_SEND_BUSY |
259 DP_AUX_CH_CTL_TIME_OUT_400us |
260 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
261 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
262 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
263 DP_AUX_CH_CTL_DONE |
264 DP_AUX_CH_CTL_TIME_OUT_ERROR |
265 DP_AUX_CH_CTL_RECEIVE_ERROR);
266 for (;;) {
267 status = REG_READ(ch_ctl);
268 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
269 break;
270 udelay(100);
271 }
272
273 /* Clear done status and any errors */
274 REG_WRITE(ch_ctl,
275 status |
276 DP_AUX_CH_CTL_DONE |
277 DP_AUX_CH_CTL_TIME_OUT_ERROR |
278 DP_AUX_CH_CTL_RECEIVE_ERROR);
279 if (status & DP_AUX_CH_CTL_DONE)
280 break;
281 }
282
283 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
284 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
285 return -EBUSY;
286 }
287
288 /* Check for timeout or receive error.
289 * Timeouts occur when the sink is not connected
290 */
291 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
292 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
293 return -EIO;
294 }
295
296 /* Timeouts occur when the device isn't connected, so they're
297 * "normal" -- don't fill the kernel log with these */
298 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
299 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
300 return -ETIMEDOUT;
301 }
302
303 /* Unload any bytes sent back from the other side */
304 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
305 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
306 if (recv_bytes > recv_size)
307 recv_bytes = recv_size;
308
309 for (i = 0; i < recv_bytes; i += 4)
310 unpack_aux(REG_READ(ch_data + i),
311 recv + i, recv_bytes - i);
312
313 return recv_bytes;
314}
315
316/* Write data to the aux channel in native mode */
317static int
318psb_intel_dp_aux_native_write(struct psb_intel_output *output,
319 uint16_t address, uint8_t *send, int send_bytes)
320{
321 int ret;
322 uint8_t msg[20];
323 int msg_bytes;
324 uint8_t ack;
325
326 if (send_bytes > 16)
327 return -1;
328 msg[0] = AUX_NATIVE_WRITE << 4;
329 msg[1] = address >> 8;
330 msg[2] = address & 0xff;
331 msg[3] = send_bytes - 1;
332 memcpy(&msg[4], send, send_bytes);
333 msg_bytes = send_bytes + 4;
334 for (;;) {
335 ret = psb_intel_dp_aux_ch(output, msg, msg_bytes, &ack, 1);
336 if (ret < 0)
337 return ret;
338 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
339 break;
340 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
341 udelay(100);
342 else
343 return -EIO;
344 }
345 return send_bytes;
346}
347
348/* Write a single byte to the aux channel in native mode */
349static int
350psb_intel_dp_aux_native_write_1(struct psb_intel_output *output,
351 uint16_t address, uint8_t byte)
352{
353 return psb_intel_dp_aux_native_write(output, address, &byte, 1);
354}
355
356/* read bytes from a native aux channel */
357static int
358psb_intel_dp_aux_native_read(struct psb_intel_output *output,
359 uint16_t address, uint8_t *recv, int recv_bytes)
360{
361 uint8_t msg[4];
362 int msg_bytes;
363 uint8_t reply[20];
364 int reply_bytes;
365 uint8_t ack;
366 int ret;
367
368 msg[0] = AUX_NATIVE_READ << 4;
369 msg[1] = address >> 8;
370 msg[2] = address & 0xff;
371 msg[3] = recv_bytes - 1;
372
373 msg_bytes = 4;
374 reply_bytes = recv_bytes + 1;
375
376 for (;;) {
377 ret = psb_intel_dp_aux_ch(output, msg, msg_bytes,
378 reply, reply_bytes);
379 if (ret == 0)
380 return -EPROTO;
381 if (ret < 0)
382 return ret;
383 ack = reply[0];
384 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
385 memcpy(recv, reply + 1, ret - 1);
386 return ret - 1;
387 }
388 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
389 udelay(100);
390 else
391 return -EIO;
392 }
393}
394
395static int
396psb_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
397 uint8_t write_byte, uint8_t *read_byte)
398{
399 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
400 struct psb_intel_dp *intel_dp = container_of(adapter,
401 struct psb_intel_dp,
402 adapter);
403 struct psb_intel_output *output = intel_dp->output;
404 uint16_t address = algo_data->address;
405 uint8_t msg[5];
406 uint8_t reply[2];
407 unsigned retry;
408 int msg_bytes;
409 int reply_bytes;
410 int ret;
411
412 /* Set up the command byte */
413 if (mode & MODE_I2C_READ)
414 msg[0] = AUX_I2C_READ << 4;
415 else
416 msg[0] = AUX_I2C_WRITE << 4;
417
418 if (!(mode & MODE_I2C_STOP))
419 msg[0] |= AUX_I2C_MOT << 4;
420
421 msg[1] = address >> 8;
422 msg[2] = address;
423
424 switch (mode) {
425 case MODE_I2C_WRITE:
426 msg[3] = 0;
427 msg[4] = write_byte;
428 msg_bytes = 5;
429 reply_bytes = 1;
430 break;
431 case MODE_I2C_READ:
432 msg[3] = 0;
433 msg_bytes = 4;
434 reply_bytes = 2;
435 break;
436 default:
437 msg_bytes = 3;
438 reply_bytes = 1;
439 break;
440 }
441
442 for (retry = 0; retry < 5; retry++) {
443 ret = psb_intel_dp_aux_ch(output,
444 msg, msg_bytes,
445 reply, reply_bytes);
446 if (ret < 0) {
447 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
448 return ret;
449 }
450
451 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
452 case AUX_NATIVE_REPLY_ACK:
453 /* I2C-over-AUX Reply field is only valid
454 * when paired with AUX ACK.
455 */
456 break;
457 case AUX_NATIVE_REPLY_NACK:
458 DRM_DEBUG_KMS("aux_ch native nack\n");
459 return -EREMOTEIO;
460 case AUX_NATIVE_REPLY_DEFER:
461 udelay(100);
462 continue;
463 default:
464 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
465 reply[0]);
466 return -EREMOTEIO;
467 }
468
469 switch (reply[0] & AUX_I2C_REPLY_MASK) {
470 case AUX_I2C_REPLY_ACK:
471 if (mode == MODE_I2C_READ) {
472 *read_byte = reply[1];
473 }
474 return reply_bytes - 1;
475 case AUX_I2C_REPLY_NACK:
476 DRM_DEBUG_KMS("aux_i2c nack\n");
477 return -EREMOTEIO;
478 case AUX_I2C_REPLY_DEFER:
479 DRM_DEBUG_KMS("aux_i2c defer\n");
480 udelay(100);
481 break;
482 default:
483 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
484 return -EREMOTEIO;
485 }
486 }
487
488 DRM_ERROR("too many retries, giving up\n");
489 return -EREMOTEIO;
490}
491
492static int
493psb_intel_dp_i2c_init(struct psb_intel_output *output, const char *name)
494{
495 struct psb_intel_dp *intel_dp = output->dev_priv;
496 DRM_DEBUG_KMS("i2c_init %s\n", name);
497 intel_dp->algo.running = false;
498 intel_dp->algo.address = 0;
499 intel_dp->algo.aux_ch = psb_intel_dp_i2c_aux_ch;
500
501 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
502 intel_dp->adapter.owner = THIS_MODULE;
503 intel_dp->adapter.class = I2C_CLASS_DDC;
504 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
505 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
506 intel_dp->adapter.algo_data = &intel_dp->algo;
507 intel_dp->adapter.dev.parent = &output->base.kdev;
508
509 return i2c_dp_aux_add_bus(&intel_dp->adapter);
510}
511
512static bool
513psb_intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
514 struct drm_display_mode *adjusted_mode)
515{
516 struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
517 struct psb_intel_dp *intel_dp = output->dev_priv;
518 int lane_count, clock;
519 int max_lane_count = psb_intel_dp_max_lane_count(output);
520 int max_clock = psb_intel_dp_max_link_bw(output) == DP_LINK_BW_2_7 ? 1 : 0;
521 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
522
523
524 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
525 for (clock = max_clock; clock >= 0; clock--) {
526 int link_avail = psb_intel_dp_max_data_rate(psb_intel_dp_link_clock(bws[clock]), lane_count);
527
528 if (psb_intel_dp_link_required(mode->clock, 24)
529 <= link_avail) {
530 intel_dp->link_bw = bws[clock];
531 intel_dp->lane_count = lane_count;
532 adjusted_mode->clock = psb_intel_dp_link_clock(intel_dp->link_bw);
533 DRM_DEBUG_KMS("Display port link bw %02x lane "
534 "count %d clock %d\n",
535 intel_dp->link_bw, intel_dp->lane_count,
536 adjusted_mode->clock);
537 return true;
538 }
539 }
540 }
541
542 return false;
543}
544
545struct psb_intel_dp_m_n {
546 uint32_t tu;
547 uint32_t gmch_m;
548 uint32_t gmch_n;
549 uint32_t link_m;
550 uint32_t link_n;
551};
552
553static void
554psb_intel_reduce_ratio(uint32_t *num, uint32_t *den)
555{
556 /*
557 while (*num > 0xffffff || *den > 0xffffff) {
558 *num >>= 1;
559 *den >>= 1;
560 }*/
561 uint64_t value, m;
562 m = *num;
563 value = m * (0x800000);
564 m = do_div(value, *den);
565 *num = value;
566 *den = 0x800000;
567}
568
569static void
570psb_intel_dp_compute_m_n(int bpp,
571 int nlanes,
572 int pixel_clock,
573 int link_clock,
574 struct psb_intel_dp_m_n *m_n)
575{
576 m_n->tu = 64;
577 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3;
578 m_n->gmch_n = link_clock * nlanes;
579 psb_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
580 m_n->link_m = pixel_clock;
581 m_n->link_n = link_clock;
582 psb_intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
583}
584
585void
586psb_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
587 struct drm_display_mode *adjusted_mode)
588{
589 struct drm_device *dev = crtc->dev;
590 struct drm_mode_config *mode_config = &dev->mode_config;
591 struct drm_encoder *encoder;
592 struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
593 int lane_count = 4, bpp = 24;
594 struct psb_intel_dp_m_n m_n;
595 int pipe = intel_crtc->pipe;
596
597 /*
598 * Find the lane count in the intel_encoder private
599 */
600 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
601 struct psb_intel_output *intel_output;
602 struct psb_intel_dp *intel_dp;
603
604 if (encoder->crtc != crtc)
605 continue;
606
607 intel_output = enc_to_psb_intel_output(encoder);
608 intel_dp = intel_output->dev_priv;
609 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
610 lane_count = intel_dp->lane_count;
611 break;
612 } else if (is_edp(intel_output)) {
613 lane_count = intel_dp->lane_count;
614 break;
615 }
616 }
617
618 /*
619 * Compute the GMCH and Link ratios. The '3' here is
620 * the number of bytes_per_pixel post-LUT, which we always
621 * set up for 8-bits of R/G/B, or 3 bytes total.
622 */
623 psb_intel_dp_compute_m_n(bpp, lane_count,
624 mode->clock, adjusted_mode->clock, &m_n);
625
626 {
627 REG_WRITE(PIPE_GMCH_DATA_M(pipe),
628 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
629 m_n.gmch_m);
630 REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
631 REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
632 REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
633 }
634}
635
636static void
637psb_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
638 struct drm_display_mode *adjusted_mode)
639{
640 struct psb_intel_output *intel_output = enc_to_psb_intel_output(encoder);
641 struct drm_crtc *crtc = encoder->crtc;
642 struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
643 struct psb_intel_dp *intel_dp = intel_output->dev_priv;
644
645
646 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
647 intel_dp->DP |= intel_dp->color_range;
648
649 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
650 intel_dp->DP |= DP_SYNC_HS_HIGH;
651 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
652 intel_dp->DP |= DP_SYNC_VS_HIGH;
653
654 intel_dp->DP |= DP_LINK_TRAIN_OFF;
655
656 switch (intel_dp->lane_count) {
657 case 1:
658 intel_dp->DP |= DP_PORT_WIDTH_1;
659 break;
660 case 2:
661 intel_dp->DP |= DP_PORT_WIDTH_2;
662 break;
663 case 4:
664 intel_dp->DP |= DP_PORT_WIDTH_4;
665 break;
666 }
667 if (intel_dp->has_audio)
668 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
669
670 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
671 intel_dp->link_configuration[0] = intel_dp->link_bw;
672 intel_dp->link_configuration[1] = intel_dp->lane_count;
673
674 /*
675 * Check for DPCD version > 1.1 and enhanced framing support
676 */
677 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
678 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
679 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
680 intel_dp->DP |= DP_ENHANCED_FRAMING;
681 }
682
683 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
684 if (intel_crtc->pipe == 1)
685 intel_dp->DP |= DP_PIPEB_SELECT;
686
687 DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);
688}
689
690
691/* If the sink supports it, try to set the power state appropriately */
692static void psb_intel_dp_sink_dpms(struct psb_intel_output *output, int mode)
693{
694 struct psb_intel_dp *intel_dp = output->dev_priv;
695 int ret, i;
696
697 /* Should have a valid DPCD by this point */
698 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
699 return;
700
701 if (mode != DRM_MODE_DPMS_ON) {
702 ret = psb_intel_dp_aux_native_write_1(output, DP_SET_POWER,
703 DP_SET_POWER_D3);
704 if (ret != 1)
705 DRM_DEBUG_DRIVER("failed to write sink power state\n");
706 } else {
707 /*
708 * When turning on, we need to retry for 1ms to give the sink
709 * time to wake up.
710 */
711 for (i = 0; i < 3; i++) {
712 ret = psb_intel_dp_aux_native_write_1(output,
713 DP_SET_POWER,
714 DP_SET_POWER_D0);
715 if (ret == 1)
716 break;
717 udelay(1000);
718 }
719 }
720}
721
722static void psb_intel_dp_prepare(struct drm_encoder *encoder)
723{
724 struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
725
726 /* Wake up the sink first */
727 psb_intel_dp_sink_dpms(output, DRM_MODE_DPMS_ON);
728
729 psb_intel_dp_link_down(output);
730}
731
732static void psb_intel_dp_commit(struct drm_encoder *encoder)
733{
734 struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
735
736 psb_intel_dp_start_link_train(output);
737
738 psb_intel_dp_complete_link_train(output);
739
740}
741
742static void
743psb_intel_dp_dpms(struct drm_encoder *encoder, int mode)
744{
745 struct psb_intel_output *intel_output = enc_to_psb_intel_output(encoder);
746 struct psb_intel_dp *intel_dp = intel_output->dev_priv;
747 struct drm_device *dev = encoder->dev;
748 uint32_t dp_reg = REG_READ(intel_dp->output_reg);
749
750 if (mode != DRM_MODE_DPMS_ON) {
751 psb_intel_dp_sink_dpms(intel_output, mode);
752 psb_intel_dp_link_down(intel_output);
753 } else {
754 psb_intel_dp_sink_dpms(intel_output, mode);
755 if (!(dp_reg & DP_PORT_EN)) {
756 psb_intel_dp_start_link_train(intel_output);
757 psb_intel_dp_complete_link_train(intel_output);
758 }
759 }
760}
761
762/*
763 * Native read with retry for link status and receiver capability reads for
764 * cases where the sink may still be asleep.
765 */
766static bool
767psb_intel_dp_aux_native_read_retry(struct psb_intel_output *output, uint16_t address,
768 uint8_t *recv, int recv_bytes)
769{
770 int ret, i;
771
772 /*
773 * Sinks are *supposed* to come up within 1ms from an off state,
774 * but we're also supposed to retry 3 times per the spec.
775 */
776 for (i = 0; i < 3; i++) {
777 ret = psb_intel_dp_aux_native_read(output, address, recv,
778 recv_bytes);
779 if (ret == recv_bytes)
780 return true;
781 udelay(1000);
782 }
783
784 return false;
785}
786
787/*
788 * Fetch AUX CH registers 0x202 - 0x207 which contain
789 * link status information
790 */
791static bool
792psb_intel_dp_get_link_status(struct psb_intel_output *output)
793{
794 struct psb_intel_dp *intel_dp = output->dev_priv;
795 return psb_intel_dp_aux_native_read_retry(output,
796 DP_LANE0_1_STATUS,
797 intel_dp->link_status,
798 DP_LINK_STATUS_SIZE);
799}
800
801static uint8_t
802psb_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
803 int r)
804{
805 return link_status[r - DP_LANE0_1_STATUS];
806}
807
808static uint8_t
809psb_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
810 int lane)
811{
812 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
813 int s = ((lane & 1) ?
814 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
815 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
816 uint8_t l = psb_intel_dp_link_status(link_status, i);
817
818 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
819}
820
821static uint8_t
822psb_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
823 int lane)
824{
825 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
826 int s = ((lane & 1) ?
827 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
828 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
829 uint8_t l = psb_intel_dp_link_status(link_status, i);
830
831 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
832}
833
834
835#if 0
836static char *voltage_names[] = {
837 "0.4V", "0.6V", "0.8V", "1.2V"
838};
839static char *pre_emph_names[] = {
840 "0dB", "3.5dB", "6dB", "9.5dB"
841};
842static char *link_train_names[] = {
843 "pattern 1", "pattern 2", "idle", "off"
844};
845#endif
846
847#define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
848/*
849static uint8_t
850psb_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
851{
852 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
853 case DP_TRAIN_VOLTAGE_SWING_400:
854 return DP_TRAIN_PRE_EMPHASIS_6;
855 case DP_TRAIN_VOLTAGE_SWING_600:
856 return DP_TRAIN_PRE_EMPHASIS_6;
857 case DP_TRAIN_VOLTAGE_SWING_800:
858 return DP_TRAIN_PRE_EMPHASIS_3_5;
859 case DP_TRAIN_VOLTAGE_SWING_1200:
860 default:
861 return DP_TRAIN_PRE_EMPHASIS_0;
862 }
863}
864*/
865static void
866psb_intel_get_adjust_train(struct psb_intel_output *output)
867{
868 struct psb_intel_dp *intel_dp = output->dev_priv;
869 uint8_t v = 0;
870 uint8_t p = 0;
871 int lane;
872
873 for (lane = 0; lane < intel_dp->lane_count; lane++) {
874 uint8_t this_v = psb_intel_get_adjust_request_voltage(intel_dp->link_status, lane);
875 uint8_t this_p = psb_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
876
877 if (this_v > v)
878 v = this_v;
879 if (this_p > p)
880 p = this_p;
881 }
882
883 if (v >= CDV_DP_VOLTAGE_MAX)
884 v = CDV_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
885
886 if (p == DP_TRAIN_PRE_EMPHASIS_MASK)
887 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
888
889 for (lane = 0; lane < 4; lane++)
890 intel_dp->train_set[lane] = v | p;
891}
892
893
894static uint8_t
895psb_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
896 int lane)
897{
898 int i = DP_LANE0_1_STATUS + (lane >> 1);
899 int s = (lane & 1) * 4;
900 uint8_t l = psb_intel_dp_link_status(link_status, i);
901
902 return (l >> s) & 0xf;
903}
904
905/* Check for clock recovery is done on all channels */
906static bool
907psb_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
908{
909 int lane;
910 uint8_t lane_status;
911
912 for (lane = 0; lane < lane_count; lane++) {
913 lane_status = psb_intel_get_lane_status(link_status, lane);
914 if ((lane_status & DP_LANE_CR_DONE) == 0)
915 return false;
916 }
917 return true;
918}
919
920/* Check to see if channel eq is done on all channels */
921#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
922 DP_LANE_CHANNEL_EQ_DONE|\
923 DP_LANE_SYMBOL_LOCKED)
924static bool
925psb_intel_channel_eq_ok(struct psb_intel_output *output)
926{
927 struct psb_intel_dp *intel_dp = output->dev_priv;
928 uint8_t lane_align;
929 uint8_t lane_status;
930 int lane;
931
932 lane_align = psb_intel_dp_link_status(intel_dp->link_status,
933 DP_LANE_ALIGN_STATUS_UPDATED);
934 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
935 return false;
936 for (lane = 0; lane < intel_dp->lane_count; lane++) {
937 lane_status = psb_intel_get_lane_status(intel_dp->link_status, lane);
938 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
939 return false;
940 }
941 return true;
942}
943
944static bool
945psb_intel_dp_set_link_train(struct psb_intel_output *output,
946 uint32_t dp_reg_value,
947 uint8_t dp_train_pat)
948{
949
950 struct drm_device *dev = output->base.dev;
951 int ret;
952 struct psb_intel_dp *intel_dp = output->dev_priv;
953
954 REG_WRITE(intel_dp->output_reg, dp_reg_value);
955 REG_READ(intel_dp->output_reg);
956
957 ret = psb_intel_dp_aux_native_write_1(output,
958 DP_TRAINING_PATTERN_SET,
959 dp_train_pat);
960
961 if (ret != 1) {
962 DRM_DEBUG_KMS("Failure in setting link pattern %x\n",
963 dp_train_pat);
964 return false;
965 }
966
967 return true;
968}
969
970
971static bool
972psb_intel_dplink_set_level(struct psb_intel_output *output,
973 uint8_t dp_train_pat)
974{
975
976 int ret;
977 struct psb_intel_dp *intel_dp = output->dev_priv;
978
979 ret = psb_intel_dp_aux_native_write(output,
980 DP_TRAINING_LANE0_SET,
981 intel_dp->train_set,
982 intel_dp->lane_count);
983
984 if (ret != intel_dp->lane_count) {
985 DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d\n",
986 intel_dp->train_set[0], intel_dp->lane_count);
987 return false;
988 }
989 return true;
990}
991
992static void
993psb_intel_dp_set_vswing_premph(struct psb_intel_output *output, uint8_t signal_level)
994{
995 struct drm_device *dev = output->base.dev;
996 struct psb_intel_dp *intel_dp = output->dev_priv;
997 struct ddi_regoff *ddi_reg;
998 int vswing, premph, index;
999
1000 if (intel_dp->output_reg == DP_B)
1001 ddi_reg = &ddi_DP_train_table[0];
1002 else
1003 ddi_reg = &ddi_DP_train_table[1];
1004
1005 vswing = (signal_level & DP_TRAIN_VOLTAGE_SWING_MASK);
1006 premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >>
1007 DP_TRAIN_PRE_EMPHASIS_SHIFT;
1008
1009 if (vswing + premph > 3)
1010 return;
1011#ifdef CDV_FAST_LINK_TRAIN
1012 return;
1013#endif
1014 DRM_DEBUG_KMS("Test2\n");
1015 //return ;
1016 psb_sb_reset(dev);
1017 /* ;Swing voltage programming
1018 ;gfx_dpio_set_reg(0xc058, 0x0505313A) */
1019 psb_sb_write(dev, ddi_reg->VSwing5, 0x0505313A);
1020
1021 /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */
1022 psb_sb_write(dev, ddi_reg->VSwing1, 0x43406055);
1023
1024 /* ;gfx_dpio_set_reg(0x8148, 0x55338954)
1025 * The VSwing_PreEmph table is also considered based on the vswing/premp
1026 */
1027 index = (vswing + premph) * 2;
1028 if (premph == 1 && vswing == 1) {
1029 psb_sb_write(dev, ddi_reg->VSwing2, 0x055738954);
1030 } else
1031 psb_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
1032
1033 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
1034 if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200)
1035 psb_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
1036 else
1037 psb_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
1038
1039 /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */
1040 //psb_sb_write(dev, ddi_reg->VSwing4, 0x2b405555);
1041
1042 /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */
1043 psb_sb_write(dev, ddi_reg->VSwing1, 0xc3406055);
1044
1045 /* ;Pre emphasis programming
1046 * ;gfx_dpio_set_reg(0xc02c, 0x1f030040)
1047 */
1048 psb_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040);
1049
1050 /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */
1051 index = 2 * premph + 1;
1052 psb_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]);
1053 return;
1054}
1055
1056
1057/* Enable corresponding port and start training pattern 1 */
1058static void
1059psb_intel_dp_start_link_train(struct psb_intel_output *output)
1060{
1061 struct drm_device *dev = output->base.dev;
1062 struct psb_intel_dp *intel_dp = output->dev_priv;
1063 int i;
1064 uint8_t voltage;
1065 bool clock_recovery = false;
1066 int tries;
1067 u32 reg;
1068 uint32_t DP = intel_dp->DP;
1069
1070 DP |= DP_PORT_EN;
1071 DP &= ~DP_LINK_TRAIN_MASK;
1072
1073 reg = DP;
1074 reg |= DP_LINK_TRAIN_PAT_1;
1075 /* Enable output, wait for it to become active */
1076 REG_WRITE(intel_dp->output_reg, reg);
1077 REG_READ(intel_dp->output_reg);
1078 psb_intel_wait_for_vblank(dev);
1079
1080 DRM_DEBUG_KMS("Link config\n");
1081 /* Write the link configuration data */
1082 psb_intel_dp_aux_native_write(output, DP_LINK_BW_SET,
1083 intel_dp->link_configuration,
1084 2);
1085
1086 memset(intel_dp->train_set, 0, 4);
1087 voltage = 0;
1088 tries = 0;
1089 clock_recovery = false;
1090
1091 DRM_DEBUG_KMS("Start train\n");
1092 reg = DP | DP_LINK_TRAIN_PAT_1;
1093
1094
1095 for (;;) {
1096 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1097
1098 if (!psb_intel_dp_set_link_train(output, reg, DP_TRAINING_PATTERN_1)) {
1099 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n");
1100 }
1101 psb_intel_dp_set_vswing_premph(output, intel_dp->train_set[0]);
1102 /* Set training pattern 1 */
1103
1104 psb_intel_dplink_set_level(output, DP_TRAINING_PATTERN_1);
1105
1106 udelay(200);
1107 if (!psb_intel_dp_get_link_status(output))
1108 break;
1109
1110 if (psb_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1111 DRM_DEBUG_KMS("PT1 train is done\n");
1112 clock_recovery = true;
1113 break;
1114 }
1115
1116 /* Check to see if we've tried the max voltage */
1117 for (i = 0; i < intel_dp->lane_count; i++)
1118 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1119 break;
1120 if (i == intel_dp->lane_count)
1121 break;
1122
1123 /* Check to see if we've tried the same voltage 5 times */
1124 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1125 ++tries;
1126 if (tries == 5)
1127 break;
1128 } else
1129 tries = 0;
1130 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1131
1132 /* Compute new intel_dp->train_set as requested by target */
1133 psb_intel_get_adjust_train(output);
1134
1135 }
1136
1137 if (!clock_recovery) {
1138 DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]);
1139 }
1140
1141 intel_dp->DP = DP;
1142}
1143
1144static void
1145psb_intel_dp_complete_link_train(struct psb_intel_output *output)
1146{
1147 struct drm_device *dev = output->base.dev;
1148 struct psb_intel_dp *intel_dp = output->dev_priv;
1149 bool channel_eq = false;
1150 int tries, cr_tries;
1151 u32 reg;
1152 uint32_t DP = intel_dp->DP;
1153
1154 /* channel equalization */
1155 tries = 0;
1156 cr_tries = 0;
1157 channel_eq = false;
1158
1159 DRM_DEBUG_KMS("\n");
1160 reg = DP | DP_LINK_TRAIN_PAT_2;
1161
1162 for (;;) {
1163 /* channel eq pattern */
1164 if (!psb_intel_dp_set_link_train(output, reg,
1165 DP_TRAINING_PATTERN_2)) {
1166 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n");
1167 }
1168 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1169
1170 if (cr_tries > 5) {
1171 DRM_ERROR("failed to train DP, aborting\n");
1172 psb_intel_dp_link_down(output);
1173 break;
1174 }
1175
1176 psb_intel_dp_set_vswing_premph(output, intel_dp->train_set[0]);
1177
1178 psb_intel_dplink_set_level(output, DP_TRAINING_PATTERN_2);
1179
1180 udelay(1000);
1181 if (!psb_intel_dp_get_link_status(output))
1182 break;
1183
1184 /* Make sure clock is still ok */
1185 if (!psb_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1186 psb_intel_dp_start_link_train(output);
1187 cr_tries++;
1188 continue;
1189 }
1190
1191 if (psb_intel_channel_eq_ok(output)) {
1192 DRM_DEBUG_KMS("PT2 train is done\n");
1193 channel_eq = true;
1194 break;
1195 }
1196
1197 /* Try 5 times, then try clock recovery if that fails */
1198 if (tries > 5) {
1199 psb_intel_dp_link_down(output);
1200 psb_intel_dp_start_link_train(output);
1201 tries = 0;
1202 cr_tries++;
1203 continue;
1204 }
1205
1206 /* Compute new intel_dp->train_set as requested by target */
1207 psb_intel_get_adjust_train(output);
1208 ++tries;
1209
1210 }
1211
1212 reg = DP | DP_LINK_TRAIN_OFF;
1213
1214 REG_WRITE(intel_dp->output_reg, reg);
1215 REG_READ(intel_dp->output_reg);
1216 psb_intel_dp_aux_native_write_1(output,
1217 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1218}
1219
1220static void
1221psb_intel_dp_link_down(struct psb_intel_output *output)
1222{
1223 struct drm_device *dev = output->base.dev;
1224 struct psb_intel_dp *intel_dp = output->dev_priv;
1225 uint32_t DP = intel_dp->DP;
1226
1227 if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1228 return;
1229
1230 DRM_DEBUG_KMS("\n");
1231
1232
1233 {
1234 DP &= ~DP_LINK_TRAIN_MASK;
1235 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1236 }
1237 REG_READ(intel_dp->output_reg);
1238
1239 msleep(17);
1240
1241 REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1242 REG_READ(intel_dp->output_reg);
1243}
1244
1245static enum drm_connector_status
1246cdv_dp_detect(struct psb_intel_output *output)
1247{
1248 struct psb_intel_dp *intel_dp = output->dev_priv;
1249 enum drm_connector_status status;
1250
1251 status = connector_status_disconnected;
1252 if (psb_intel_dp_aux_native_read(output, 0x000, intel_dp->dpcd,
1253 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1254 {
1255 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1256 status = connector_status_connected;
1257 }
1258 if (status == connector_status_connected)
1259 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
1260 intel_dp->dpcd[0], intel_dp->dpcd[1],
1261 intel_dp->dpcd[2], intel_dp->dpcd[3]);
1262 return status;
1263}
1264
1265/**
1266 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1267 *
1268 * \return true if DP port is connected.
1269 * \return false if DP port is disconnected.
1270 */
1271static enum drm_connector_status
1272psb_intel_dp_detect(struct drm_connector *connector, bool force)
1273{
1274 struct psb_intel_output *output = to_psb_intel_output(connector);
1275 struct psb_intel_dp *intel_dp = output->dev_priv;
1276 enum drm_connector_status status;
1277 struct edid *edid = NULL;
1278
1279 intel_dp->has_audio = false;
1280
1281 status = cdv_dp_detect(output);
1282 if (status != connector_status_connected)
1283 return status;
1284
1285 if (intel_dp->force_audio) {
1286 intel_dp->has_audio = intel_dp->force_audio > 0;
1287 } else {
1288 edid = drm_get_edid(connector, &intel_dp->adapter);
1289 if (edid) {
1290 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1291 connector->display_info.raw_edid = NULL;
1292 kfree(edid);
1293 }
1294 }
1295
1296 return connector_status_connected;
1297}
1298
1299static int psb_intel_dp_get_modes(struct drm_connector *connector)
1300{
1301 struct psb_intel_output *intel_output = to_psb_intel_output(connector);
1302 struct psb_intel_dp *intel_dp = intel_output->dev_priv;
1303 struct edid *edid = NULL;
1304 int ret = 0;
1305
1306
1307 edid = drm_get_edid(&intel_output->base,
1308 &intel_dp->adapter);
1309 if (edid) {
1310 drm_mode_connector_update_edid_property(&intel_output->
1311 base, edid);
1312 ret = drm_add_edid_modes(&intel_output->base, edid);
1313 kfree(edid);
1314 }
1315
1316 return ret;
1317}
1318
1319static bool
1320psb_intel_dp_detect_audio(struct drm_connector *connector)
1321{
1322 struct psb_intel_output *output = to_psb_intel_output(connector);
1323 struct psb_intel_dp *intel_dp = output->dev_priv;
1324 struct edid *edid;
1325 bool has_audio = false;
1326
1327 edid = drm_get_edid(connector, &intel_dp->adapter);
1328 if (edid) {
1329 has_audio = drm_detect_monitor_audio(edid);
1330
1331 connector->display_info.raw_edid = NULL;
1332 kfree(edid);
1333 }
1334
1335 return has_audio;
1336}
1337
1338static int
1339psb_intel_dp_set_property(struct drm_connector *connector,
1340 struct drm_property *property,
1341 uint64_t val)
1342{
1343 struct drm_psb_private *dev_priv = connector->dev->dev_private;
1344 struct psb_intel_output *output = to_psb_intel_output(connector);
1345 struct psb_intel_dp *intel_dp = output->dev_priv;
1346 int ret;
1347
1348 ret = drm_connector_property_set_value(connector, property, val);
1349 if (ret)
1350 return ret;
1351
1352 if (property == dev_priv->force_audio_property) {
1353 int i = val;
1354 bool has_audio;
1355
1356 if (i == intel_dp->force_audio)
1357 return 0;
1358
1359 intel_dp->force_audio = i;
1360
1361 if (i == 0)
1362 has_audio = psb_intel_dp_detect_audio(connector);
1363 else
1364 has_audio = i > 0;
1365
1366 if (has_audio == intel_dp->has_audio)
1367 return 0;
1368
1369 intel_dp->has_audio = has_audio;
1370 goto done;
1371 }
1372
1373 if (property == dev_priv->broadcast_rgb_property) {
1374 if (val == !!intel_dp->color_range)
1375 return 0;
1376
1377 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1378 goto done;
1379 }
1380
1381 return -EINVAL;
1382
1383done:
1384 if (output->enc.crtc) {
1385 struct drm_crtc *crtc = output->enc.crtc;
1386 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1387 crtc->x, crtc->y,
1388 crtc->fb);
1389 }
1390
1391 return 0;
1392}
1393
1394static void
1395psb_intel_dp_destroy (struct drm_connector *connector)
1396{
1397 struct psb_intel_output *output = to_psb_intel_output(connector);
1398 struct psb_intel_dp *intel_dp = output->dev_priv;
1399
1400 i2c_del_adapter(&intel_dp->adapter);
1401 drm_sysfs_connector_remove(connector);
1402 drm_connector_cleanup(connector);
1403 kfree(connector);
1404}
1405
1406static void psb_intel_dp_encoder_destroy(struct drm_encoder *encoder)
1407{
1408 drm_encoder_cleanup(encoder);
1409}
1410
1411static const struct drm_encoder_helper_funcs psb_intel_dp_helper_funcs = {
1412 .dpms = psb_intel_dp_dpms,
1413 .mode_fixup = psb_intel_dp_mode_fixup,
1414 .prepare = psb_intel_dp_prepare,
1415 .mode_set = psb_intel_dp_mode_set,
1416 .commit = psb_intel_dp_commit,
1417};
1418
1419static const struct drm_connector_funcs psb_intel_dp_connector_funcs = {
1420 .dpms = drm_helper_connector_dpms,
1421 .detect = psb_intel_dp_detect,
1422 .fill_modes = drm_helper_probe_single_connector_modes,
1423 .set_property = psb_intel_dp_set_property,
1424 .destroy = psb_intel_dp_destroy,
1425};
1426
1427static const struct drm_connector_helper_funcs psb_intel_dp_connector_helper_funcs = {
1428 .get_modes = psb_intel_dp_get_modes,
1429 .mode_valid = psb_intel_dp_mode_valid,
1430 .best_encoder = psb_intel_best_encoder,
1431};
1432
1433static const struct drm_encoder_funcs psb_intel_dp_enc_funcs = {
1434 .destroy = psb_intel_dp_encoder_destroy,
1435};
1436
1437
1438static void
1439psb_intel_dp_add_properties(struct psb_intel_output *output, struct drm_connector *connector)
1440{
1441 psb_intel_attach_force_audio_property(connector);
1442 psb_intel_attach_broadcast_rgb_property(connector);
1443}
1444
1445void
1446psb_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
1447{
1448 struct drm_connector *connector;
1449 struct drm_encoder *encoder;
1450 struct psb_intel_output *psb_intel_output;
1451 struct psb_intel_dp *intel_dp;
1452 const char *name = NULL;
1453 int type;
1454
1455 psb_intel_output = kzalloc(sizeof(struct psb_intel_output) +
1456 sizeof(struct psb_intel_dp), GFP_KERNEL);
1457 if (!psb_intel_output)
1458 return;
1459
1460 intel_dp = (struct psb_intel_dp *)(psb_intel_output + 1);
1461 psb_intel_output->mode_dev = mode_dev;
1462 connector = &psb_intel_output->base;
1463 encoder = &psb_intel_output->enc;
1464 psb_intel_output->dev_priv=intel_dp;
1465 intel_dp->output = psb_intel_output;
1466
1467 intel_dp->output_reg = output_reg;
1468
1469 type = DRM_MODE_CONNECTOR_DisplayPort;
1470 psb_intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
1471
1472 drm_connector_init(dev, connector, &psb_intel_dp_connector_funcs, type);
1473 drm_connector_helper_add(connector, &psb_intel_dp_connector_helper_funcs);
1474
1475 connector->polled = DRM_CONNECTOR_POLL_HPD;
1476
1477 connector->interlace_allowed = 0;
1478 connector->doublescan_allowed = 0;
1479
1480 drm_encoder_init(dev, encoder, &psb_intel_dp_enc_funcs,
1481 DRM_MODE_ENCODER_TMDS);
1482 drm_encoder_helper_add(encoder, &psb_intel_dp_helper_funcs);
1483
1484 drm_mode_connector_attach_encoder(&psb_intel_output->base,
1485 &psb_intel_output->enc);
1486
1487 drm_sysfs_connector_add(connector);
1488
1489 /* Set up the DDC bus. */
1490 switch (output_reg) {
1491 case DP_B:
1492 name = "DPDDC-B";
1493 psb_intel_output->ddi_select = (DP_MASK | DDI0_SELECT);
1494 break;
1495 case DP_C:
1496 name = "DPDDC-C";
1497 psb_intel_output->ddi_select = (DP_MASK | DDI1_SELECT);
1498 break;
1499 }
1500
1501 psb_intel_dp_i2c_init(psb_intel_output, name);
1502 psb_intel_dp_add_properties(psb_intel_output, connector);
1503
1504}
diff --git a/drivers/gpu/drm/gma500/psb_intel_drv.h b/drivers/gpu/drm/gma500/psb_intel_drv.h
index 7b357b04d4e2..73214e281fab 100644
--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
+++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
@@ -29,10 +29,6 @@
29 * Display related stuff 29 * Display related stuff
30 */ 30 */
31 31
32/* store information about an Ixxx DVO */
33/* The i830->i865 use multiple DVOs with multiple i2cs */
34/* the i915, i945 have a single sDVO i2c bus - which is different */
35#define MAX_OUTPUTS 6
36/* maximum connectors per crtcs in the mode set */ 32/* maximum connectors per crtcs in the mode set */
37#define INTELFB_CONN_LIMIT 4 33#define INTELFB_CONN_LIMIT 4
38 34
@@ -69,6 +65,8 @@
69#define INTEL_OUTPUT_HDMI 6 65#define INTEL_OUTPUT_HDMI 6
70#define INTEL_OUTPUT_MIPI 7 66#define INTEL_OUTPUT_MIPI 7
71#define INTEL_OUTPUT_MIPI2 8 67#define INTEL_OUTPUT_MIPI2 8
68#define INTEL_OUTPUT_DISPLAYPORT 9
69#define INTEL_OUTPUT_EDP 10
72 70
73#define INTEL_DVO_CHIP_NONE 0 71#define INTEL_DVO_CHIP_NONE 0
74#define INTEL_DVO_CHIP_LVDS 1 72#define INTEL_DVO_CHIP_LVDS 1
diff --git a/drivers/gpu/drm/gma500/psb_intel_reg.h b/drivers/gpu/drm/gma500/psb_intel_reg.h
index 8e8c8efb0a89..d3091fc72b9e 100644
--- a/drivers/gpu/drm/gma500/psb_intel_reg.h
+++ b/drivers/gpu/drm/gma500/psb_intel_reg.h
@@ -1347,5 +1347,160 @@ No status bits are changed.
1347#define LANE_PLL_ENABLE (0x3 << 20) 1347#define LANE_PLL_ENABLE (0x3 << 20)
1348#define LANE_PLL_PIPE(p) (((p) == 0) ? (1 << 21) : (0 << 21)) 1348#define LANE_PLL_PIPE(p) (((p) == 0) ? (1 << 21) : (0 << 21))
1349 1349
1350#define DP_B 0x64100
1351#define DP_C 0x64200
1352
1353#define DP_PORT_EN (1 << 31)
1354#define DP_PIPEB_SELECT (1 << 30)
1355#define DP_PIPE_MASK (1 << 30)
1356
1357/* Link training mode - select a suitable mode for each stage */
1358#define DP_LINK_TRAIN_PAT_1 (0 << 28)
1359#define DP_LINK_TRAIN_PAT_2 (1 << 28)
1360#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1361#define DP_LINK_TRAIN_OFF (3 << 28)
1362#define DP_LINK_TRAIN_MASK (3 << 28)
1363#define DP_LINK_TRAIN_SHIFT 28
1364
1365/* Signal voltages. These are mostly controlled by the other end */
1366#define DP_VOLTAGE_0_4 (0 << 25)
1367#define DP_VOLTAGE_0_6 (1 << 25)
1368#define DP_VOLTAGE_0_8 (2 << 25)
1369#define DP_VOLTAGE_1_2 (3 << 25)
1370#define DP_VOLTAGE_MASK (7 << 25)
1371#define DP_VOLTAGE_SHIFT 25
1372
1373/* Signal pre-emphasis levels, like voltages, the other end tells us what
1374 * they want
1375 */
1376#define DP_PRE_EMPHASIS_0 (0 << 22)
1377#define DP_PRE_EMPHASIS_3_5 (1 << 22)
1378#define DP_PRE_EMPHASIS_6 (2 << 22)
1379#define DP_PRE_EMPHASIS_9_5 (3 << 22)
1380#define DP_PRE_EMPHASIS_MASK (7 << 22)
1381#define DP_PRE_EMPHASIS_SHIFT 22
1382
1383/* How many wires to use. I guess 3 was too hard */
1384#define DP_PORT_WIDTH_1 (0 << 19)
1385#define DP_PORT_WIDTH_2 (1 << 19)
1386#define DP_PORT_WIDTH_4 (3 << 19)
1387#define DP_PORT_WIDTH_MASK (7 << 19)
1388
1389/* Mystic DPCD version 1.1 special mode */
1390#define DP_ENHANCED_FRAMING (1 << 18)
1391
1392/** locked once port is enabled */
1393#define DP_PORT_REVERSAL (1 << 15)
1394
1395/** sends the clock on lane 15 of the PEG for debug */
1396#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1397
1398#define DP_SCRAMBLING_DISABLE (1 << 12)
1399#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
1400
1401/** limit RGB values to avoid confusing TVs */
1402#define DP_COLOR_RANGE_16_235 (1 << 8)
1403
1404/** Turn on the audio link */
1405#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1406
1407/** vs and hs sync polarity */
1408#define DP_SYNC_VS_HIGH (1 << 4)
1409#define DP_SYNC_HS_HIGH (1 << 3)
1410
1411/** A fantasy */
1412#define DP_DETECTED (1 << 2)
1413
1414/** The aux channel provides a way to talk to the
1415 * signal sink for DDC etc. Max packet size supported
1416 * is 20 bytes in each direction, hence the 5 fixed
1417 * data registers
1418 */
1419#define DPB_AUX_CH_CTL 0x64110
1420#define DPB_AUX_CH_DATA1 0x64114
1421#define DPB_AUX_CH_DATA2 0x64118
1422#define DPB_AUX_CH_DATA3 0x6411c
1423#define DPB_AUX_CH_DATA4 0x64120
1424#define DPB_AUX_CH_DATA5 0x64124
1425
1426#define DPC_AUX_CH_CTL 0x64210
1427#define DPC_AUX_CH_DATA1 0x64214
1428#define DPC_AUX_CH_DATA2 0x64218
1429#define DPC_AUX_CH_DATA3 0x6421c
1430#define DPC_AUX_CH_DATA4 0x64220
1431#define DPC_AUX_CH_DATA5 0x64224
1432
1433#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
1434#define DP_AUX_CH_CTL_DONE (1 << 30)
1435#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
1436#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
1437#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
1438#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
1439#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
1440#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
1441#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
1442#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
1443#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
1444#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
1445#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
1446#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
1447#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
1448#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
1449#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
1450#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
1451#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
1452#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1453#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
1454
1455/*
1456 * Computing GMCH M and N values for the Display Port link
1457 *
1458 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1459 *
1460 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1461 *
1462 * The GMCH value is used internally
1463 *
1464 * bytes_per_pixel is the number of bytes coming out of the plane,
1465 * which is after the LUTs, so we want the bytes for our color format.
1466 * For our current usage, this is always 3, one byte for R, G and B.
1467 */
1468
1469#define _PIPEA_GMCH_DATA_M 0x70050
1470#define _PIPEB_GMCH_DATA_M 0x71050
1471
1472/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1473#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
1474#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
1475
1476#define PIPE_GMCH_DATA_M_MASK (0xffffff)
1477
1478#define _PIPEA_GMCH_DATA_N 0x70054
1479#define _PIPEB_GMCH_DATA_N 0x71054
1480#define PIPE_GMCH_DATA_N_MASK (0xffffff)
1481
1482/*
1483 * Computing Link M and N values for the Display Port link
1484 *
1485 * Link M / N = pixel_clock / ls_clk
1486 *
1487 * (the DP spec calls pixel_clock the 'strm_clk')
1488 *
1489 * The Link value is transmitted in the Main Stream
1490 * Attributes and VB-ID.
1491 */
1492
1493#define _PIPEA_DP_LINK_M 0x70060
1494#define _PIPEB_DP_LINK_M 0x71060
1495#define PIPEA_DP_LINK_M_MASK (0xffffff)
1496
1497#define _PIPEA_DP_LINK_N 0x70064
1498#define _PIPEB_DP_LINK_N 0x71064
1499#define PIPEA_DP_LINK_N_MASK (0xffffff)
1500
1501#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
1502#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
1503#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
1504#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
1350 1505
1351#endif 1506#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 00:17:27 -0500