diff options
author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-05-26 21:40:19 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-05-26 21:40:19 -0400 |
commit | f35c69b736e4f910d7447346980145212c283570 (patch) | |
tree | 824b90cd870e6de07bbba19d761c1c74cf1fb4a7 /drivers/gpu/drm/radeon | |
parent | cd4373984a5903276f52777a6003425e023eaa7e (diff) | |
parent | e4aa937ec75df0eea0bee03bffa3303ad36c986b (diff) |
Merge 3.10-rc3 into char-misc-next
We want the changes in here.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 31 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen_hdmi.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r300_cmdbuf.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600_hdmi.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 22 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_bios.c | 28 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_device.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_drv.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_family.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_mode.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_ttm.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/si.c | 370 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/sid.h | 1 |
16 files changed, 380 insertions, 119 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 6d6fdb3ba0d0..d5df8fd10217 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -1811,12 +1811,9 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, | |||
1811 | 1811 | ||
1812 | static void atombios_crtc_prepare(struct drm_crtc *crtc) | 1812 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
1813 | { | 1813 | { |
1814 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
1815 | struct drm_device *dev = crtc->dev; | 1814 | struct drm_device *dev = crtc->dev; |
1816 | struct radeon_device *rdev = dev->dev_private; | 1815 | struct radeon_device *rdev = dev->dev_private; |
1817 | 1816 | ||
1818 | radeon_crtc->in_mode_set = true; | ||
1819 | |||
1820 | /* disable crtc pair power gating before programming */ | 1817 | /* disable crtc pair power gating before programming */ |
1821 | if (ASIC_IS_DCE6(rdev)) | 1818 | if (ASIC_IS_DCE6(rdev)) |
1822 | atombios_powergate_crtc(crtc, ATOM_DISABLE); | 1819 | atombios_powergate_crtc(crtc, ATOM_DISABLE); |
@@ -1827,11 +1824,8 @@ static void atombios_crtc_prepare(struct drm_crtc *crtc) | |||
1827 | 1824 | ||
1828 | static void atombios_crtc_commit(struct drm_crtc *crtc) | 1825 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
1829 | { | 1826 | { |
1830 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
1831 | |||
1832 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); | 1827 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
1833 | atombios_lock_crtc(crtc, ATOM_DISABLE); | 1828 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
1834 | radeon_crtc->in_mode_set = false; | ||
1835 | } | 1829 | } |
1836 | 1830 | ||
1837 | static void atombios_crtc_disable(struct drm_crtc *crtc) | 1831 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 105bafb6c29d..8f9e2d31b255 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -2343,11 +2343,13 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav | |||
2343 | u32 crtc_enabled, tmp, frame_count, blackout; | 2343 | u32 crtc_enabled, tmp, frame_count, blackout; |
2344 | int i, j; | 2344 | int i, j; |
2345 | 2345 | ||
2346 | save->vga_render_control = RREG32(VGA_RENDER_CONTROL); | 2346 | if (!ASIC_IS_NODCE(rdev)) { |
2347 | save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); | 2347 | save->vga_render_control = RREG32(VGA_RENDER_CONTROL); |
2348 | save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); | ||
2348 | 2349 | ||
2349 | /* disable VGA render */ | 2350 | /* disable VGA render */ |
2350 | WREG32(VGA_RENDER_CONTROL, 0); | 2351 | WREG32(VGA_RENDER_CONTROL, 0); |
2352 | } | ||
2351 | /* blank the display controllers */ | 2353 | /* blank the display controllers */ |
2352 | for (i = 0; i < rdev->num_crtc; i++) { | 2354 | for (i = 0; i < rdev->num_crtc; i++) { |
2353 | crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; | 2355 | crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; |
@@ -2438,8 +2440,11 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s | |||
2438 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], | 2440 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], |
2439 | (u32)rdev->mc.vram_start); | 2441 | (u32)rdev->mc.vram_start); |
2440 | } | 2442 | } |
2441 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); | 2443 | |
2442 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); | 2444 | if (!ASIC_IS_NODCE(rdev)) { |
2445 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); | ||
2446 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); | ||
2447 | } | ||
2443 | 2448 | ||
2444 | /* unlock regs and wait for update */ | 2449 | /* unlock regs and wait for update */ |
2445 | for (i = 0; i < rdev->num_crtc; i++) { | 2450 | for (i = 0; i < rdev->num_crtc; i++) { |
@@ -2499,10 +2504,12 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s | |||
2499 | } | 2504 | } |
2500 | } | 2505 | } |
2501 | } | 2506 | } |
2502 | /* Unlock vga access */ | 2507 | if (!ASIC_IS_NODCE(rdev)) { |
2503 | WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); | 2508 | /* Unlock vga access */ |
2504 | mdelay(1); | 2509 | WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); |
2505 | WREG32(VGA_RENDER_CONTROL, save->vga_render_control); | 2510 | mdelay(1); |
2511 | WREG32(VGA_RENDER_CONTROL, save->vga_render_control); | ||
2512 | } | ||
2506 | } | 2513 | } |
2507 | 2514 | ||
2508 | void evergreen_mc_program(struct radeon_device *rdev) | 2515 | void evergreen_mc_program(struct radeon_device *rdev) |
@@ -3405,8 +3412,8 @@ int evergreen_mc_init(struct radeon_device *rdev) | |||
3405 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | 3412 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
3406 | } else { | 3413 | } else { |
3407 | /* size in MB on evergreen/cayman/tn */ | 3414 | /* size in MB on evergreen/cayman/tn */ |
3408 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | 3415 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; |
3409 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | 3416 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; |
3410 | } | 3417 | } |
3411 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | 3418 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
3412 | r700_vram_gtt_location(rdev, &rdev->mc); | 3419 | r700_vram_gtt_location(rdev, &rdev->mc); |
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index b4ab8ceb1654..ed7c8a768092 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c | |||
@@ -154,19 +154,18 @@ static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |||
154 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 154 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
155 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 155 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
156 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | 156 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
157 | u32 base_rate = 48000; | 157 | u32 base_rate = 24000; |
158 | 158 | ||
159 | if (!dig || !dig->afmt) | 159 | if (!dig || !dig->afmt) |
160 | return; | 160 | return; |
161 | 161 | ||
162 | /* XXX: properly calculate this */ | ||
163 | /* XXX two dtos; generally use dto0 for hdmi */ | 162 | /* XXX two dtos; generally use dto0 for hdmi */ |
164 | /* Express [24MHz / target pixel clock] as an exact rational | 163 | /* Express [24MHz / target pixel clock] as an exact rational |
165 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | 164 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
166 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | 165 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
167 | */ | 166 | */ |
168 | WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff); | 167 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); |
169 | WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff); | 168 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
170 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); | 169 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); |
171 | } | 170 | } |
172 | 171 | ||
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c index 865e2c9980db..60170ea5e3a2 100644 --- a/drivers/gpu/drm/radeon/r300_cmdbuf.c +++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c | |||
@@ -75,7 +75,7 @@ static int r300_emit_cliprects(drm_radeon_private_t *dev_priv, | |||
75 | OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); | 75 | OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); |
76 | 76 | ||
77 | for (i = 0; i < nr; ++i) { | 77 | for (i = 0; i < nr; ++i) { |
78 | if (DRM_COPY_FROM_USER_UNCHECKED | 78 | if (DRM_COPY_FROM_USER |
79 | (&box, &cmdbuf->boxes[n + i], sizeof(box))) { | 79 | (&box, &cmdbuf->boxes[n + i], sizeof(box))) { |
80 | DRM_ERROR("copy cliprect faulted\n"); | 80 | DRM_ERROR("copy cliprect faulted\n"); |
81 | return -EFAULT; | 81 | return -EFAULT; |
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 47f180a79352..456750a0daa5 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c | |||
@@ -232,7 +232,7 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |||
232 | struct radeon_device *rdev = dev->dev_private; | 232 | struct radeon_device *rdev = dev->dev_private; |
233 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 233 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
234 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 234 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
235 | u32 base_rate = 48000; | 235 | u32 base_rate = 24000; |
236 | 236 | ||
237 | if (!dig || !dig->afmt) | 237 | if (!dig || !dig->afmt) |
238 | return; | 238 | return; |
@@ -240,7 +240,6 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |||
240 | /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. | 240 | /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. |
241 | * doesn't matter which one you use. Just use the first one. | 241 | * doesn't matter which one you use. Just use the first one. |
242 | */ | 242 | */ |
243 | /* XXX: properly calculate this */ | ||
244 | /* XXX two dtos; generally use dto0 for hdmi */ | 243 | /* XXX two dtos; generally use dto0 for hdmi */ |
245 | /* Express [24MHz / target pixel clock] as an exact rational | 244 | /* Express [24MHz / target pixel clock] as an exact rational |
246 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | 245 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
@@ -250,13 +249,13 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) | |||
250 | /* according to the reg specs, this should DCE3.2 only, but in | 249 | /* according to the reg specs, this should DCE3.2 only, but in |
251 | * practice it seems to cover DCE3.0 as well. | 250 | * practice it seems to cover DCE3.0 as well. |
252 | */ | 251 | */ |
253 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50); | 252 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); |
254 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); | 253 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
255 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ | 254 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ |
256 | } else { | 255 | } else { |
257 | /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ | 256 | /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ |
258 | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) | | 257 | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | |
259 | AUDIO_DTO_MODULE(clock * 100)); | 258 | AUDIO_DTO_MODULE(clock / 10)); |
260 | } | 259 | } |
261 | } | 260 | } |
262 | 261 | ||
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 1442ce765d48..142ce6cc69f5 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -1694,6 +1694,7 @@ struct radeon_device { | |||
1694 | int num_crtc; /* number of crtcs */ | 1694 | int num_crtc; /* number of crtcs */ |
1695 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ | 1695 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
1696 | bool audio_enabled; | 1696 | bool audio_enabled; |
1697 | bool has_uvd; | ||
1697 | struct r600_audio audio_status; /* audio stuff */ | 1698 | struct r600_audio audio_status; /* audio stuff */ |
1698 | struct notifier_block acpi_nb; | 1699 | struct notifier_block acpi_nb; |
1699 | /* only one userspace can use Hyperz features or CMASK at a time */ | 1700 | /* only one userspace can use Hyperz features or CMASK at a time */ |
@@ -1838,6 +1839,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); | |||
1838 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ | 1839 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
1839 | (rdev->flags & RADEON_IS_IGP)) | 1840 | (rdev->flags & RADEON_IS_IGP)) |
1840 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) | 1841 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
1842 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) | ||
1841 | 1843 | ||
1842 | /* | 1844 | /* |
1843 | * BIOS helpers. | 1845 | * BIOS helpers. |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 6417132c50cf..06b8c19ab19e 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -1935,6 +1935,8 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
1935 | else | 1935 | else |
1936 | rdev->num_crtc = 2; | 1936 | rdev->num_crtc = 2; |
1937 | 1937 | ||
1938 | rdev->has_uvd = false; | ||
1939 | |||
1938 | switch (rdev->family) { | 1940 | switch (rdev->family) { |
1939 | case CHIP_R100: | 1941 | case CHIP_R100: |
1940 | case CHIP_RV100: | 1942 | case CHIP_RV100: |
@@ -1999,16 +2001,22 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
1999 | case CHIP_RV635: | 2001 | case CHIP_RV635: |
2000 | case CHIP_RV670: | 2002 | case CHIP_RV670: |
2001 | rdev->asic = &r600_asic; | 2003 | rdev->asic = &r600_asic; |
2004 | if (rdev->family == CHIP_R600) | ||
2005 | rdev->has_uvd = false; | ||
2006 | else | ||
2007 | rdev->has_uvd = true; | ||
2002 | break; | 2008 | break; |
2003 | case CHIP_RS780: | 2009 | case CHIP_RS780: |
2004 | case CHIP_RS880: | 2010 | case CHIP_RS880: |
2005 | rdev->asic = &rs780_asic; | 2011 | rdev->asic = &rs780_asic; |
2012 | rdev->has_uvd = true; | ||
2006 | break; | 2013 | break; |
2007 | case CHIP_RV770: | 2014 | case CHIP_RV770: |
2008 | case CHIP_RV730: | 2015 | case CHIP_RV730: |
2009 | case CHIP_RV710: | 2016 | case CHIP_RV710: |
2010 | case CHIP_RV740: | 2017 | case CHIP_RV740: |
2011 | rdev->asic = &rv770_asic; | 2018 | rdev->asic = &rv770_asic; |
2019 | rdev->has_uvd = true; | ||
2012 | break; | 2020 | break; |
2013 | case CHIP_CEDAR: | 2021 | case CHIP_CEDAR: |
2014 | case CHIP_REDWOOD: | 2022 | case CHIP_REDWOOD: |
@@ -2021,11 +2029,13 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
2021 | else | 2029 | else |
2022 | rdev->num_crtc = 6; | 2030 | rdev->num_crtc = 6; |
2023 | rdev->asic = &evergreen_asic; | 2031 | rdev->asic = &evergreen_asic; |
2032 | rdev->has_uvd = true; | ||
2024 | break; | 2033 | break; |
2025 | case CHIP_PALM: | 2034 | case CHIP_PALM: |
2026 | case CHIP_SUMO: | 2035 | case CHIP_SUMO: |
2027 | case CHIP_SUMO2: | 2036 | case CHIP_SUMO2: |
2028 | rdev->asic = &sumo_asic; | 2037 | rdev->asic = &sumo_asic; |
2038 | rdev->has_uvd = true; | ||
2029 | break; | 2039 | break; |
2030 | case CHIP_BARTS: | 2040 | case CHIP_BARTS: |
2031 | case CHIP_TURKS: | 2041 | case CHIP_TURKS: |
@@ -2036,27 +2046,37 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
2036 | else | 2046 | else |
2037 | rdev->num_crtc = 6; | 2047 | rdev->num_crtc = 6; |
2038 | rdev->asic = &btc_asic; | 2048 | rdev->asic = &btc_asic; |
2049 | rdev->has_uvd = true; | ||
2039 | break; | 2050 | break; |
2040 | case CHIP_CAYMAN: | 2051 | case CHIP_CAYMAN: |
2041 | rdev->asic = &cayman_asic; | 2052 | rdev->asic = &cayman_asic; |
2042 | /* set num crtcs */ | 2053 | /* set num crtcs */ |
2043 | rdev->num_crtc = 6; | 2054 | rdev->num_crtc = 6; |
2055 | rdev->has_uvd = true; | ||
2044 | break; | 2056 | break; |
2045 | case CHIP_ARUBA: | 2057 | case CHIP_ARUBA: |
2046 | rdev->asic = &trinity_asic; | 2058 | rdev->asic = &trinity_asic; |
2047 | /* set num crtcs */ | 2059 | /* set num crtcs */ |
2048 | rdev->num_crtc = 4; | 2060 | rdev->num_crtc = 4; |
2061 | rdev->has_uvd = true; | ||
2049 | break; | 2062 | break; |
2050 | case CHIP_TAHITI: | 2063 | case CHIP_TAHITI: |
2051 | case CHIP_PITCAIRN: | 2064 | case CHIP_PITCAIRN: |
2052 | case CHIP_VERDE: | 2065 | case CHIP_VERDE: |
2053 | case CHIP_OLAND: | 2066 | case CHIP_OLAND: |
2067 | case CHIP_HAINAN: | ||
2054 | rdev->asic = &si_asic; | 2068 | rdev->asic = &si_asic; |
2055 | /* set num crtcs */ | 2069 | /* set num crtcs */ |
2056 | if (rdev->family == CHIP_OLAND) | 2070 | if (rdev->family == CHIP_HAINAN) |
2071 | rdev->num_crtc = 0; | ||
2072 | else if (rdev->family == CHIP_OLAND) | ||
2057 | rdev->num_crtc = 2; | 2073 | rdev->num_crtc = 2; |
2058 | else | 2074 | else |
2059 | rdev->num_crtc = 6; | 2075 | rdev->num_crtc = 6; |
2076 | if (rdev->family == CHIP_HAINAN) | ||
2077 | rdev->has_uvd = false; | ||
2078 | else | ||
2079 | rdev->has_uvd = true; | ||
2060 | break; | 2080 | break; |
2061 | default: | 2081 | default: |
2062 | /* FIXME: not supported yet */ | 2082 | /* FIXME: not supported yet */ |
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c index fa3c56fba294..061b227dae0c 100644 --- a/drivers/gpu/drm/radeon/radeon_bios.c +++ b/drivers/gpu/drm/radeon/radeon_bios.c | |||
@@ -244,24 +244,28 @@ static bool ni_read_disabled_bios(struct radeon_device *rdev) | |||
244 | 244 | ||
245 | /* enable the rom */ | 245 | /* enable the rom */ |
246 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); | 246 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
247 | /* Disable VGA mode */ | 247 | if (!ASIC_IS_NODCE(rdev)) { |
248 | WREG32(AVIVO_D1VGA_CONTROL, | 248 | /* Disable VGA mode */ |
249 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | 249 | WREG32(AVIVO_D1VGA_CONTROL, |
250 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | 250 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
251 | WREG32(AVIVO_D2VGA_CONTROL, | 251 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
252 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | 252 | WREG32(AVIVO_D2VGA_CONTROL, |
253 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | 253 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
254 | WREG32(AVIVO_VGA_RENDER_CONTROL, | 254 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
255 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | 255 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
256 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | ||
257 | } | ||
256 | WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); | 258 | WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); |
257 | 259 | ||
258 | r = radeon_read_bios(rdev); | 260 | r = radeon_read_bios(rdev); |
259 | 261 | ||
260 | /* restore regs */ | 262 | /* restore regs */ |
261 | WREG32(R600_BUS_CNTL, bus_cntl); | 263 | WREG32(R600_BUS_CNTL, bus_cntl); |
262 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); | 264 | if (!ASIC_IS_NODCE(rdev)) { |
263 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | 265 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
264 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | 266 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
267 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | ||
268 | } | ||
265 | WREG32(R600_ROM_CNTL, rom_cntl); | 269 | WREG32(R600_ROM_CNTL, rom_cntl); |
266 | return r; | 270 | return r; |
267 | } | 271 | } |
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index a8f608903989..c2c59fb1ea01 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -94,6 +94,7 @@ static const char radeon_family_name[][16] = { | |||
94 | "PITCAIRN", | 94 | "PITCAIRN", |
95 | "VERDE", | 95 | "VERDE", |
96 | "OLAND", | 96 | "OLAND", |
97 | "HAINAN", | ||
97 | "LAST", | 98 | "LAST", |
98 | }; | 99 | }; |
99 | 100 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index d33f484ace48..094e7e5ea39e 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c | |||
@@ -147,7 +147,7 @@ static inline void radeon_unregister_atpx_handler(void) {} | |||
147 | #endif | 147 | #endif |
148 | 148 | ||
149 | int radeon_no_wb; | 149 | int radeon_no_wb; |
150 | int radeon_modeset = 1; | 150 | int radeon_modeset = -1; |
151 | int radeon_dynclks = -1; | 151 | int radeon_dynclks = -1; |
152 | int radeon_r4xx_atom = 0; | 152 | int radeon_r4xx_atom = 0; |
153 | int radeon_agpmode = 0; | 153 | int radeon_agpmode = 0; |
@@ -456,6 +456,16 @@ static struct pci_driver radeon_kms_pci_driver = { | |||
456 | 456 | ||
457 | static int __init radeon_init(void) | 457 | static int __init radeon_init(void) |
458 | { | 458 | { |
459 | #ifdef CONFIG_VGA_CONSOLE | ||
460 | if (vgacon_text_force() && radeon_modeset == -1) { | ||
461 | DRM_INFO("VGACON disable radeon kernel modesetting.\n"); | ||
462 | radeon_modeset = 0; | ||
463 | } | ||
464 | #endif | ||
465 | /* set to modesetting by default if not nomodeset */ | ||
466 | if (radeon_modeset == -1) | ||
467 | radeon_modeset = 1; | ||
468 | |||
459 | if (radeon_modeset == 1) { | 469 | if (radeon_modeset == 1) { |
460 | DRM_INFO("radeon kernel modesetting enabled.\n"); | 470 | DRM_INFO("radeon kernel modesetting enabled.\n"); |
461 | driver = &kms_driver; | 471 | driver = &kms_driver; |
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h index 2d91123f2759..36e9803b077d 100644 --- a/drivers/gpu/drm/radeon/radeon_family.h +++ b/drivers/gpu/drm/radeon/radeon_family.h | |||
@@ -92,6 +92,7 @@ enum radeon_family { | |||
92 | CHIP_PITCAIRN, | 92 | CHIP_PITCAIRN, |
93 | CHIP_VERDE, | 93 | CHIP_VERDE, |
94 | CHIP_OLAND, | 94 | CHIP_OLAND, |
95 | CHIP_HAINAN, | ||
95 | CHIP_LAST, | 96 | CHIP_LAST, |
96 | }; | 97 | }; |
97 | 98 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index 6857cb4efb76..7cb178a34a0f 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c | |||
@@ -1031,11 +1031,9 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc, | |||
1031 | 1031 | ||
1032 | static void radeon_crtc_prepare(struct drm_crtc *crtc) | 1032 | static void radeon_crtc_prepare(struct drm_crtc *crtc) |
1033 | { | 1033 | { |
1034 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
1035 | struct drm_device *dev = crtc->dev; | 1034 | struct drm_device *dev = crtc->dev; |
1036 | struct drm_crtc *crtci; | 1035 | struct drm_crtc *crtci; |
1037 | 1036 | ||
1038 | radeon_crtc->in_mode_set = true; | ||
1039 | /* | 1037 | /* |
1040 | * The hardware wedges sometimes if you reconfigure one CRTC | 1038 | * The hardware wedges sometimes if you reconfigure one CRTC |
1041 | * whilst another is running (see fdo bug #24611). | 1039 | * whilst another is running (see fdo bug #24611). |
@@ -1046,7 +1044,6 @@ static void radeon_crtc_prepare(struct drm_crtc *crtc) | |||
1046 | 1044 | ||
1047 | static void radeon_crtc_commit(struct drm_crtc *crtc) | 1045 | static void radeon_crtc_commit(struct drm_crtc *crtc) |
1048 | { | 1046 | { |
1049 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | ||
1050 | struct drm_device *dev = crtc->dev; | 1047 | struct drm_device *dev = crtc->dev; |
1051 | struct drm_crtc *crtci; | 1048 | struct drm_crtc *crtci; |
1052 | 1049 | ||
@@ -1057,7 +1054,6 @@ static void radeon_crtc_commit(struct drm_crtc *crtc) | |||
1057 | if (crtci->enabled) | 1054 | if (crtci->enabled) |
1058 | radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); | 1055 | radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); |
1059 | } | 1056 | } |
1060 | radeon_crtc->in_mode_set = false; | ||
1061 | } | 1057 | } |
1062 | 1058 | ||
1063 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { | 1059 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 44e579e75fd0..69ad4fe224c1 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h | |||
@@ -302,7 +302,6 @@ struct radeon_crtc { | |||
302 | u16 lut_r[256], lut_g[256], lut_b[256]; | 302 | u16 lut_r[256], lut_g[256], lut_b[256]; |
303 | bool enabled; | 303 | bool enabled; |
304 | bool can_tile; | 304 | bool can_tile; |
305 | bool in_mode_set; | ||
306 | uint32_t crtc_offset; | 305 | uint32_t crtc_offset; |
307 | struct drm_gem_object *cursor_bo; | 306 | struct drm_gem_object *cursor_bo; |
308 | uint64_t cursor_addr; | 307 | uint64_t cursor_addr; |
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 93f760e27a92..6c0ce8915fac 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c | |||
@@ -726,7 +726,7 @@ int radeon_ttm_init(struct radeon_device *rdev) | |||
726 | return r; | 726 | return r; |
727 | } | 727 | } |
728 | DRM_INFO("radeon: %uM of VRAM memory ready\n", | 728 | DRM_INFO("radeon: %uM of VRAM memory ready\n", |
729 | (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); | 729 | (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); |
730 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, | 730 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
731 | rdev->mc.gtt_size >> PAGE_SHIFT); | 731 | rdev->mc.gtt_size >> PAGE_SHIFT); |
732 | if (r) { | 732 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index f0b6c2f87c4d..5ffade69af25 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -60,6 +60,11 @@ MODULE_FIRMWARE("radeon/OLAND_me.bin"); | |||
60 | MODULE_FIRMWARE("radeon/OLAND_ce.bin"); | 60 | MODULE_FIRMWARE("radeon/OLAND_ce.bin"); |
61 | MODULE_FIRMWARE("radeon/OLAND_mc.bin"); | 61 | MODULE_FIRMWARE("radeon/OLAND_mc.bin"); |
62 | MODULE_FIRMWARE("radeon/OLAND_rlc.bin"); | 62 | MODULE_FIRMWARE("radeon/OLAND_rlc.bin"); |
63 | MODULE_FIRMWARE("radeon/HAINAN_pfp.bin"); | ||
64 | MODULE_FIRMWARE("radeon/HAINAN_me.bin"); | ||
65 | MODULE_FIRMWARE("radeon/HAINAN_ce.bin"); | ||
66 | MODULE_FIRMWARE("radeon/HAINAN_mc.bin"); | ||
67 | MODULE_FIRMWARE("radeon/HAINAN_rlc.bin"); | ||
63 | 68 | ||
64 | extern int r600_ih_ring_alloc(struct radeon_device *rdev); | 69 | extern int r600_ih_ring_alloc(struct radeon_device *rdev); |
65 | extern void r600_ih_ring_fini(struct radeon_device *rdev); | 70 | extern void r600_ih_ring_fini(struct radeon_device *rdev); |
@@ -265,6 +270,40 @@ static const u32 oland_golden_registers[] = | |||
265 | 0x15c0, 0x000c0fc0, 0x000c0400 | 270 | 0x15c0, 0x000c0fc0, 0x000c0400 |
266 | }; | 271 | }; |
267 | 272 | ||
273 | static const u32 hainan_golden_registers[] = | ||
274 | { | ||
275 | 0x9a10, 0x00010000, 0x00018208, | ||
276 | 0x9830, 0xffffffff, 0x00000000, | ||
277 | 0x9834, 0xf00fffff, 0x00000400, | ||
278 | 0x9838, 0x0002021c, 0x00020200, | ||
279 | 0xd0c0, 0xff000fff, 0x00000100, | ||
280 | 0xd030, 0x000300c0, 0x00800040, | ||
281 | 0xd8c0, 0xff000fff, 0x00000100, | ||
282 | 0xd830, 0x000300c0, 0x00800040, | ||
283 | 0x2ae4, 0x00073ffe, 0x000022a2, | ||
284 | 0x240c, 0x000007ff, 0x00000000, | ||
285 | 0x8a14, 0xf000001f, 0x00000007, | ||
286 | 0x8b24, 0xffffffff, 0x00ffffff, | ||
287 | 0x8b10, 0x0000ff0f, 0x00000000, | ||
288 | 0x28a4c, 0x07ffffff, 0x4e000000, | ||
289 | 0x28350, 0x3f3f3fff, 0x00000000, | ||
290 | 0x30, 0x000000ff, 0x0040, | ||
291 | 0x34, 0x00000040, 0x00004040, | ||
292 | 0x9100, 0x03e00000, 0x03600000, | ||
293 | 0x9060, 0x0000007f, 0x00000020, | ||
294 | 0x9508, 0x00010000, 0x00010000, | ||
295 | 0xac14, 0x000003ff, 0x000000f1, | ||
296 | 0xac10, 0xffffffff, 0x00000000, | ||
297 | 0xac0c, 0xffffffff, 0x00003210, | ||
298 | 0x88d4, 0x0000001f, 0x00000010, | ||
299 | 0x15c0, 0x000c0fc0, 0x000c0400 | ||
300 | }; | ||
301 | |||
302 | static const u32 hainan_golden_registers2[] = | ||
303 | { | ||
304 | 0x98f8, 0xffffffff, 0x02010001 | ||
305 | }; | ||
306 | |||
268 | static const u32 tahiti_mgcg_cgcg_init[] = | 307 | static const u32 tahiti_mgcg_cgcg_init[] = |
269 | { | 308 | { |
270 | 0xc400, 0xffffffff, 0xfffffffc, | 309 | 0xc400, 0xffffffff, 0xfffffffc, |
@@ -673,6 +712,83 @@ static const u32 oland_mgcg_cgcg_init[] = | |||
673 | 0xd8c0, 0xfffffff0, 0x00000100 | 712 | 0xd8c0, 0xfffffff0, 0x00000100 |
674 | }; | 713 | }; |
675 | 714 | ||
715 | static const u32 hainan_mgcg_cgcg_init[] = | ||
716 | { | ||
717 | 0xc400, 0xffffffff, 0xfffffffc, | ||
718 | 0x802c, 0xffffffff, 0xe0000000, | ||
719 | 0x9a60, 0xffffffff, 0x00000100, | ||
720 | 0x92a4, 0xffffffff, 0x00000100, | ||
721 | 0xc164, 0xffffffff, 0x00000100, | ||
722 | 0x9774, 0xffffffff, 0x00000100, | ||
723 | 0x8984, 0xffffffff, 0x06000100, | ||
724 | 0x8a18, 0xffffffff, 0x00000100, | ||
725 | 0x92a0, 0xffffffff, 0x00000100, | ||
726 | 0xc380, 0xffffffff, 0x00000100, | ||
727 | 0x8b28, 0xffffffff, 0x00000100, | ||
728 | 0x9144, 0xffffffff, 0x00000100, | ||
729 | 0x8d88, 0xffffffff, 0x00000100, | ||
730 | 0x8d8c, 0xffffffff, 0x00000100, | ||
731 | 0x9030, 0xffffffff, 0x00000100, | ||
732 | 0x9034, 0xffffffff, 0x00000100, | ||
733 | 0x9038, 0xffffffff, 0x00000100, | ||
734 | 0x903c, 0xffffffff, 0x00000100, | ||
735 | 0xad80, 0xffffffff, 0x00000100, | ||
736 | 0xac54, 0xffffffff, 0x00000100, | ||
737 | 0x897c, 0xffffffff, 0x06000100, | ||
738 | 0x9868, 0xffffffff, 0x00000100, | ||
739 | 0x9510, 0xffffffff, 0x00000100, | ||
740 | 0xaf04, 0xffffffff, 0x00000100, | ||
741 | 0xae04, 0xffffffff, 0x00000100, | ||
742 | 0x949c, 0xffffffff, 0x00000100, | ||
743 | 0x802c, 0xffffffff, 0xe0000000, | ||
744 | 0x9160, 0xffffffff, 0x00010000, | ||
745 | 0x9164, 0xffffffff, 0x00030002, | ||
746 | 0x9168, 0xffffffff, 0x00040007, | ||
747 | 0x916c, 0xffffffff, 0x00060005, | ||
748 | 0x9170, 0xffffffff, 0x00090008, | ||
749 | 0x9174, 0xffffffff, 0x00020001, | ||
750 | 0x9178, 0xffffffff, 0x00040003, | ||
751 | 0x917c, 0xffffffff, 0x00000007, | ||
752 | 0x9180, 0xffffffff, 0x00060005, | ||
753 | 0x9184, 0xffffffff, 0x00090008, | ||
754 | 0x9188, 0xffffffff, 0x00030002, | ||
755 | 0x918c, 0xffffffff, 0x00050004, | ||
756 | 0x9190, 0xffffffff, 0x00000008, | ||
757 | 0x9194, 0xffffffff, 0x00070006, | ||
758 | 0x9198, 0xffffffff, 0x000a0009, | ||
759 | 0x919c, 0xffffffff, 0x00040003, | ||
760 | 0x91a0, 0xffffffff, 0x00060005, | ||
761 | 0x91a4, 0xffffffff, 0x00000009, | ||
762 | 0x91a8, 0xffffffff, 0x00080007, | ||
763 | 0x91ac, 0xffffffff, 0x000b000a, | ||
764 | 0x91b0, 0xffffffff, 0x00050004, | ||
765 | 0x91b4, 0xffffffff, 0x00070006, | ||
766 | 0x91b8, 0xffffffff, 0x0008000b, | ||
767 | 0x91bc, 0xffffffff, 0x000a0009, | ||
768 | 0x91c0, 0xffffffff, 0x000d000c, | ||
769 | 0x91c4, 0xffffffff, 0x00060005, | ||
770 | 0x91c8, 0xffffffff, 0x00080007, | ||
771 | 0x91cc, 0xffffffff, 0x0000000b, | ||
772 | 0x91d0, 0xffffffff, 0x000a0009, | ||
773 | 0x91d4, 0xffffffff, 0x000d000c, | ||
774 | 0x9150, 0xffffffff, 0x96940200, | ||
775 | 0x8708, 0xffffffff, 0x00900100, | ||
776 | 0xc478, 0xffffffff, 0x00000080, | ||
777 | 0xc404, 0xffffffff, 0x0020003f, | ||
778 | 0x30, 0xffffffff, 0x0000001c, | ||
779 | 0x34, 0x000f0000, 0x000f0000, | ||
780 | 0x160c, 0xffffffff, 0x00000100, | ||
781 | 0x1024, 0xffffffff, 0x00000100, | ||
782 | 0x20a8, 0xffffffff, 0x00000104, | ||
783 | 0x264c, 0x000c0000, 0x000c0000, | ||
784 | 0x2648, 0x000c0000, 0x000c0000, | ||
785 | 0x2f50, 0x00000001, 0x00000001, | ||
786 | 0x30cc, 0xc0000fff, 0x00000104, | ||
787 | 0xc1e4, 0x00000001, 0x00000001, | ||
788 | 0xd0c0, 0xfffffff0, 0x00000100, | ||
789 | 0xd8c0, 0xfffffff0, 0x00000100 | ||
790 | }; | ||
791 | |||
676 | static u32 verde_pg_init[] = | 792 | static u32 verde_pg_init[] = |
677 | { | 793 | { |
678 | 0x353c, 0xffffffff, 0x40000, | 794 | 0x353c, 0xffffffff, 0x40000, |
@@ -853,6 +969,17 @@ static void si_init_golden_registers(struct radeon_device *rdev) | |||
853 | oland_mgcg_cgcg_init, | 969 | oland_mgcg_cgcg_init, |
854 | (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); | 970 | (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); |
855 | break; | 971 | break; |
972 | case CHIP_HAINAN: | ||
973 | radeon_program_register_sequence(rdev, | ||
974 | hainan_golden_registers, | ||
975 | (const u32)ARRAY_SIZE(hainan_golden_registers)); | ||
976 | radeon_program_register_sequence(rdev, | ||
977 | hainan_golden_registers2, | ||
978 | (const u32)ARRAY_SIZE(hainan_golden_registers2)); | ||
979 | radeon_program_register_sequence(rdev, | ||
980 | hainan_mgcg_cgcg_init, | ||
981 | (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init)); | ||
982 | break; | ||
856 | default: | 983 | default: |
857 | break; | 984 | break; |
858 | } | 985 | } |
@@ -1062,6 +1189,45 @@ static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { | |||
1062 | {0x0000009f, 0x00a17730} | 1189 | {0x0000009f, 0x00a17730} |
1063 | }; | 1190 | }; |
1064 | 1191 | ||
1192 | static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { | ||
1193 | {0x0000006f, 0x03044000}, | ||
1194 | {0x00000070, 0x0480c018}, | ||
1195 | {0x00000071, 0x00000040}, | ||
1196 | {0x00000072, 0x01000000}, | ||
1197 | {0x00000074, 0x000000ff}, | ||
1198 | {0x00000075, 0x00143400}, | ||
1199 | {0x00000076, 0x08ec0800}, | ||
1200 | {0x00000077, 0x040000cc}, | ||
1201 | {0x00000079, 0x00000000}, | ||
1202 | {0x0000007a, 0x21000409}, | ||
1203 | {0x0000007c, 0x00000000}, | ||
1204 | {0x0000007d, 0xe8000000}, | ||
1205 | {0x0000007e, 0x044408a8}, | ||
1206 | {0x0000007f, 0x00000003}, | ||
1207 | {0x00000080, 0x00000000}, | ||
1208 | {0x00000081, 0x01000000}, | ||
1209 | {0x00000082, 0x02000000}, | ||
1210 | {0x00000083, 0x00000000}, | ||
1211 | {0x00000084, 0xe3f3e4f4}, | ||
1212 | {0x00000085, 0x00052024}, | ||
1213 | {0x00000087, 0x00000000}, | ||
1214 | {0x00000088, 0x66036603}, | ||
1215 | {0x00000089, 0x01000000}, | ||
1216 | {0x0000008b, 0x1c0a0000}, | ||
1217 | {0x0000008c, 0xff010000}, | ||
1218 | {0x0000008e, 0xffffefff}, | ||
1219 | {0x0000008f, 0xfff3efff}, | ||
1220 | {0x00000090, 0xfff3efbf}, | ||
1221 | {0x00000094, 0x00101101}, | ||
1222 | {0x00000095, 0x00000fff}, | ||
1223 | {0x00000096, 0x00116fff}, | ||
1224 | {0x00000097, 0x60010000}, | ||
1225 | {0x00000098, 0x10010000}, | ||
1226 | {0x00000099, 0x00006000}, | ||
1227 | {0x0000009a, 0x00001000}, | ||
1228 | {0x0000009f, 0x00a07730} | ||
1229 | }; | ||
1230 | |||
1065 | /* ucode loading */ | 1231 | /* ucode loading */ |
1066 | static int si_mc_load_microcode(struct radeon_device *rdev) | 1232 | static int si_mc_load_microcode(struct radeon_device *rdev) |
1067 | { | 1233 | { |
@@ -1095,6 +1261,11 @@ static int si_mc_load_microcode(struct radeon_device *rdev) | |||
1095 | ucode_size = OLAND_MC_UCODE_SIZE; | 1261 | ucode_size = OLAND_MC_UCODE_SIZE; |
1096 | regs_size = TAHITI_IO_MC_REGS_SIZE; | 1262 | regs_size = TAHITI_IO_MC_REGS_SIZE; |
1097 | break; | 1263 | break; |
1264 | case CHIP_HAINAN: | ||
1265 | io_mc_regs = (u32 *)&hainan_io_mc_regs; | ||
1266 | ucode_size = OLAND_MC_UCODE_SIZE; | ||
1267 | regs_size = TAHITI_IO_MC_REGS_SIZE; | ||
1268 | break; | ||
1098 | } | 1269 | } |
1099 | 1270 | ||
1100 | running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; | 1271 | running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; |
@@ -1198,6 +1369,15 @@ static int si_init_microcode(struct radeon_device *rdev) | |||
1198 | rlc_req_size = SI_RLC_UCODE_SIZE * 4; | 1369 | rlc_req_size = SI_RLC_UCODE_SIZE * 4; |
1199 | mc_req_size = OLAND_MC_UCODE_SIZE * 4; | 1370 | mc_req_size = OLAND_MC_UCODE_SIZE * 4; |
1200 | break; | 1371 | break; |
1372 | case CHIP_HAINAN: | ||
1373 | chip_name = "HAINAN"; | ||
1374 | rlc_chip_name = "HAINAN"; | ||
1375 | pfp_req_size = SI_PFP_UCODE_SIZE * 4; | ||
1376 | me_req_size = SI_PM4_UCODE_SIZE * 4; | ||
1377 | ce_req_size = SI_CE_UCODE_SIZE * 4; | ||
1378 | rlc_req_size = SI_RLC_UCODE_SIZE * 4; | ||
1379 | mc_req_size = OLAND_MC_UCODE_SIZE * 4; | ||
1380 | break; | ||
1201 | default: BUG(); | 1381 | default: BUG(); |
1202 | } | 1382 | } |
1203 | 1383 | ||
@@ -2003,7 +2183,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev) | |||
2003 | WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); | 2183 | WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); |
2004 | } | 2184 | } |
2005 | } else if ((rdev->family == CHIP_VERDE) || | 2185 | } else if ((rdev->family == CHIP_VERDE) || |
2006 | (rdev->family == CHIP_OLAND)) { | 2186 | (rdev->family == CHIP_OLAND) || |
2187 | (rdev->family == CHIP_HAINAN)) { | ||
2007 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { | 2188 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { |
2008 | switch (reg_offset) { | 2189 | switch (reg_offset) { |
2009 | case 0: /* non-AA compressed depth or any compressed stencil */ | 2190 | case 0: /* non-AA compressed depth or any compressed stencil */ |
@@ -2466,6 +2647,23 @@ static void si_gpu_init(struct radeon_device *rdev) | |||
2466 | rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; | 2647 | rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; |
2467 | gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; | 2648 | gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; |
2468 | break; | 2649 | break; |
2650 | case CHIP_HAINAN: | ||
2651 | rdev->config.si.max_shader_engines = 1; | ||
2652 | rdev->config.si.max_tile_pipes = 4; | ||
2653 | rdev->config.si.max_cu_per_sh = 5; | ||
2654 | rdev->config.si.max_sh_per_se = 1; | ||
2655 | rdev->config.si.max_backends_per_se = 1; | ||
2656 | rdev->config.si.max_texture_channel_caches = 2; | ||
2657 | rdev->config.si.max_gprs = 256; | ||
2658 | rdev->config.si.max_gs_threads = 16; | ||
2659 | rdev->config.si.max_hw_contexts = 8; | ||
2660 | |||
2661 | rdev->config.si.sc_prim_fifo_size_frontend = 0x20; | ||
2662 | rdev->config.si.sc_prim_fifo_size_backend = 0x40; | ||
2663 | rdev->config.si.sc_hiz_tile_fifo_size = 0x30; | ||
2664 | rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; | ||
2665 | gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; | ||
2666 | break; | ||
2469 | } | 2667 | } |
2470 | 2668 | ||
2471 | /* Initialize HDP */ | 2669 | /* Initialize HDP */ |
@@ -2559,9 +2757,11 @@ static void si_gpu_init(struct radeon_device *rdev) | |||
2559 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); | 2757 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
2560 | WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); | 2758 | WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); |
2561 | WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); | 2759 | WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); |
2562 | WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); | 2760 | if (rdev->has_uvd) { |
2563 | WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); | 2761 | WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); |
2564 | WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); | 2762 | WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); |
2763 | WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); | ||
2764 | } | ||
2565 | 2765 | ||
2566 | si_tiling_mode_table_init(rdev); | 2766 | si_tiling_mode_table_init(rdev); |
2567 | 2767 | ||
@@ -3304,8 +3504,9 @@ static void si_mc_program(struct radeon_device *rdev) | |||
3304 | if (radeon_mc_wait_for_idle(rdev)) { | 3504 | if (radeon_mc_wait_for_idle(rdev)) { |
3305 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | 3505 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3306 | } | 3506 | } |
3307 | /* Lockout access through VGA aperture*/ | 3507 | if (!ASIC_IS_NODCE(rdev)) |
3308 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); | 3508 | /* Lockout access through VGA aperture*/ |
3509 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); | ||
3309 | /* Update configuration */ | 3510 | /* Update configuration */ |
3310 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | 3511 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
3311 | rdev->mc.vram_start >> 12); | 3512 | rdev->mc.vram_start >> 12); |
@@ -3327,9 +3528,11 @@ static void si_mc_program(struct radeon_device *rdev) | |||
3327 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | 3528 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3328 | } | 3529 | } |
3329 | evergreen_mc_resume(rdev, &save); | 3530 | evergreen_mc_resume(rdev, &save); |
3330 | /* we need to own VRAM, so turn off the VGA renderer here | 3531 | if (!ASIC_IS_NODCE(rdev)) { |
3331 | * to stop it overwriting our objects */ | 3532 | /* we need to own VRAM, so turn off the VGA renderer here |
3332 | rv515_vga_render_disable(rdev); | 3533 | * to stop it overwriting our objects */ |
3534 | rv515_vga_render_disable(rdev); | ||
3535 | } | ||
3333 | } | 3536 | } |
3334 | 3537 | ||
3335 | static void si_vram_gtt_location(struct radeon_device *rdev, | 3538 | static void si_vram_gtt_location(struct radeon_device *rdev, |
@@ -3397,8 +3600,8 @@ static int si_mc_init(struct radeon_device *rdev) | |||
3397 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); | 3600 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
3398 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | 3601 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
3399 | /* size in MB on si */ | 3602 | /* size in MB on si */ |
3400 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | 3603 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; |
3401 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | 3604 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; |
3402 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | 3605 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
3403 | si_vram_gtt_location(rdev, &rdev->mc); | 3606 | si_vram_gtt_location(rdev, &rdev->mc); |
3404 | radeon_update_bandwidth_info(rdev); | 3607 | radeon_update_bandwidth_info(rdev); |
@@ -4251,8 +4454,10 @@ static void si_disable_interrupt_state(struct radeon_device *rdev) | |||
4251 | tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; | 4454 | tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; |
4252 | WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); | 4455 | WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); |
4253 | WREG32(GRBM_INT_CNTL, 0); | 4456 | WREG32(GRBM_INT_CNTL, 0); |
4254 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | 4457 | if (rdev->num_crtc >= 2) { |
4255 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | 4458 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
4459 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | ||
4460 | } | ||
4256 | if (rdev->num_crtc >= 4) { | 4461 | if (rdev->num_crtc >= 4) { |
4257 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); | 4462 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
4258 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | 4463 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
@@ -4262,8 +4467,10 @@ static void si_disable_interrupt_state(struct radeon_device *rdev) | |||
4262 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | 4467 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
4263 | } | 4468 | } |
4264 | 4469 | ||
4265 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | 4470 | if (rdev->num_crtc >= 2) { |
4266 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | 4471 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
4472 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | ||
4473 | } | ||
4267 | if (rdev->num_crtc >= 4) { | 4474 | if (rdev->num_crtc >= 4) { |
4268 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); | 4475 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
4269 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | 4476 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
@@ -4273,21 +4480,22 @@ static void si_disable_interrupt_state(struct radeon_device *rdev) | |||
4273 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | 4480 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
4274 | } | 4481 | } |
4275 | 4482 | ||
4276 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | 4483 | if (!ASIC_IS_NODCE(rdev)) { |
4277 | 4484 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
4278 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4279 | WREG32(DC_HPD1_INT_CONTROL, tmp); | ||
4280 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4281 | WREG32(DC_HPD2_INT_CONTROL, tmp); | ||
4282 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4283 | WREG32(DC_HPD3_INT_CONTROL, tmp); | ||
4284 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4285 | WREG32(DC_HPD4_INT_CONTROL, tmp); | ||
4286 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4287 | WREG32(DC_HPD5_INT_CONTROL, tmp); | ||
4288 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4289 | WREG32(DC_HPD6_INT_CONTROL, tmp); | ||
4290 | 4485 | ||
4486 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4487 | WREG32(DC_HPD1_INT_CONTROL, tmp); | ||
4488 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4489 | WREG32(DC_HPD2_INT_CONTROL, tmp); | ||
4490 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4491 | WREG32(DC_HPD3_INT_CONTROL, tmp); | ||
4492 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4493 | WREG32(DC_HPD4_INT_CONTROL, tmp); | ||
4494 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4495 | WREG32(DC_HPD5_INT_CONTROL, tmp); | ||
4496 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; | ||
4497 | WREG32(DC_HPD6_INT_CONTROL, tmp); | ||
4498 | } | ||
4291 | } | 4499 | } |
4292 | 4500 | ||
4293 | static int si_irq_init(struct radeon_device *rdev) | 4501 | static int si_irq_init(struct radeon_device *rdev) |
@@ -4366,7 +4574,7 @@ int si_irq_set(struct radeon_device *rdev) | |||
4366 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; | 4574 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
4367 | u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; | 4575 | u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; |
4368 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; | 4576 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
4369 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; | 4577 | u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
4370 | u32 grbm_int_cntl = 0; | 4578 | u32 grbm_int_cntl = 0; |
4371 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; | 4579 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; |
4372 | u32 dma_cntl, dma_cntl1; | 4580 | u32 dma_cntl, dma_cntl1; |
@@ -4383,12 +4591,14 @@ int si_irq_set(struct radeon_device *rdev) | |||
4383 | return 0; | 4591 | return 0; |
4384 | } | 4592 | } |
4385 | 4593 | ||
4386 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; | 4594 | if (!ASIC_IS_NODCE(rdev)) { |
4387 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | 4595 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4388 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | 4596 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4389 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | 4597 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4390 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | 4598 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4391 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | 4599 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
4600 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | ||
4601 | } | ||
4392 | 4602 | ||
4393 | dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; | 4603 | dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; |
4394 | dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; | 4604 | dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; |
@@ -4479,8 +4689,10 @@ int si_irq_set(struct radeon_device *rdev) | |||
4479 | 4689 | ||
4480 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); | 4690 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
4481 | 4691 | ||
4482 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); | 4692 | if (rdev->num_crtc >= 2) { |
4483 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); | 4693 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); |
4694 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); | ||
4695 | } | ||
4484 | if (rdev->num_crtc >= 4) { | 4696 | if (rdev->num_crtc >= 4) { |
4485 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); | 4697 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); |
4486 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); | 4698 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); |
@@ -4490,8 +4702,10 @@ int si_irq_set(struct radeon_device *rdev) | |||
4490 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); | 4702 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); |
4491 | } | 4703 | } |
4492 | 4704 | ||
4493 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); | 4705 | if (rdev->num_crtc >= 2) { |
4494 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); | 4706 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); |
4707 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); | ||
4708 | } | ||
4495 | if (rdev->num_crtc >= 4) { | 4709 | if (rdev->num_crtc >= 4) { |
4496 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); | 4710 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); |
4497 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); | 4711 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); |
@@ -4501,12 +4715,14 @@ int si_irq_set(struct radeon_device *rdev) | |||
4501 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); | 4715 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); |
4502 | } | 4716 | } |
4503 | 4717 | ||
4504 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | 4718 | if (!ASIC_IS_NODCE(rdev)) { |
4505 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | 4719 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
4506 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | 4720 | WREG32(DC_HPD2_INT_CONTROL, hpd2); |
4507 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | 4721 | WREG32(DC_HPD3_INT_CONTROL, hpd3); |
4508 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | 4722 | WREG32(DC_HPD4_INT_CONTROL, hpd4); |
4509 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | 4723 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
4724 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | ||
4725 | } | ||
4510 | 4726 | ||
4511 | return 0; | 4727 | return 0; |
4512 | } | 4728 | } |
@@ -4515,6 +4731,9 @@ static inline void si_irq_ack(struct radeon_device *rdev) | |||
4515 | { | 4731 | { |
4516 | u32 tmp; | 4732 | u32 tmp; |
4517 | 4733 | ||
4734 | if (ASIC_IS_NODCE(rdev)) | ||
4735 | return; | ||
4736 | |||
4518 | rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); | 4737 | rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
4519 | rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | 4738 | rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); |
4520 | rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); | 4739 | rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); |
@@ -5118,15 +5337,17 @@ static int si_startup(struct radeon_device *rdev) | |||
5118 | return r; | 5337 | return r; |
5119 | } | 5338 | } |
5120 | 5339 | ||
5121 | r = rv770_uvd_resume(rdev); | 5340 | if (rdev->has_uvd) { |
5122 | if (!r) { | 5341 | r = rv770_uvd_resume(rdev); |
5123 | r = radeon_fence_driver_start_ring(rdev, | 5342 | if (!r) { |
5124 | R600_RING_TYPE_UVD_INDEX); | 5343 | r = radeon_fence_driver_start_ring(rdev, |
5344 | R600_RING_TYPE_UVD_INDEX); | ||
5345 | if (r) | ||
5346 | dev_err(rdev->dev, "UVD fences init error (%d).\n", r); | ||
5347 | } | ||
5125 | if (r) | 5348 | if (r) |
5126 | dev_err(rdev->dev, "UVD fences init error (%d).\n", r); | 5349 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
5127 | } | 5350 | } |
5128 | if (r) | ||
5129 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; | ||
5130 | 5351 | ||
5131 | /* Enable IRQ */ | 5352 | /* Enable IRQ */ |
5132 | r = si_irq_init(rdev); | 5353 | r = si_irq_init(rdev); |
@@ -5185,16 +5406,18 @@ static int si_startup(struct radeon_device *rdev) | |||
5185 | if (r) | 5406 | if (r) |
5186 | return r; | 5407 | return r; |
5187 | 5408 | ||
5188 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; | 5409 | if (rdev->has_uvd) { |
5189 | if (ring->ring_size) { | 5410 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
5190 | r = radeon_ring_init(rdev, ring, ring->ring_size, | 5411 | if (ring->ring_size) { |
5191 | R600_WB_UVD_RPTR_OFFSET, | 5412 | r = radeon_ring_init(rdev, ring, ring->ring_size, |
5192 | UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, | 5413 | R600_WB_UVD_RPTR_OFFSET, |
5193 | 0, 0xfffff, RADEON_CP_PACKET2); | 5414 | UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, |
5194 | if (!r) | 5415 | 0, 0xfffff, RADEON_CP_PACKET2); |
5195 | r = r600_uvd_init(rdev); | 5416 | if (!r) |
5196 | if (r) | 5417 | r = r600_uvd_init(rdev); |
5197 | DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); | 5418 | if (r) |
5419 | DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); | ||
5420 | } | ||
5198 | } | 5421 | } |
5199 | 5422 | ||
5200 | r = radeon_ib_pool_init(rdev); | 5423 | r = radeon_ib_pool_init(rdev); |
@@ -5243,8 +5466,10 @@ int si_suspend(struct radeon_device *rdev) | |||
5243 | radeon_vm_manager_fini(rdev); | 5466 | radeon_vm_manager_fini(rdev); |
5244 | si_cp_enable(rdev, false); | 5467 | si_cp_enable(rdev, false); |
5245 | cayman_dma_stop(rdev); | 5468 | cayman_dma_stop(rdev); |
5246 | r600_uvd_rbc_stop(rdev); | 5469 | if (rdev->has_uvd) { |
5247 | radeon_uvd_suspend(rdev); | 5470 | r600_uvd_rbc_stop(rdev); |
5471 | radeon_uvd_suspend(rdev); | ||
5472 | } | ||
5248 | si_irq_suspend(rdev); | 5473 | si_irq_suspend(rdev); |
5249 | radeon_wb_disable(rdev); | 5474 | radeon_wb_disable(rdev); |
5250 | si_pcie_gart_disable(rdev); | 5475 | si_pcie_gart_disable(rdev); |
@@ -5332,11 +5557,13 @@ int si_init(struct radeon_device *rdev) | |||
5332 | ring->ring_obj = NULL; | 5557 | ring->ring_obj = NULL; |
5333 | r600_ring_init(rdev, ring, 64 * 1024); | 5558 | r600_ring_init(rdev, ring, 64 * 1024); |
5334 | 5559 | ||
5335 | r = radeon_uvd_init(rdev); | 5560 | if (rdev->has_uvd) { |
5336 | if (!r) { | 5561 | r = radeon_uvd_init(rdev); |
5337 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; | 5562 | if (!r) { |
5338 | ring->ring_obj = NULL; | 5563 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
5339 | r600_ring_init(rdev, ring, 4096); | 5564 | ring->ring_obj = NULL; |
5565 | r600_ring_init(rdev, ring, 4096); | ||
5566 | } | ||
5340 | } | 5567 | } |
5341 | 5568 | ||
5342 | rdev->ih.ring_obj = NULL; | 5569 | rdev->ih.ring_obj = NULL; |
@@ -5384,7 +5611,8 @@ void si_fini(struct radeon_device *rdev) | |||
5384 | radeon_vm_manager_fini(rdev); | 5611 | radeon_vm_manager_fini(rdev); |
5385 | radeon_ib_pool_fini(rdev); | 5612 | radeon_ib_pool_fini(rdev); |
5386 | radeon_irq_kms_fini(rdev); | 5613 | radeon_irq_kms_fini(rdev); |
5387 | radeon_uvd_fini(rdev); | 5614 | if (rdev->has_uvd) |
5615 | radeon_uvd_fini(rdev); | ||
5388 | si_pcie_gart_fini(rdev); | 5616 | si_pcie_gart_fini(rdev); |
5389 | r600_vram_scratch_fini(rdev); | 5617 | r600_vram_scratch_fini(rdev); |
5390 | radeon_gem_fini(rdev); | 5618 | radeon_gem_fini(rdev); |
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 222877ba6cf5..8f2d7d4f9b28 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h | |||
@@ -28,6 +28,7 @@ | |||
28 | 28 | ||
29 | #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 | 29 | #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 |
30 | #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 | 30 | #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 |
31 | #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 | ||
31 | 32 | ||
32 | /* discrete uvd clocks */ | 33 | /* discrete uvd clocks */ |
33 | #define CG_UPLL_FUNC_CNTL 0x634 | 34 | #define CG_UPLL_FUNC_CNTL 0x634 |