diff options
author | Dave Airlie <airlied@redhat.com> | 2014-03-18 05:12:31 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2014-03-18 05:12:31 -0400 |
commit | bcc298bc924e0a990f853ba3e19f8b5a833cba7e (patch) | |
tree | 1c87c8f73dc41fd11ee3dacb1b91a7cc8b4798bb /drivers/gpu/drm/radeon | |
parent | 978c6050165bba52eab7ef3581d447eb215def77 (diff) | |
parent | dcb99fd9b08cfe1afe426af4d8d3cbc429190f15 (diff) |
Merge tag 'v3.14-rc7' into drm-next
Linux 3.14-rc7
Backmerge to help out Intel guys.
Diffstat (limited to 'drivers/gpu/drm/radeon')
28 files changed, 113 insertions, 71 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 0d19f4f94d5a..daa4dd375ab1 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -1774,6 +1774,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) | |||
1774 | return ATOM_PPLL1; | 1774 | return ATOM_PPLL1; |
1775 | DRM_ERROR("unable to allocate a PPLL\n"); | 1775 | DRM_ERROR("unable to allocate a PPLL\n"); |
1776 | return ATOM_PPLL_INVALID; | 1776 | return ATOM_PPLL_INVALID; |
1777 | } else if (ASIC_IS_DCE41(rdev)) { | ||
1778 | /* Don't share PLLs on DCE4.1 chips */ | ||
1779 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { | ||
1780 | if (rdev->clock.dp_extclk) | ||
1781 | /* skip PPLL programming if using ext clock */ | ||
1782 | return ATOM_PPLL_INVALID; | ||
1783 | } | ||
1784 | pll_in_use = radeon_get_pll_use_mask(crtc); | ||
1785 | if (!(pll_in_use & (1 << ATOM_PPLL1))) | ||
1786 | return ATOM_PPLL1; | ||
1787 | if (!(pll_in_use & (1 << ATOM_PPLL2))) | ||
1788 | return ATOM_PPLL2; | ||
1789 | DRM_ERROR("unable to allocate a PPLL\n"); | ||
1790 | return ATOM_PPLL_INVALID; | ||
1777 | } else if (ASIC_IS_DCE4(rdev)) { | 1791 | } else if (ASIC_IS_DCE4(rdev)) { |
1778 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, | 1792 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1779 | * depending on the asic: | 1793 | * depending on the asic: |
@@ -1801,7 +1815,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) | |||
1801 | if (pll != ATOM_PPLL_INVALID) | 1815 | if (pll != ATOM_PPLL_INVALID) |
1802 | return pll; | 1816 | return pll; |
1803 | } | 1817 | } |
1804 | } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */ | 1818 | } else { |
1805 | /* use the same PPLL for all monitors with the same clock */ | 1819 | /* use the same PPLL for all monitors with the same clock */ |
1806 | pll = radeon_get_shared_nondp_ppll(crtc); | 1820 | pll = radeon_get_shared_nondp_ppll(crtc); |
1807 | if (pll != ATOM_PPLL_INVALID) | 1821 | if (pll != ATOM_PPLL_INVALID) |
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index 2cec2ab02f80..607dc14d195e 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c | |||
@@ -1314,7 +1314,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
1314 | } | 1314 | } |
1315 | if (is_dp) | 1315 | if (is_dp) |
1316 | args.v5.ucLaneNum = dp_lane_count; | 1316 | args.v5.ucLaneNum = dp_lane_count; |
1317 | else if (radeon_encoder->pixel_clock > 165000) | 1317 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1318 | args.v5.ucLaneNum = 8; | 1318 | args.v5.ucLaneNum = 8; |
1319 | else | 1319 | else |
1320 | args.v5.ucLaneNum = 4; | 1320 | args.v5.ucLaneNum = 4; |
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 92e38b54efb9..0ae991d3289a 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
@@ -3047,7 +3047,7 @@ static u32 cik_create_bitmask(u32 bit_width) | |||
3047 | } | 3047 | } |
3048 | 3048 | ||
3049 | /** | 3049 | /** |
3050 | * cik_select_se_sh - select which SE, SH to address | 3050 | * cik_get_rb_disabled - computes the mask of disabled RBs |
3051 | * | 3051 | * |
3052 | * @rdev: radeon_device pointer | 3052 | * @rdev: radeon_device pointer |
3053 | * @max_rb_num: max RBs (render backends) for the asic | 3053 | * @max_rb_num: max RBs (render backends) for the asic |
@@ -4133,8 +4133,11 @@ static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable) | |||
4133 | { | 4133 | { |
4134 | if (enable) | 4134 | if (enable) |
4135 | WREG32(CP_MEC_CNTL, 0); | 4135 | WREG32(CP_MEC_CNTL, 0); |
4136 | else | 4136 | else { |
4137 | WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); | 4137 | WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); |
4138 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; | ||
4139 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; | ||
4140 | } | ||
4138 | udelay(50); | 4141 | udelay(50); |
4139 | } | 4142 | } |
4140 | 4143 | ||
@@ -7949,7 +7952,8 @@ int cik_resume(struct radeon_device *rdev) | |||
7949 | /* init golden registers */ | 7952 | /* init golden registers */ |
7950 | cik_init_golden_registers(rdev); | 7953 | cik_init_golden_registers(rdev); |
7951 | 7954 | ||
7952 | radeon_pm_resume(rdev); | 7955 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
7956 | radeon_pm_resume(rdev); | ||
7953 | 7957 | ||
7954 | rdev->accel_working = true; | 7958 | rdev->accel_working = true; |
7955 | r = cik_startup(rdev); | 7959 | r = cik_startup(rdev); |
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c index 00150ac49cd2..89b4afa5041c 100644 --- a/drivers/gpu/drm/radeon/cik_sdma.c +++ b/drivers/gpu/drm/radeon/cik_sdma.c | |||
@@ -264,6 +264,8 @@ static void cik_sdma_gfx_stop(struct radeon_device *rdev) | |||
264 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); | 264 | WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); |
265 | WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); | 265 | WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); |
266 | } | 266 | } |
267 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; | ||
268 | rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; | ||
267 | } | 269 | } |
268 | 270 | ||
269 | /** | 271 | /** |
@@ -291,6 +293,11 @@ void cik_sdma_enable(struct radeon_device *rdev, bool enable) | |||
291 | u32 me_cntl, reg_offset; | 293 | u32 me_cntl, reg_offset; |
292 | int i; | 294 | int i; |
293 | 295 | ||
296 | if (enable == false) { | ||
297 | cik_sdma_gfx_stop(rdev); | ||
298 | cik_sdma_rlc_stop(rdev); | ||
299 | } | ||
300 | |||
294 | for (i = 0; i < 2; i++) { | 301 | for (i = 0; i < 2; i++) { |
295 | if (i == 0) | 302 | if (i == 0) |
296 | reg_offset = SDMA0_REGISTER_OFFSET; | 303 | reg_offset = SDMA0_REGISTER_OFFSET; |
@@ -418,10 +425,6 @@ static int cik_sdma_load_microcode(struct radeon_device *rdev) | |||
418 | if (!rdev->sdma_fw) | 425 | if (!rdev->sdma_fw) |
419 | return -EINVAL; | 426 | return -EINVAL; |
420 | 427 | ||
421 | /* stop the gfx rings and rlc compute queues */ | ||
422 | cik_sdma_gfx_stop(rdev); | ||
423 | cik_sdma_rlc_stop(rdev); | ||
424 | |||
425 | /* halt the MEs */ | 428 | /* halt the MEs */ |
426 | cik_sdma_enable(rdev, false); | 429 | cik_sdma_enable(rdev, false); |
427 | 430 | ||
@@ -490,9 +493,6 @@ int cik_sdma_resume(struct radeon_device *rdev) | |||
490 | */ | 493 | */ |
491 | void cik_sdma_fini(struct radeon_device *rdev) | 494 | void cik_sdma_fini(struct radeon_device *rdev) |
492 | { | 495 | { |
493 | /* stop the gfx rings and rlc compute queues */ | ||
494 | cik_sdma_gfx_stop(rdev); | ||
495 | cik_sdma_rlc_stop(rdev); | ||
496 | /* halt the MEs */ | 496 | /* halt the MEs */ |
497 | cik_sdma_enable(rdev, false); | 497 | cik_sdma_enable(rdev, false); |
498 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); | 498 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); |
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c index 713a5d359901..94e858751994 100644 --- a/drivers/gpu/drm/radeon/dce6_afmt.c +++ b/drivers/gpu/drm/radeon/dce6_afmt.c | |||
@@ -278,13 +278,15 @@ static int dce6_audio_chipset_supported(struct radeon_device *rdev) | |||
278 | return !ASIC_IS_NODCE(rdev); | 278 | return !ASIC_IS_NODCE(rdev); |
279 | } | 279 | } |
280 | 280 | ||
281 | static void dce6_audio_enable(struct radeon_device *rdev, | 281 | void dce6_audio_enable(struct radeon_device *rdev, |
282 | struct r600_audio_pin *pin, | 282 | struct r600_audio_pin *pin, |
283 | bool enable) | 283 | bool enable) |
284 | { | 284 | { |
285 | if (!pin) | ||
286 | return; | ||
287 | |||
285 | WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, | 288 | WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, |
286 | AUDIO_ENABLED); | 289 | enable ? AUDIO_ENABLED : 0); |
287 | DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); | ||
288 | } | 290 | } |
289 | 291 | ||
290 | static const u32 pin_offsets[7] = | 292 | static const u32 pin_offsets[7] = |
@@ -323,7 +325,8 @@ int dce6_audio_init(struct radeon_device *rdev) | |||
323 | rdev->audio.pin[i].connected = false; | 325 | rdev->audio.pin[i].connected = false; |
324 | rdev->audio.pin[i].offset = pin_offsets[i]; | 326 | rdev->audio.pin[i].offset = pin_offsets[i]; |
325 | rdev->audio.pin[i].id = i; | 327 | rdev->audio.pin[i].id = i; |
326 | dce6_audio_enable(rdev, &rdev->audio.pin[i], true); | 328 | /* disable audio. it will be set up later */ |
329 | dce6_audio_enable(rdev, &rdev->audio.pin[i], false); | ||
327 | } | 330 | } |
328 | 331 | ||
329 | return 0; | 332 | return 0; |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index b1f1253e2ced..b406546440da 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -5295,7 +5295,8 @@ int evergreen_resume(struct radeon_device *rdev) | |||
5295 | /* init golden registers */ | 5295 | /* init golden registers */ |
5296 | evergreen_init_golden_registers(rdev); | 5296 | evergreen_init_golden_registers(rdev); |
5297 | 5297 | ||
5298 | radeon_pm_resume(rdev); | 5298 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
5299 | radeon_pm_resume(rdev); | ||
5299 | 5300 | ||
5300 | rdev->accel_working = true; | 5301 | rdev->accel_working = true; |
5301 | r = evergreen_startup(rdev); | 5302 | r = evergreen_startup(rdev); |
@@ -5471,9 +5472,9 @@ void evergreen_fini(struct radeon_device *rdev) | |||
5471 | radeon_wb_fini(rdev); | 5472 | radeon_wb_fini(rdev); |
5472 | radeon_ib_pool_fini(rdev); | 5473 | radeon_ib_pool_fini(rdev); |
5473 | radeon_irq_kms_fini(rdev); | 5474 | radeon_irq_kms_fini(rdev); |
5474 | evergreen_pcie_gart_fini(rdev); | ||
5475 | uvd_v1_0_fini(rdev); | 5475 | uvd_v1_0_fini(rdev); |
5476 | radeon_uvd_fini(rdev); | 5476 | radeon_uvd_fini(rdev); |
5477 | evergreen_pcie_gart_fini(rdev); | ||
5477 | r600_vram_scratch_fini(rdev); | 5478 | r600_vram_scratch_fini(rdev); |
5478 | radeon_gem_fini(rdev); | 5479 | radeon_gem_fini(rdev); |
5479 | radeon_fence_driver_fini(rdev); | 5480 | radeon_fence_driver_fini(rdev); |
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index 0c6d5cef4cf1..05b0c95813fd 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c | |||
@@ -306,6 +306,15 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode | |||
306 | return; | 306 | return; |
307 | offset = dig->afmt->offset; | 307 | offset = dig->afmt->offset; |
308 | 308 | ||
309 | /* disable audio prior to setting up hw */ | ||
310 | if (ASIC_IS_DCE6(rdev)) { | ||
311 | dig->afmt->pin = dce6_audio_get_pin(rdev); | ||
312 | dce6_audio_enable(rdev, dig->afmt->pin, false); | ||
313 | } else { | ||
314 | dig->afmt->pin = r600_audio_get_pin(rdev); | ||
315 | r600_audio_enable(rdev, dig->afmt->pin, false); | ||
316 | } | ||
317 | |||
309 | evergreen_audio_set_dto(encoder, mode->clock); | 318 | evergreen_audio_set_dto(encoder, mode->clock); |
310 | 319 | ||
311 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, | 320 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
@@ -409,12 +418,16 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode | |||
409 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); | 418 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); |
410 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); | 419 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); |
411 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); | 420 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); |
421 | |||
422 | /* enable audio after to setting up hw */ | ||
423 | if (ASIC_IS_DCE6(rdev)) | ||
424 | dce6_audio_enable(rdev, dig->afmt->pin, true); | ||
425 | else | ||
426 | r600_audio_enable(rdev, dig->afmt->pin, true); | ||
412 | } | 427 | } |
413 | 428 | ||
414 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) | 429 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
415 | { | 430 | { |
416 | struct drm_device *dev = encoder->dev; | ||
417 | struct radeon_device *rdev = dev->dev_private; | ||
418 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 431 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
419 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 432 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
420 | 433 | ||
@@ -427,15 +440,6 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) | |||
427 | if (!enable && !dig->afmt->enabled) | 440 | if (!enable && !dig->afmt->enabled) |
428 | return; | 441 | return; |
429 | 442 | ||
430 | if (enable) { | ||
431 | if (ASIC_IS_DCE6(rdev)) | ||
432 | dig->afmt->pin = dce6_audio_get_pin(rdev); | ||
433 | else | ||
434 | dig->afmt->pin = r600_audio_get_pin(rdev); | ||
435 | } else { | ||
436 | dig->afmt->pin = NULL; | ||
437 | } | ||
438 | |||
439 | dig->afmt->enabled = enable; | 443 | dig->afmt->enabled = enable; |
440 | 444 | ||
441 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", | 445 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
diff --git a/drivers/gpu/drm/radeon/evergreen_smc.h b/drivers/gpu/drm/radeon/evergreen_smc.h index 76ada8cfe902..3a03ba37d043 100644 --- a/drivers/gpu/drm/radeon/evergreen_smc.h +++ b/drivers/gpu/drm/radeon/evergreen_smc.h | |||
@@ -57,7 +57,7 @@ typedef struct SMC_Evergreen_MCRegisters SMC_Evergreen_MCRegisters; | |||
57 | 57 | ||
58 | #define EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION 0x100 | 58 | #define EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION 0x100 |
59 | 59 | ||
60 | #define EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters 0x0 | 60 | #define EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters 0x8 |
61 | #define EVERGREEN_SMC_FIRMWARE_HEADER_stateTable 0xC | 61 | #define EVERGREEN_SMC_FIRMWARE_HEADER_stateTable 0xC |
62 | #define EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20 | 62 | #define EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20 |
63 | 63 | ||
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 85168ecd216b..d246e043421a 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -2103,7 +2103,8 @@ int cayman_resume(struct radeon_device *rdev) | |||
2103 | /* init golden registers */ | 2103 | /* init golden registers */ |
2104 | ni_init_golden_registers(rdev); | 2104 | ni_init_golden_registers(rdev); |
2105 | 2105 | ||
2106 | radeon_pm_resume(rdev); | 2106 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
2107 | radeon_pm_resume(rdev); | ||
2107 | 2108 | ||
2108 | rdev->accel_working = true; | 2109 | rdev->accel_working = true; |
2109 | r = cayman_startup(rdev); | 2110 | r = cayman_startup(rdev); |
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 0a894aee7406..030f8e49c5ee 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -3939,8 +3939,6 @@ int r100_resume(struct radeon_device *rdev) | |||
3939 | /* Initialize surface registers */ | 3939 | /* Initialize surface registers */ |
3940 | radeon_surface_init(rdev); | 3940 | radeon_surface_init(rdev); |
3941 | 3941 | ||
3942 | radeon_pm_resume(rdev); | ||
3943 | |||
3944 | rdev->accel_working = true; | 3942 | rdev->accel_working = true; |
3945 | r = r100_startup(rdev); | 3943 | r = r100_startup(rdev); |
3946 | if (r) { | 3944 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 41cdf236ee9a..206caf9700b7 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -1430,8 +1430,6 @@ int r300_resume(struct radeon_device *rdev) | |||
1430 | /* Initialize surface registers */ | 1430 | /* Initialize surface registers */ |
1431 | radeon_surface_init(rdev); | 1431 | radeon_surface_init(rdev); |
1432 | 1432 | ||
1433 | radeon_pm_resume(rdev); | ||
1434 | |||
1435 | rdev->accel_working = true; | 1433 | rdev->accel_working = true; |
1436 | r = r300_startup(rdev); | 1434 | r = r300_startup(rdev); |
1437 | if (r) { | 1435 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 3768aab2710b..802b19220a21 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c | |||
@@ -325,8 +325,6 @@ int r420_resume(struct radeon_device *rdev) | |||
325 | /* Initialize surface registers */ | 325 | /* Initialize surface registers */ |
326 | radeon_surface_init(rdev); | 326 | radeon_surface_init(rdev); |
327 | 327 | ||
328 | radeon_pm_resume(rdev); | ||
329 | |||
330 | rdev->accel_working = true; | 328 | rdev->accel_working = true; |
331 | r = r420_startup(rdev); | 329 | r = r420_startup(rdev); |
332 | if (r) { | 330 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c index e209eb75024f..98d6053c36c6 100644 --- a/drivers/gpu/drm/radeon/r520.c +++ b/drivers/gpu/drm/radeon/r520.c | |||
@@ -240,8 +240,6 @@ int r520_resume(struct radeon_device *rdev) | |||
240 | /* Initialize surface registers */ | 240 | /* Initialize surface registers */ |
241 | radeon_surface_init(rdev); | 241 | radeon_surface_init(rdev); |
242 | 242 | ||
243 | radeon_pm_resume(rdev); | ||
244 | |||
245 | rdev->accel_working = true; | 243 | rdev->accel_working = true; |
246 | r = r520_startup(rdev); | 244 | r = r520_startup(rdev); |
247 | if (r) { | 245 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 0f4ab928a15a..6e887d004eba 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -2964,7 +2964,8 @@ int r600_resume(struct radeon_device *rdev) | |||
2964 | /* post card */ | 2964 | /* post card */ |
2965 | atom_asic_init(rdev->mode_info.atom_context); | 2965 | atom_asic_init(rdev->mode_info.atom_context); |
2966 | 2966 | ||
2967 | radeon_pm_resume(rdev); | 2967 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
2968 | radeon_pm_resume(rdev); | ||
2968 | 2969 | ||
2969 | rdev->accel_working = true; | 2970 | rdev->accel_working = true; |
2970 | r = r600_startup(rdev); | 2971 | r = r600_startup(rdev); |
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c index 47fc2b886979..bffac10c4296 100644 --- a/drivers/gpu/drm/radeon/r600_audio.c +++ b/drivers/gpu/drm/radeon/r600_audio.c | |||
@@ -142,12 +142,15 @@ void r600_audio_update_hdmi(struct work_struct *work) | |||
142 | } | 142 | } |
143 | 143 | ||
144 | /* enable the audio stream */ | 144 | /* enable the audio stream */ |
145 | static void r600_audio_enable(struct radeon_device *rdev, | 145 | void r600_audio_enable(struct radeon_device *rdev, |
146 | struct r600_audio_pin *pin, | 146 | struct r600_audio_pin *pin, |
147 | bool enable) | 147 | bool enable) |
148 | { | 148 | { |
149 | u32 value = 0; | 149 | u32 value = 0; |
150 | 150 | ||
151 | if (!pin) | ||
152 | return; | ||
153 | |||
151 | if (ASIC_IS_DCE4(rdev)) { | 154 | if (ASIC_IS_DCE4(rdev)) { |
152 | if (enable) { | 155 | if (enable) { |
153 | value |= 0x81000000; /* Required to enable audio */ | 156 | value |= 0x81000000; /* Required to enable audio */ |
@@ -158,7 +161,6 @@ static void r600_audio_enable(struct radeon_device *rdev, | |||
158 | WREG32_P(R600_AUDIO_ENABLE, | 161 | WREG32_P(R600_AUDIO_ENABLE, |
159 | enable ? 0x81000000 : 0x0, ~0x81000000); | 162 | enable ? 0x81000000 : 0x0, ~0x81000000); |
160 | } | 163 | } |
161 | DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); | ||
162 | } | 164 | } |
163 | 165 | ||
164 | /* | 166 | /* |
@@ -178,8 +180,8 @@ int r600_audio_init(struct radeon_device *rdev) | |||
178 | rdev->audio.pin[0].status_bits = 0; | 180 | rdev->audio.pin[0].status_bits = 0; |
179 | rdev->audio.pin[0].category_code = 0; | 181 | rdev->audio.pin[0].category_code = 0; |
180 | rdev->audio.pin[0].id = 0; | 182 | rdev->audio.pin[0].id = 0; |
181 | 183 | /* disable audio. it will be set up later */ | |
182 | r600_audio_enable(rdev, &rdev->audio.pin[0], true); | 184 | r600_audio_enable(rdev, &rdev->audio.pin[0], false); |
183 | 185 | ||
184 | return 0; | 186 | return 0; |
185 | } | 187 | } |
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 3016fc14f502..85a2bb28aed2 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c | |||
@@ -329,9 +329,6 @@ static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder) | |||
329 | u8 *sadb; | 329 | u8 *sadb; |
330 | int sad_count; | 330 | int sad_count; |
331 | 331 | ||
332 | /* XXX: setting this register causes hangs on some asics */ | ||
333 | return; | ||
334 | |||
335 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | 332 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
336 | if (connector->encoder == encoder) { | 333 | if (connector->encoder == encoder) { |
337 | radeon_connector = to_radeon_connector(connector); | 334 | radeon_connector = to_radeon_connector(connector); |
@@ -460,6 +457,10 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod | |||
460 | return; | 457 | return; |
461 | offset = dig->afmt->offset; | 458 | offset = dig->afmt->offset; |
462 | 459 | ||
460 | /* disable audio prior to setting up hw */ | ||
461 | dig->afmt->pin = r600_audio_get_pin(rdev); | ||
462 | r600_audio_enable(rdev, dig->afmt->pin, false); | ||
463 | |||
463 | r600_audio_set_dto(encoder, mode->clock); | 464 | r600_audio_set_dto(encoder, mode->clock); |
464 | 465 | ||
465 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, | 466 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
@@ -531,6 +532,9 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod | |||
531 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); | 532 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); |
532 | 533 | ||
533 | r600_hdmi_audio_workaround(encoder); | 534 | r600_hdmi_audio_workaround(encoder); |
535 | |||
536 | /* enable audio after to setting up hw */ | ||
537 | r600_audio_enable(rdev, dig->afmt->pin, true); | ||
534 | } | 538 | } |
535 | 539 | ||
536 | /* | 540 | /* |
@@ -651,11 +655,6 @@ void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) | |||
651 | if (!enable && !dig->afmt->enabled) | 655 | if (!enable && !dig->afmt->enabled) |
652 | return; | 656 | return; |
653 | 657 | ||
654 | if (enable) | ||
655 | dig->afmt->pin = r600_audio_get_pin(rdev); | ||
656 | else | ||
657 | dig->afmt->pin = NULL; | ||
658 | |||
659 | /* Older chipsets require setting HDMI and routing manually */ | 658 | /* Older chipsets require setting HDMI and routing manually */ |
660 | if (!ASIC_IS_DCE3(rdev)) { | 659 | if (!ASIC_IS_DCE3(rdev)) { |
661 | if (enable) | 660 | if (enable) |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 111deab2492a..f21db7a0b34d 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -2833,6 +2833,12 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev, | |||
2833 | void r600_audio_update_hdmi(struct work_struct *work); | 2833 | void r600_audio_update_hdmi(struct work_struct *work); |
2834 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); | 2834 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
2835 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); | 2835 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); |
2836 | void r600_audio_enable(struct radeon_device *rdev, | ||
2837 | struct r600_audio_pin *pin, | ||
2838 | bool enable); | ||
2839 | void dce6_audio_enable(struct radeon_device *rdev, | ||
2840 | struct r600_audio_pin *pin, | ||
2841 | bool enable); | ||
2836 | 2842 | ||
2837 | /* | 2843 | /* |
2838 | * R600 vram scratch functions | 2844 | * R600 vram scratch functions |
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c index 485848f889f5..fa9a9c02751e 100644 --- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c +++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c | |||
@@ -219,7 +219,8 @@ static int radeon_atpx_verify_interface(struct radeon_atpx *atpx) | |||
219 | memcpy(&output, info->buffer.pointer, size); | 219 | memcpy(&output, info->buffer.pointer, size); |
220 | 220 | ||
221 | /* TODO: check version? */ | 221 | /* TODO: check version? */ |
222 | printk("ATPX version %u\n", output.version); | 222 | printk("ATPX version %u, functions 0x%08x\n", |
223 | output.version, output.function_bits); | ||
223 | 224 | ||
224 | radeon_atpx_parse_functions(&atpx->functions, output.function_bits); | 225 | radeon_atpx_parse_functions(&atpx->functions, output.function_bits); |
225 | 226 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 7db44de90d6c..2e72dcd94b13 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -1517,13 +1517,16 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) | |||
1517 | if (r) | 1517 | if (r) |
1518 | DRM_ERROR("ib ring test failed (%d).\n", r); | 1518 | DRM_ERROR("ib ring test failed (%d).\n", r); |
1519 | 1519 | ||
1520 | if (rdev->pm.dpm_enabled) { | 1520 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
1521 | /* do dpm late init */ | 1521 | /* do dpm late init */ |
1522 | r = radeon_pm_late_init(rdev); | 1522 | r = radeon_pm_late_init(rdev); |
1523 | if (r) { | 1523 | if (r) { |
1524 | rdev->pm.dpm_enabled = false; | 1524 | rdev->pm.dpm_enabled = false; |
1525 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); | 1525 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); |
1526 | } | 1526 | } |
1527 | } else { | ||
1528 | /* resume old pm late */ | ||
1529 | radeon_pm_resume(rdev); | ||
1527 | } | 1530 | } |
1528 | 1531 | ||
1529 | radeon_restore_bios_scratch_regs(rdev); | 1532 | radeon_restore_bios_scratch_regs(rdev); |
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index 37b1deacb5b1..6f1dfac17507 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c | |||
@@ -33,6 +33,13 @@ | |||
33 | #include <linux/vga_switcheroo.h> | 33 | #include <linux/vga_switcheroo.h> |
34 | #include <linux/slab.h> | 34 | #include <linux/slab.h> |
35 | #include <linux/pm_runtime.h> | 35 | #include <linux/pm_runtime.h> |
36 | |||
37 | #if defined(CONFIG_VGA_SWITCHEROO) | ||
38 | bool radeon_is_px(void); | ||
39 | #else | ||
40 | static inline bool radeon_is_px(void) { return false; } | ||
41 | #endif | ||
42 | |||
36 | /** | 43 | /** |
37 | * radeon_driver_unload_kms - Main unload function for KMS. | 44 | * radeon_driver_unload_kms - Main unload function for KMS. |
38 | * | 45 | * |
@@ -130,7 +137,8 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) | |||
130 | "Error during ACPI methods call\n"); | 137 | "Error during ACPI methods call\n"); |
131 | } | 138 | } |
132 | 139 | ||
133 | if (radeon_runtime_pm != 0) { | 140 | if ((radeon_runtime_pm == 1) || |
141 | ((radeon_runtime_pm == -1) && radeon_is_px())) { | ||
134 | pm_runtime_use_autosuspend(dev->dev); | 142 | pm_runtime_use_autosuspend(dev->dev); |
135 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | 143 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); |
136 | pm_runtime_set_active(dev->dev); | 144 | pm_runtime_set_active(dev->dev); |
@@ -567,6 +575,10 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |||
567 | if (r) | 575 | if (r) |
568 | return r; | 576 | return r; |
569 | 577 | ||
578 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); | ||
579 | if (r) | ||
580 | return r; | ||
581 | |||
570 | /* map the ib pool buffer read only into | 582 | /* map the ib pool buffer read only into |
571 | * virtual address space */ | 583 | * virtual address space */ |
572 | bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, | 584 | bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, |
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 60dfce889ecf..d46b33a1cbcd 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c | |||
@@ -720,6 +720,9 @@ int radeon_ttm_init(struct radeon_device *rdev) | |||
720 | DRM_ERROR("Failed initializing VRAM heap.\n"); | 720 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
721 | return r; | 721 | return r; |
722 | } | 722 | } |
723 | /* Change the size here instead of the init above so only lpfn is affected */ | ||
724 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | ||
725 | |||
723 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, | 726 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
724 | RADEON_GEM_DOMAIN_VRAM, | 727 | RADEON_GEM_DOMAIN_VRAM, |
725 | NULL, &rdev->stollen_vga_memory); | 728 | NULL, &rdev->stollen_vga_memory); |
@@ -941,7 +944,7 @@ static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, | |||
941 | while (size) { | 944 | while (size) { |
942 | loff_t p = *pos / PAGE_SIZE; | 945 | loff_t p = *pos / PAGE_SIZE; |
943 | unsigned off = *pos & ~PAGE_MASK; | 946 | unsigned off = *pos & ~PAGE_MASK; |
944 | ssize_t cur_size = min(size, PAGE_SIZE - off); | 947 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); |
945 | struct page *page; | 948 | struct page *page; |
946 | void *ptr; | 949 | void *ptr; |
947 | 950 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index 6a2e3ff68374..5748bdaeacce 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c | |||
@@ -171,6 +171,8 @@ void radeon_uvd_fini(struct radeon_device *rdev) | |||
171 | 171 | ||
172 | radeon_bo_unref(&rdev->uvd.vcpu_bo); | 172 | radeon_bo_unref(&rdev->uvd.vcpu_bo); |
173 | 173 | ||
174 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]); | ||
175 | |||
174 | release_firmware(rdev->uvd_fw); | 176 | release_firmware(rdev->uvd_fw); |
175 | } | 177 | } |
176 | 178 | ||
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index b5c2369cda2f..130d5cc50d43 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c | |||
@@ -474,8 +474,6 @@ int rs400_resume(struct radeon_device *rdev) | |||
474 | /* Initialize surface registers */ | 474 | /* Initialize surface registers */ |
475 | radeon_surface_init(rdev); | 475 | radeon_surface_init(rdev); |
476 | 476 | ||
477 | radeon_pm_resume(rdev); | ||
478 | |||
479 | rdev->accel_working = true; | 477 | rdev->accel_working = true; |
480 | r = rs400_startup(rdev); | 478 | r = rs400_startup(rdev); |
481 | if (r) { | 479 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index fdcde7693032..72d3616de08e 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
@@ -1048,8 +1048,6 @@ int rs600_resume(struct radeon_device *rdev) | |||
1048 | /* Initialize surface registers */ | 1048 | /* Initialize surface registers */ |
1049 | radeon_surface_init(rdev); | 1049 | radeon_surface_init(rdev); |
1050 | 1050 | ||
1051 | radeon_pm_resume(rdev); | ||
1052 | |||
1053 | rdev->accel_working = true; | 1051 | rdev->accel_working = true; |
1054 | r = rs600_startup(rdev); | 1052 | r = rs600_startup(rdev); |
1055 | if (r) { | 1053 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index 35950738bd5e..3462b64369bf 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c | |||
@@ -756,8 +756,6 @@ int rs690_resume(struct radeon_device *rdev) | |||
756 | /* Initialize surface registers */ | 756 | /* Initialize surface registers */ |
757 | radeon_surface_init(rdev); | 757 | radeon_surface_init(rdev); |
758 | 758 | ||
759 | radeon_pm_resume(rdev); | ||
760 | |||
761 | rdev->accel_working = true; | 759 | rdev->accel_working = true; |
762 | r = rs690_startup(rdev); | 760 | r = rs690_startup(rdev); |
763 | if (r) { | 761 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 98e8138ff779..237dd29d9f1c 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
@@ -586,8 +586,6 @@ int rv515_resume(struct radeon_device *rdev) | |||
586 | /* Initialize surface registers */ | 586 | /* Initialize surface registers */ |
587 | radeon_surface_init(rdev); | 587 | radeon_surface_init(rdev); |
588 | 588 | ||
589 | radeon_pm_resume(rdev); | ||
590 | |||
591 | rdev->accel_working = true; | 589 | rdev->accel_working = true; |
592 | r = rv515_startup(rdev); | 590 | r = rv515_startup(rdev); |
593 | if (r) { | 591 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 6c772e58c784..fef310773aad 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -1811,7 +1811,8 @@ int rv770_resume(struct radeon_device *rdev) | |||
1811 | /* init golden registers */ | 1811 | /* init golden registers */ |
1812 | rv770_init_golden_registers(rdev); | 1812 | rv770_init_golden_registers(rdev); |
1813 | 1813 | ||
1814 | radeon_pm_resume(rdev); | 1814 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
1815 | radeon_pm_resume(rdev); | ||
1815 | 1816 | ||
1816 | rdev->accel_working = true; | 1817 | rdev->accel_working = true; |
1817 | r = rv770_startup(rdev); | 1818 | r = rv770_startup(rdev); |
@@ -1955,9 +1956,9 @@ void rv770_fini(struct radeon_device *rdev) | |||
1955 | radeon_wb_fini(rdev); | 1956 | radeon_wb_fini(rdev); |
1956 | radeon_ib_pool_fini(rdev); | 1957 | radeon_ib_pool_fini(rdev); |
1957 | radeon_irq_kms_fini(rdev); | 1958 | radeon_irq_kms_fini(rdev); |
1958 | rv770_pcie_gart_fini(rdev); | ||
1959 | uvd_v1_0_fini(rdev); | 1959 | uvd_v1_0_fini(rdev); |
1960 | radeon_uvd_fini(rdev); | 1960 | radeon_uvd_fini(rdev); |
1961 | rv770_pcie_gart_fini(rdev); | ||
1961 | r600_vram_scratch_fini(rdev); | 1962 | r600_vram_scratch_fini(rdev); |
1962 | radeon_gem_fini(rdev); | 1963 | radeon_gem_fini(rdev); |
1963 | radeon_fence_driver_fini(rdev); | 1964 | radeon_fence_driver_fini(rdev); |
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 8008cb8d5324..d589475fe9e6 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -6610,7 +6610,8 @@ int si_resume(struct radeon_device *rdev) | |||
6610 | /* init golden registers */ | 6610 | /* init golden registers */ |
6611 | si_init_golden_registers(rdev); | 6611 | si_init_golden_registers(rdev); |
6612 | 6612 | ||
6613 | radeon_pm_resume(rdev); | 6613 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
6614 | radeon_pm_resume(rdev); | ||
6614 | 6615 | ||
6615 | rdev->accel_working = true; | 6616 | rdev->accel_working = true; |
6616 | r = si_startup(rdev); | 6617 | r = si_startup(rdev); |