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authorJerome Glisse <jglisse@redhat.com>2010-02-10 17:30:05 -0500
committerDave Airlie <airlied@redhat.com>2010-02-11 04:03:45 -0500
commit961fb597c17e2e4f55407d56b7211c188ab41eff (patch)
tree14ec50b2d934c3dafac313b5adf53df1e32be107 /drivers/gpu/drm/radeon
parent4c36b678a23d33b82d614afe4f958a9d244ede5d (diff)
drm/radeon/kms: r600/r700 command stream checker
This patch add cs checker to r600/r700 hw. Command stream checking will rewrite some of the cs value in order to restrict GPU access to BO size. This doesn't break old userspace but just enforce safe value. It should break any things that was using the r600/r700 cs ioctl to do forbidden things (malicious software), though we are not aware of such things. Here is the list of thing we check : - enforcing resource size - enforcing color buffer slice tile max, will restrict cb access - enforcing db buffer slice tile max, will restrict db access We don't check for shader bigger than the BO in which they are supposed to be, such use would lead to GPU lockup and is harmless from security POV, as far as we can tell (note that even checking for this wouldn't prevent someone to write bogus shader that lead to lockup). This patch has received as much testing as humanly possible with old userspace to check that it didn't break such configuration. However not all the applications out there were tested, thus it might broke some odd, rare applications. [airlied: fix rules for cs checker for parallel builds] Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/Makefile5
-rw-r--r--drivers/gpu/drm/radeon/r600.c6
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c31
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c826
-rw-r--r--drivers/gpu/drm/radeon/r600d.h467
-rw-r--r--drivers/gpu/drm/radeon/radeon.h6
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h3
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r600837
-rw-r--r--drivers/gpu/drm/radeon/rv770.c6
9 files changed, 2058 insertions, 129 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 83c59079193b..b46f115d1c25 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -30,6 +30,9 @@ $(obj)/r420_reg_safe.h: $(src)/reg_srcs/r420 $(obj)/mkregtable
30$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable 30$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
31 $(call if_changed,mkregtable) 31 $(call if_changed,mkregtable)
32 32
33$(obj)/r600_reg_safe.h: $(src)/reg_srcs/r600 $(obj)/mkregtable
34 $(call if_changed,mkregtable)
35
33$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h 36$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h
34 37
35$(obj)/r200.o: $(obj)/r200_reg_safe.h 38$(obj)/r200.o: $(obj)/r200_reg_safe.h
@@ -42,6 +45,8 @@ $(obj)/r420.o: $(obj)/r420_reg_safe.h
42 45
43$(obj)/rs600.o: $(obj)/rs600_reg_safe.h 46$(obj)/rs600.o: $(obj)/rs600_reg_safe.h
44 47
48$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h
49
45radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ 50radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
46 radeon_irq.o r300_cmdbuf.o r600_cp.o 51 radeon_irq.o r300_cmdbuf.o r600_cp.o
47# add KMS driver 52# add KMS driver
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 05769fa77a21..c9723daee357 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1077,21 +1077,27 @@ void r600_gpu_init(struct radeon_device *rdev)
1077 switch (rdev->config.r600.max_tile_pipes) { 1077 switch (rdev->config.r600.max_tile_pipes) {
1078 case 1: 1078 case 1:
1079 tiling_config |= PIPE_TILING(0); 1079 tiling_config |= PIPE_TILING(0);
1080 rdev->config.r600.tiling_npipes = 1;
1080 break; 1081 break;
1081 case 2: 1082 case 2:
1082 tiling_config |= PIPE_TILING(1); 1083 tiling_config |= PIPE_TILING(1);
1084 rdev->config.r600.tiling_npipes = 2;
1083 break; 1085 break;
1084 case 4: 1086 case 4:
1085 tiling_config |= PIPE_TILING(2); 1087 tiling_config |= PIPE_TILING(2);
1088 rdev->config.r600.tiling_npipes = 4;
1086 break; 1089 break;
1087 case 8: 1090 case 8:
1088 tiling_config |= PIPE_TILING(3); 1091 tiling_config |= PIPE_TILING(3);
1092 rdev->config.r600.tiling_npipes = 8;
1089 break; 1093 break;
1090 default: 1094 default:
1091 break; 1095 break;
1092 } 1096 }
1097 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1093 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1098 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1094 tiling_config |= GROUP_SIZE(0); 1099 tiling_config |= GROUP_SIZE(0);
1100 rdev->config.r600.tiling_group_size = 256;
1095 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1101 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1096 if (tmp > 3) { 1102 if (tmp > 3) {
1097 tiling_config |= ROW_TILING(3); 1103 tiling_config |= ROW_TILING(3);
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 6d5a711c2e91..d9712a1023b1 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -873,6 +873,17 @@ static void r600_gfx_init(struct drm_device *dev,
873 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 873 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
874 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 874 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
875 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 875 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
876 if (gb_tiling_config & 0xc0) {
877 dev_priv->r600_group_size = 512;
878 } else {
879 dev_priv->r600_group_size = 256;
880 }
881 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
882 if (gb_tiling_config & 0x30) {
883 dev_priv->r600_nbanks = 8;
884 } else {
885 dev_priv->r600_nbanks = 4;
886 }
876 887
877 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 888 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
878 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 889 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
@@ -1444,6 +1455,17 @@ static void r700_gfx_init(struct drm_device *dev,
1444 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1455 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1445 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1456 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1446 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1457 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1458 if (gb_tiling_config & 0xc0) {
1459 dev_priv->r600_group_size = 512;
1460 } else {
1461 dev_priv->r600_group_size = 256;
1462 }
1463 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
1464 if (gb_tiling_config & 0x30) {
1465 dev_priv->r600_nbanks = 8;
1466 } else {
1467 dev_priv->r600_nbanks = 4;
1468 }
1447 1469
1448 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1470 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1449 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1471 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
@@ -2526,3 +2548,12 @@ out:
2526 mutex_unlock(&dev_priv->cs_mutex); 2548 mutex_unlock(&dev_priv->cs_mutex);
2527 return r; 2549 return r;
2528} 2550}
2551
2552void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size)
2553{
2554 struct drm_radeon_private *dev_priv = dev->dev_private;
2555
2556 *npipes = dev_priv->r600_npipes;
2557 *nbanks = dev_priv->r600_nbanks;
2558 *group_size = dev_priv->r600_group_size;
2559}
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index e4c45ec16507..ac67d6488a95 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -28,6 +28,7 @@
28#include "drmP.h" 28#include "drmP.h"
29#include "radeon.h" 29#include "radeon.h"
30#include "r600d.h" 30#include "r600d.h"
31#include "r600_reg_safe.h"
31 32
32static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, 33static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
33 struct radeon_cs_reloc **cs_reloc); 34 struct radeon_cs_reloc **cs_reloc);
@@ -35,11 +36,313 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc); 36 struct radeon_cs_reloc **cs_reloc);
36typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); 37typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
37static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; 38static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
39extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
40
38 41
39struct r600_cs_track { 42struct r600_cs_track {
40 u32 cb_color0_base_last; 43 /* configuration we miror so that we use same code btw kms/ums */
44 u32 group_size;
45 u32 nbanks;
46 u32 npipes;
47 /* value we track */
48 u32 nsamples;
49 u32 cb_color_base_last[8];
50 struct radeon_bo *cb_color_bo[8];
51 u32 cb_color_bo_offset[8];
52 struct radeon_bo *cb_color_frag_bo[8];
53 struct radeon_bo *cb_color_tile_bo[8];
54 u32 cb_color_info[8];
55 u32 cb_color_size_idx[8];
56 u32 cb_target_mask;
57 u32 cb_shader_mask;
58 u32 cb_color_size[8];
59 u32 vgt_strmout_en;
60 u32 vgt_strmout_buffer_en;
61 u32 db_depth_control;
62 u32 db_depth_info;
63 u32 db_depth_size_idx;
64 u32 db_depth_view;
65 u32 db_depth_size;
66 u32 db_offset;
67 struct radeon_bo *db_bo;
41}; 68};
42 69
70static inline int r600_bpe_from_format(u32 *bpe, u32 format)
71{
72 switch (format) {
73 case V_038004_COLOR_8:
74 case V_038004_COLOR_4_4:
75 case V_038004_COLOR_3_3_2:
76 case V_038004_FMT_1:
77 *bpe = 1;
78 break;
79 case V_038004_COLOR_16:
80 case V_038004_COLOR_16_FLOAT:
81 case V_038004_COLOR_8_8:
82 case V_038004_COLOR_5_6_5:
83 case V_038004_COLOR_6_5_5:
84 case V_038004_COLOR_1_5_5_5:
85 case V_038004_COLOR_4_4_4_4:
86 case V_038004_COLOR_5_5_5_1:
87 *bpe = 2;
88 break;
89 case V_038004_FMT_8_8_8:
90 *bpe = 3;
91 break;
92 case V_038004_COLOR_32:
93 case V_038004_COLOR_32_FLOAT:
94 case V_038004_COLOR_16_16:
95 case V_038004_COLOR_16_16_FLOAT:
96 case V_038004_COLOR_8_24:
97 case V_038004_COLOR_8_24_FLOAT:
98 case V_038004_COLOR_24_8:
99 case V_038004_COLOR_24_8_FLOAT:
100 case V_038004_COLOR_10_11_11:
101 case V_038004_COLOR_10_11_11_FLOAT:
102 case V_038004_COLOR_11_11_10:
103 case V_038004_COLOR_11_11_10_FLOAT:
104 case V_038004_COLOR_2_10_10_10:
105 case V_038004_COLOR_8_8_8_8:
106 case V_038004_COLOR_10_10_10_2:
107 case V_038004_FMT_5_9_9_9_SHAREDEXP:
108 case V_038004_FMT_32_AS_8:
109 case V_038004_FMT_32_AS_8_8:
110 *bpe = 4;
111 break;
112 case V_038004_COLOR_X24_8_32_FLOAT:
113 case V_038004_COLOR_32_32:
114 case V_038004_COLOR_32_32_FLOAT:
115 case V_038004_COLOR_16_16_16_16:
116 case V_038004_COLOR_16_16_16_16_FLOAT:
117 *bpe = 8;
118 break;
119 case V_038004_FMT_16_16_16:
120 case V_038004_FMT_16_16_16_FLOAT:
121 *bpe = 6;
122 break;
123 case V_038004_FMT_32_32_32:
124 case V_038004_FMT_32_32_32_FLOAT:
125 *bpe = 12;
126 break;
127 case V_038004_COLOR_32_32_32_32:
128 case V_038004_COLOR_32_32_32_32_FLOAT:
129 *bpe = 16;
130 break;
131 case V_038004_FMT_GB_GR:
132 case V_038004_FMT_BG_RG:
133 case V_038004_COLOR_INVALID:
134 *bpe = 16;
135 return -EINVAL;
136 }
137 return 0;
138}
139
140static void r600_cs_track_init(struct r600_cs_track *track)
141{
142 int i;
143
144 for (i = 0; i < 8; i++) {
145 track->cb_color_base_last[i] = 0;
146 track->cb_color_size[i] = 0;
147 track->cb_color_size_idx[i] = 0;
148 track->cb_color_info[i] = 0;
149 track->cb_color_bo[i] = NULL;
150 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
151 }
152 track->cb_target_mask = 0xFFFFFFFF;
153 track->cb_shader_mask = 0xFFFFFFFF;
154 track->db_bo = NULL;
155 /* assume the biggest format and that htile is enabled */
156 track->db_depth_info = 7 | (1 << 25);
157 track->db_depth_view = 0xFFFFC000;
158 track->db_depth_size = 0xFFFFFFFF;
159 track->db_depth_size_idx = 0;
160 track->db_depth_control = 0xFFFFFFFF;
161}
162
163static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
164{
165 struct r600_cs_track *track = p->track;
166 u32 bpe, pitch, slice_tile_max, size, tmp, height;
167 volatile u32 *ib = p->ib->ptr;
168
169 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
170 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
171 return -EINVAL;
172 }
173 size = radeon_bo_size(track->cb_color_bo[i]);
174 if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) {
175 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
176 __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]),
177 i, track->cb_color_info[i]);
178 return -EINVAL;
179 }
180 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) << 3;
181 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
182 if (!pitch) {
183 dev_warn(p->dev, "%s:%d cb pitch (%d) for %d invalid (0x%08X)\n",
184 __func__, __LINE__, pitch, i, track->cb_color_size[i]);
185 return -EINVAL;
186 }
187 height = size / (pitch * bpe);
188 if (height > 8192)
189 height = 8192;
190 switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) {
191 case V_0280A0_ARRAY_LINEAR_GENERAL:
192 case V_0280A0_ARRAY_LINEAR_ALIGNED:
193 if (pitch & 0x3f) {
194 dev_warn(p->dev, "%s:%d cb pitch (%d x %d = %d) invalid\n",
195 __func__, __LINE__, pitch, bpe, pitch * bpe);
196 return -EINVAL;
197 }
198 if ((pitch * bpe) & (track->group_size - 1)) {
199 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
200 __func__, __LINE__, pitch);
201 return -EINVAL;
202 }
203 break;
204 case V_0280A0_ARRAY_1D_TILED_THIN1:
205 if ((pitch * 8 * bpe * track->nsamples) & (track->group_size - 1)) {
206 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
207 __func__, __LINE__, pitch);
208 return -EINVAL;
209 }
210 height &= ~0x7;
211 if (!height)
212 height = 8;
213 break;
214 case V_0280A0_ARRAY_2D_TILED_THIN1:
215 if (pitch & ((8 * track->nbanks) - 1)) {
216 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
217 __func__, __LINE__, pitch);
218 return -EINVAL;
219 }
220 tmp = pitch * 8 * bpe * track->nsamples;
221 tmp = tmp / track->nbanks;
222 if (tmp & (track->group_size - 1)) {
223 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
224 __func__, __LINE__, pitch);
225 return -EINVAL;
226 }
227 height &= ~((16 * track->npipes) - 1);
228 if (!height)
229 height = 16 * track->npipes;
230 break;
231 default:
232 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
233 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
234 track->cb_color_info[i]);
235 return -EINVAL;
236 }
237 /* check offset */
238 tmp = height * pitch;
239 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
240 dev_warn(p->dev, "%s offset[%d] %d to big\n", __func__, i, track->cb_color_bo_offset[i]);
241 return -EINVAL;
242 }
243 /* limit max tile */
244 tmp = (height * pitch) >> 6;
245 if (tmp < slice_tile_max)
246 slice_tile_max = tmp;
247 tmp = S_028060_PITCH_TILE_MAX((pitch >> 3) - 1) |
248 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
249 ib[track->cb_color_size_idx[i]] = tmp;
250 return 0;
251}
252
253static int r600_cs_track_check(struct radeon_cs_parser *p)
254{
255 struct r600_cs_track *track = p->track;
256 u32 tmp;
257 int r, i;
258 volatile u32 *ib = p->ib->ptr;
259
260 /* on legacy kernel we don't perform advanced check */
261 if (p->rdev == NULL)
262 return 0;
263 /* we don't support out buffer yet */
264 if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
265 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
266 return -EINVAL;
267 }
268 /* check that we have a cb for each enabled target, we don't check
269 * shader_mask because it seems mesa isn't always setting it :(
270 */
271 tmp = track->cb_target_mask;
272 for (i = 0; i < 8; i++) {
273 if ((tmp >> (i * 4)) & 0xF) {
274 /* at least one component is enabled */
275 if (track->cb_color_bo[i] == NULL) {
276 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
277 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
278 return -EINVAL;
279 }
280 /* perform rewrite of CB_COLOR[0-7]_SIZE */
281 r = r600_cs_track_validate_cb(p, i);
282 if (r)
283 return r;
284 }
285 }
286 /* Check depth buffer */
287 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
288 G_028800_Z_ENABLE(track->db_depth_control)) {
289 u32 nviews, bpe, ntiles;
290 if (track->db_bo == NULL) {
291 dev_warn(p->dev, "z/stencil with no depth buffer\n");
292 return -EINVAL;
293 }
294 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
295 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
296 return -EINVAL;
297 }
298 switch (G_028010_FORMAT(track->db_depth_info)) {
299 case V_028010_DEPTH_16:
300 bpe = 2;
301 break;
302 case V_028010_DEPTH_X8_24:
303 case V_028010_DEPTH_8_24:
304 case V_028010_DEPTH_X8_24_FLOAT:
305 case V_028010_DEPTH_8_24_FLOAT:
306 case V_028010_DEPTH_32_FLOAT:
307 bpe = 4;
308 break;
309 case V_028010_DEPTH_X24_8_32_FLOAT:
310 bpe = 8;
311 break;
312 default:
313 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
314 return -EINVAL;
315 }
316 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
317 if (!track->db_depth_size_idx) {
318 dev_warn(p->dev, "z/stencil buffer size not set\n");
319 return -EINVAL;
320 }
321 printk_once(KERN_WARNING "You have old & broken userspace please consider updating mesa\n");
322 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
323 tmp = (tmp / bpe) >> 6;
324 if (!tmp) {
325 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
326 track->db_depth_size, bpe, track->db_offset,
327 radeon_bo_size(track->db_bo));
328 return -EINVAL;
329 }
330 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
331 } else {
332 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
333 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
334 tmp = ntiles * bpe * 64 * nviews;
335 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
336 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n",
337 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
338 radeon_bo_size(track->db_bo));
339 return -EINVAL;
340 }
341 }
342 }
343 return 0;
344}
345
43/** 346/**
44 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet 347 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
45 * @parser: parser structure holding parsing context. 348 * @parser: parser structure holding parsing context.
@@ -359,6 +662,334 @@ static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
359 return 0; 662 return 0;
360} 663}
361 664
665/**
666 * r600_cs_check_reg() - check if register is authorized or not
667 * @parser: parser structure holding parsing context
668 * @reg: register we are testing
669 * @idx: index into the cs buffer
670 *
671 * This function will test against r600_reg_safe_bm and return 0
672 * if register is safe. If register is not flag as safe this function
673 * will test it against a list of register needind special handling.
674 */
675static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
676{
677 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
678 struct radeon_cs_reloc *reloc;
679 u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
680 u32 m, i, tmp, *ib;
681 int r;
682
683 i = (reg >> 7);
684 if (i > last_reg) {
685 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
686 return -EINVAL;
687 }
688 m = 1 << ((reg >> 2) & 31);
689 if (!(r600_reg_safe_bm[i] & m))
690 return 0;
691 ib = p->ib->ptr;
692 switch (reg) {
693 /* force following reg to 0 in an attemp to disable out buffer
694 * which will need us to better understand how it works to perform
695 * security check on it (Jerome)
696 */
697 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
698 case R_008C44_SQ_ESGS_RING_SIZE:
699 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
700 case R_008C54_SQ_ESTMP_RING_SIZE:
701 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
702 case R_008C74_SQ_FBUF_RING_SIZE:
703 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
704 case R_008C5C_SQ_GSTMP_RING_SIZE:
705 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
706 case R_008C4C_SQ_GSVS_RING_SIZE:
707 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
708 case R_008C6C_SQ_PSTMP_RING_SIZE:
709 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
710 case R_008C7C_SQ_REDUC_RING_SIZE:
711 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
712 case R_008C64_SQ_VSTMP_RING_SIZE:
713 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
714 /* get value to populate the IB don't remove */
715 tmp =radeon_get_ib_value(p, idx);
716 ib[idx] = 0;
717 break;
718 case R_028800_DB_DEPTH_CONTROL:
719 track->db_depth_control = radeon_get_ib_value(p, idx);
720 break;
721 case R_028010_DB_DEPTH_INFO:
722 track->db_depth_info = radeon_get_ib_value(p, idx);
723 break;
724 case R_028004_DB_DEPTH_VIEW:
725 track->db_depth_view = radeon_get_ib_value(p, idx);
726 break;
727 case R_028000_DB_DEPTH_SIZE:
728 track->db_depth_size = radeon_get_ib_value(p, idx);
729 track->db_depth_size_idx = idx;
730 break;
731 case R_028AB0_VGT_STRMOUT_EN:
732 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
733 break;
734 case R_028B20_VGT_STRMOUT_BUFFER_EN:
735 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
736 break;
737 case R_028238_CB_TARGET_MASK:
738 track->cb_target_mask = radeon_get_ib_value(p, idx);
739 break;
740 case R_02823C_CB_SHADER_MASK:
741 track->cb_shader_mask = radeon_get_ib_value(p, idx);
742 break;
743 case R_028C04_PA_SC_AA_CONFIG:
744 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
745 track->nsamples = 1 << tmp;
746 break;
747 case R_0280A0_CB_COLOR0_INFO:
748 case R_0280A4_CB_COLOR1_INFO:
749 case R_0280A8_CB_COLOR2_INFO:
750 case R_0280AC_CB_COLOR3_INFO:
751 case R_0280B0_CB_COLOR4_INFO:
752 case R_0280B4_CB_COLOR5_INFO:
753 case R_0280B8_CB_COLOR6_INFO:
754 case R_0280BC_CB_COLOR7_INFO:
755 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
756 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
757 break;
758 case R_028060_CB_COLOR0_SIZE:
759 case R_028064_CB_COLOR1_SIZE:
760 case R_028068_CB_COLOR2_SIZE:
761 case R_02806C_CB_COLOR3_SIZE:
762 case R_028070_CB_COLOR4_SIZE:
763 case R_028074_CB_COLOR5_SIZE:
764 case R_028078_CB_COLOR6_SIZE:
765 case R_02807C_CB_COLOR7_SIZE:
766 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
767 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
768 track->cb_color_size_idx[tmp] = idx;
769 break;
770 /* This register were added late, there is userspace
771 * which does provide relocation for those but set
772 * 0 offset. In order to avoid breaking old userspace
773 * we detect this and set address to point to last
774 * CB_COLOR0_BASE, note that if userspace doesn't set
775 * CB_COLOR0_BASE before this register we will report
776 * error. Old userspace always set CB_COLOR0_BASE
777 * before any of this.
778 */
779 case R_0280E0_CB_COLOR0_FRAG:
780 case R_0280E4_CB_COLOR1_FRAG:
781 case R_0280E8_CB_COLOR2_FRAG:
782 case R_0280EC_CB_COLOR3_FRAG:
783 case R_0280F0_CB_COLOR4_FRAG:
784 case R_0280F4_CB_COLOR5_FRAG:
785 case R_0280F8_CB_COLOR6_FRAG:
786 case R_0280FC_CB_COLOR7_FRAG:
787 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
788 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
789 if (!track->cb_color_base_last[tmp]) {
790 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
791 return -EINVAL;
792 }
793 ib[idx] = track->cb_color_base_last[tmp];
794 printk_once(KERN_WARNING "You have old & broken userspace "
795 "please consider updating mesa & xf86-video-ati\n");
796 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
797 } else {
798 r = r600_cs_packet_next_reloc(p, &reloc);
799 if (r) {
800 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
801 return -EINVAL;
802 }
803 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
804 track->cb_color_frag_bo[tmp] = reloc->robj;
805 }
806 break;
807 case R_0280C0_CB_COLOR0_TILE:
808 case R_0280C4_CB_COLOR1_TILE:
809 case R_0280C8_CB_COLOR2_TILE:
810 case R_0280CC_CB_COLOR3_TILE:
811 case R_0280D0_CB_COLOR4_TILE:
812 case R_0280D4_CB_COLOR5_TILE:
813 case R_0280D8_CB_COLOR6_TILE:
814 case R_0280DC_CB_COLOR7_TILE:
815 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
816 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
817 if (!track->cb_color_base_last[tmp]) {
818 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
819 return -EINVAL;
820 }
821 ib[idx] = track->cb_color_base_last[tmp];
822 printk_once(KERN_WARNING "You have old & broken userspace "
823 "please consider updating mesa & xf86-video-ati\n");
824 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
825 } else {
826 r = r600_cs_packet_next_reloc(p, &reloc);
827 if (r) {
828 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
829 return -EINVAL;
830 }
831 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
832 track->cb_color_tile_bo[tmp] = reloc->robj;
833 }
834 break;
835 case CB_COLOR0_BASE:
836 case CB_COLOR1_BASE:
837 case CB_COLOR2_BASE:
838 case CB_COLOR3_BASE:
839 case CB_COLOR4_BASE:
840 case CB_COLOR5_BASE:
841 case CB_COLOR6_BASE:
842 case CB_COLOR7_BASE:
843 r = r600_cs_packet_next_reloc(p, &reloc);
844 if (r) {
845 dev_warn(p->dev, "bad SET_CONTEXT_REG "
846 "0x%04X\n", reg);
847 return -EINVAL;
848 }
849 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
850 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
851 tmp = (reg - CB_COLOR0_BASE) / 4;
852 track->cb_color_base_last[tmp] = ib[idx];
853 track->cb_color_bo[tmp] = reloc->robj;
854 break;
855 case DB_DEPTH_BASE:
856 r = r600_cs_packet_next_reloc(p, &reloc);
857 if (r) {
858 dev_warn(p->dev, "bad SET_CONTEXT_REG "
859 "0x%04X\n", reg);
860 return -EINVAL;
861 }
862 track->db_offset = radeon_get_ib_value(p, idx);
863 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
864 track->db_bo = reloc->robj;
865 break;
866 case DB_HTILE_DATA_BASE:
867 case SQ_PGM_START_FS:
868 case SQ_PGM_START_ES:
869 case SQ_PGM_START_VS:
870 case SQ_PGM_START_GS:
871 case SQ_PGM_START_PS:
872 r = r600_cs_packet_next_reloc(p, &reloc);
873 if (r) {
874 dev_warn(p->dev, "bad SET_CONTEXT_REG "
875 "0x%04X\n", reg);
876 return -EINVAL;
877 }
878 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
879 break;
880 default:
881 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
882 return -EINVAL;
883 }
884 return 0;
885}
886
887static inline unsigned minify(unsigned size, unsigned levels)
888{
889 size = size >> levels;
890 if (size < 1)
891 size = 1;
892 return size;
893}
894
895static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels,
896 unsigned w0, unsigned h0, unsigned d0, unsigned bpe,
897 unsigned *l0_size, unsigned *mipmap_size)
898{
899 unsigned offset, i, level, face;
900 unsigned width, height, depth, rowstride, size;
901
902 w0 = minify(w0, 0);
903 h0 = minify(h0, 0);
904 d0 = minify(d0, 0);
905 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
906 width = minify(w0, i);
907 height = minify(h0, i);
908 depth = minify(d0, i);
909 for(face = 0; face < nfaces; face++) {
910 rowstride = ((width * bpe) + 255) & ~255;
911 size = height * rowstride * depth;
912 offset += size;
913 offset = (offset + 0x1f) & ~0x1f;
914 }
915 }
916 *l0_size = (((w0 * bpe) + 255) & ~255) * h0 * d0;
917 *mipmap_size = offset;
918 if (!blevel)
919 *mipmap_size -= *l0_size;
920 if (!nlevels)
921 *mipmap_size = *l0_size;
922}
923
924/**
925 * r600_check_texture_resource() - check if register is authorized or not
926 * @p: parser structure holding parsing context
927 * @idx: index into the cs buffer
928 * @texture: texture's bo structure
929 * @mipmap: mipmap's bo structure
930 *
931 * This function will check that the resource has valid field and that
932 * the texture and mipmap bo object are big enough to cover this resource.
933 */
934static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
935 struct radeon_bo *texture,
936 struct radeon_bo *mipmap)
937{
938 u32 nfaces, nlevels, blevel, w0, h0, d0, bpe;
939 u32 word0, word1, l0_size, mipmap_size;
940
941 /* on legacy kernel we don't perform advanced check */
942 if (p->rdev == NULL)
943 return 0;
944 word0 = radeon_get_ib_value(p, idx + 0);
945 word1 = radeon_get_ib_value(p, idx + 1);
946 w0 = G_038000_TEX_WIDTH(word0) + 1;
947 h0 = G_038004_TEX_HEIGHT(word1) + 1;
948 d0 = G_038004_TEX_DEPTH(word1);
949 nfaces = 1;
950 switch (G_038000_DIM(word0)) {
951 case V_038000_SQ_TEX_DIM_1D:
952 case V_038000_SQ_TEX_DIM_2D:
953 case V_038000_SQ_TEX_DIM_3D:
954 break;
955 case V_038000_SQ_TEX_DIM_CUBEMAP:
956 nfaces = 6;
957 break;
958 case V_038000_SQ_TEX_DIM_1D_ARRAY:
959 case V_038000_SQ_TEX_DIM_2D_ARRAY:
960 case V_038000_SQ_TEX_DIM_2D_MSAA:
961 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
962 default:
963 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
964 return -EINVAL;
965 }
966 if (r600_bpe_from_format(&bpe, G_038004_DATA_FORMAT(word1))) {
967 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
968 __func__, __LINE__, G_038004_DATA_FORMAT(word1));
969 return -EINVAL;
970 }
971 word0 = radeon_get_ib_value(p, idx + 4);
972 word1 = radeon_get_ib_value(p, idx + 5);
973 blevel = G_038010_BASE_LEVEL(word0);
974 nlevels = G_038014_LAST_LEVEL(word1);
975 r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe, &l0_size, &mipmap_size);
976 /* using get ib will give us the offset into the texture bo */
977 word0 = radeon_get_ib_value(p, idx + 2);
978 if ((l0_size + word0) > radeon_bo_size(texture)) {
979 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
980 w0, h0, bpe, word0, l0_size, radeon_bo_size(texture));
981 return -EINVAL;
982 }
983 /* using get ib will give us the offset into the mipmap bo */
984 word0 = radeon_get_ib_value(p, idx + 3);
985 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
986 dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
987 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));
988 return -EINVAL;
989 }
990 return 0;
991}
992
362static int r600_packet3_check(struct radeon_cs_parser *p, 993static int r600_packet3_check(struct radeon_cs_parser *p,
363 struct radeon_cs_packet *pkt) 994 struct radeon_cs_packet *pkt)
364{ 995{
@@ -408,12 +1039,22 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
408 } 1039 }
409 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); 1040 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
410 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; 1041 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1042 r = r600_cs_track_check(p);
1043 if (r) {
1044 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1045 return r;
1046 }
411 break; 1047 break;
412 case PACKET3_DRAW_INDEX_AUTO: 1048 case PACKET3_DRAW_INDEX_AUTO:
413 if (pkt->count != 1) { 1049 if (pkt->count != 1) {
414 DRM_ERROR("bad DRAW_INDEX_AUTO\n"); 1050 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
415 return -EINVAL; 1051 return -EINVAL;
416 } 1052 }
1053 r = r600_cs_track_check(p);
1054 if (r) {
1055 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1056 return r;
1057 }
417 break; 1058 break;
418 case PACKET3_DRAW_INDEX_IMMD_BE: 1059 case PACKET3_DRAW_INDEX_IMMD_BE:
419 case PACKET3_DRAW_INDEX_IMMD: 1060 case PACKET3_DRAW_INDEX_IMMD:
@@ -421,6 +1062,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
421 DRM_ERROR("bad DRAW_INDEX_IMMD\n"); 1062 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
422 return -EINVAL; 1063 return -EINVAL;
423 } 1064 }
1065 r = r600_cs_track_check(p);
1066 if (r) {
1067 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1068 return r;
1069 }
424 break; 1070 break;
425 case PACKET3_WAIT_REG_MEM: 1071 case PACKET3_WAIT_REG_MEM:
426 if (pkt->count != 5) { 1072 if (pkt->count != 5) {
@@ -493,30 +1139,9 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
493 } 1139 }
494 for (i = 0; i < pkt->count; i++) { 1140 for (i = 0; i < pkt->count; i++) {
495 reg = start_reg + (4 * i); 1141 reg = start_reg + (4 * i);
496 switch (reg) { 1142 r = r600_cs_check_reg(p, reg, idx+1+i);
497 case SQ_ESGS_RING_BASE: 1143 if (r)
498 case SQ_GSVS_RING_BASE: 1144 return r;
499 case SQ_ESTMP_RING_BASE:
500 case SQ_GSTMP_RING_BASE:
501 case SQ_VSTMP_RING_BASE:
502 case SQ_PSTMP_RING_BASE:
503 case SQ_FBUF_RING_BASE:
504 case SQ_REDUC_RING_BASE:
505 case SX_MEMORY_EXPORT_BASE:
506 r = r600_cs_packet_next_reloc(p, &reloc);
507 if (r) {
508 DRM_ERROR("bad SET_CONFIG_REG "
509 "0x%04X\n", reg);
510 return -EINVAL;
511 }
512 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
513 break;
514 case CP_COHER_BASE:
515 /* use PACKET3_SURFACE_SYNC */
516 return -EINVAL;
517 default:
518 break;
519 }
520 } 1145 }
521 break; 1146 break;
522 case PACKET3_SET_CONTEXT_REG: 1147 case PACKET3_SET_CONTEXT_REG:
@@ -530,106 +1155,9 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
530 } 1155 }
531 for (i = 0; i < pkt->count; i++) { 1156 for (i = 0; i < pkt->count; i++) {
532 reg = start_reg + (4 * i); 1157 reg = start_reg + (4 * i);
533 switch (reg) { 1158 r = r600_cs_check_reg(p, reg, idx+1+i);
534 /* This register were added late, there is userspace 1159 if (r)
535 * which does provide relocation for those but set 1160 return r;
536 * 0 offset. In order to avoid breaking old userspace
537 * we detect this and set address to point to last
538 * CB_COLOR0_BASE, note that if userspace doesn't set
539 * CB_COLOR0_BASE before this register we will report
540 * error. Old userspace always set CB_COLOR0_BASE
541 * before any of this.
542 */
543 case R_0280E0_CB_COLOR0_FRAG:
544 case R_0280E4_CB_COLOR1_FRAG:
545 case R_0280E8_CB_COLOR2_FRAG:
546 case R_0280EC_CB_COLOR3_FRAG:
547 case R_0280F0_CB_COLOR4_FRAG:
548 case R_0280F4_CB_COLOR5_FRAG:
549 case R_0280F8_CB_COLOR6_FRAG:
550 case R_0280FC_CB_COLOR7_FRAG:
551 case R_0280C0_CB_COLOR0_TILE:
552 case R_0280C4_CB_COLOR1_TILE:
553 case R_0280C8_CB_COLOR2_TILE:
554 case R_0280CC_CB_COLOR3_TILE:
555 case R_0280D0_CB_COLOR4_TILE:
556 case R_0280D4_CB_COLOR5_TILE:
557 case R_0280D8_CB_COLOR6_TILE:
558 case R_0280DC_CB_COLOR7_TILE:
559 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
560 if (!track->cb_color0_base_last) {
561 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
562 return -EINVAL;
563 }
564 ib[idx+1+i] = track->cb_color0_base_last;
565 printk_once(KERN_WARNING "radeon: You have old & broken userspace "
566 "please consider updating mesa & xf86-video-ati\n");
567 } else {
568 r = r600_cs_packet_next_reloc(p, &reloc);
569 if (r) {
570 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
571 return -EINVAL;
572 }
573 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
574 }
575 break;
576 case DB_DEPTH_BASE:
577 case DB_HTILE_DATA_BASE:
578 case CB_COLOR0_BASE:
579 r = r600_cs_packet_next_reloc(p, &reloc);
580 if (r) {
581 DRM_ERROR("bad SET_CONTEXT_REG "
582 "0x%04X\n", reg);
583 return -EINVAL;
584 }
585 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
586 track->cb_color0_base_last = ib[idx+1+i];
587 break;
588 case CB_COLOR1_BASE:
589 case CB_COLOR2_BASE:
590 case CB_COLOR3_BASE:
591 case CB_COLOR4_BASE:
592 case CB_COLOR5_BASE:
593 case CB_COLOR6_BASE:
594 case CB_COLOR7_BASE:
595 case SQ_PGM_START_FS:
596 case SQ_PGM_START_ES:
597 case SQ_PGM_START_VS:
598 case SQ_PGM_START_GS:
599 case SQ_PGM_START_PS:
600 r = r600_cs_packet_next_reloc(p, &reloc);
601 if (r) {
602 DRM_ERROR("bad SET_CONTEXT_REG "
603 "0x%04X\n", reg);
604 return -EINVAL;
605 }
606 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
607 break;
608 case VGT_DMA_BASE:
609 case VGT_DMA_BASE_HI:
610 /* These should be handled by DRAW_INDEX packet 3 */
611 case VGT_STRMOUT_BASE_OFFSET_0:
612 case VGT_STRMOUT_BASE_OFFSET_1:
613 case VGT_STRMOUT_BASE_OFFSET_2:
614 case VGT_STRMOUT_BASE_OFFSET_3:
615 case VGT_STRMOUT_BASE_OFFSET_HI_0:
616 case VGT_STRMOUT_BASE_OFFSET_HI_1:
617 case VGT_STRMOUT_BASE_OFFSET_HI_2:
618 case VGT_STRMOUT_BASE_OFFSET_HI_3:
619 case VGT_STRMOUT_BUFFER_BASE_0:
620 case VGT_STRMOUT_BUFFER_BASE_1:
621 case VGT_STRMOUT_BUFFER_BASE_2:
622 case VGT_STRMOUT_BUFFER_BASE_3:
623 case VGT_STRMOUT_BUFFER_OFFSET_0:
624 case VGT_STRMOUT_BUFFER_OFFSET_1:
625 case VGT_STRMOUT_BUFFER_OFFSET_2:
626 case VGT_STRMOUT_BUFFER_OFFSET_3:
627 /* These should be handled by STRMOUT_BUFFER packet 3 */
628 DRM_ERROR("bad context reg: 0x%08x\n", reg);
629 return -EINVAL;
630 default:
631 break;
632 }
633 } 1161 }
634 break; 1162 break;
635 case PACKET3_SET_RESOURCE: 1163 case PACKET3_SET_RESOURCE:
@@ -646,6 +1174,9 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
646 return -EINVAL; 1174 return -EINVAL;
647 } 1175 }
648 for (i = 0; i < (pkt->count / 7); i++) { 1176 for (i = 0; i < (pkt->count / 7); i++) {
1177 struct radeon_bo *texture, *mipmap;
1178 u32 size, offset;
1179
649 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { 1180 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
650 case SQ_TEX_VTX_VALID_TEXTURE: 1181 case SQ_TEX_VTX_VALID_TEXTURE:
651 /* tex base */ 1182 /* tex base */
@@ -655,6 +1186,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
655 return -EINVAL; 1186 return -EINVAL;
656 } 1187 }
657 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1188 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1189 texture = reloc->robj;
658 /* tex mip base */ 1190 /* tex mip base */
659 r = r600_cs_packet_next_reloc(p, &reloc); 1191 r = r600_cs_packet_next_reloc(p, &reloc);
660 if (r) { 1192 if (r) {
@@ -662,6 +1194,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
662 return -EINVAL; 1194 return -EINVAL;
663 } 1195 }
664 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1196 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1197 mipmap = reloc->robj;
1198 r = r600_check_texture_resource(p, idx+(i*7)+1,
1199 texture, mipmap);
1200 if (r)
1201 return r;
665 break; 1202 break;
666 case SQ_TEX_VTX_VALID_BUFFER: 1203 case SQ_TEX_VTX_VALID_BUFFER:
667 /* vtx base */ 1204 /* vtx base */
@@ -670,6 +1207,13 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
670 DRM_ERROR("bad SET_RESOURCE\n"); 1207 DRM_ERROR("bad SET_RESOURCE\n");
671 return -EINVAL; 1208 return -EINVAL;
672 } 1209 }
1210 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1211 size = radeon_get_ib_value(p, idx+1+(i*7)+1);
1212 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1213 /* force size to size of the buffer */
1214 dev_warn(p->dev, "vbo resource seems too big for the bo\n");
1215 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1216 }
673 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); 1217 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
674 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; 1218 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
675 break; 1219 break;
@@ -760,8 +1304,23 @@ int r600_cs_parse(struct radeon_cs_parser *p)
760 struct r600_cs_track *track; 1304 struct r600_cs_track *track;
761 int r; 1305 int r;
762 1306
763 track = kzalloc(sizeof(*track), GFP_KERNEL); 1307 if (p->track == NULL) {
764 p->track = track; 1308 /* initialize tracker, we are in kms */
1309 track = kzalloc(sizeof(*track), GFP_KERNEL);
1310 if (track == NULL)
1311 return -ENOMEM;
1312 r600_cs_track_init(track);
1313 if (p->rdev->family < CHIP_RV770) {
1314 track->npipes = p->rdev->config.r600.tiling_npipes;
1315 track->nbanks = p->rdev->config.r600.tiling_nbanks;
1316 track->group_size = p->rdev->config.r600.tiling_group_size;
1317 } else if (p->rdev->family <= CHIP_RV740) {
1318 track->npipes = p->rdev->config.rv770.tiling_npipes;
1319 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1320 track->group_size = p->rdev->config.rv770.tiling_group_size;
1321 }
1322 p->track = track;
1323 }
765 do { 1324 do {
766 r = r600_cs_packet_parse(p, &pkt, p->idx); 1325 r = r600_cs_packet_parse(p, &pkt, p->idx);
767 if (r) { 1326 if (r) {
@@ -779,9 +1338,11 @@ int r600_cs_parse(struct radeon_cs_parser *p)
779 break; 1338 break;
780 default: 1339 default:
781 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1340 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1341 kfree(p->track);
782 return -EINVAL; 1342 return -EINVAL;
783 } 1343 }
784 if (r) { 1344 if (r) {
1345 kfree(p->track);
785 return r; 1346 return r;
786 } 1347 }
787 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1348 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
@@ -791,6 +1352,7 @@ int r600_cs_parse(struct radeon_cs_parser *p)
791 mdelay(1); 1352 mdelay(1);
792 } 1353 }
793#endif 1354#endif
1355 kfree(p->track);
794 return 0; 1356 return 0;
795} 1357}
796 1358
@@ -833,9 +1395,16 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
833{ 1395{
834 struct radeon_cs_parser parser; 1396 struct radeon_cs_parser parser;
835 struct radeon_cs_chunk *ib_chunk; 1397 struct radeon_cs_chunk *ib_chunk;
836 struct radeon_ib fake_ib; 1398 struct radeon_ib fake_ib;
1399 struct r600_cs_track *track;
837 int r; 1400 int r;
838 1401
1402 /* initialize tracker */
1403 track = kzalloc(sizeof(*track), GFP_KERNEL);
1404 if (track == NULL)
1405 return -ENOMEM;
1406 r600_cs_track_init(track);
1407 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
839 /* initialize parser */ 1408 /* initialize parser */
840 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 1409 memset(&parser, 0, sizeof(struct radeon_cs_parser));
841 parser.filp = filp; 1410 parser.filp = filp;
@@ -843,6 +1412,7 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
843 parser.rdev = NULL; 1412 parser.rdev = NULL;
844 parser.family = family; 1413 parser.family = family;
845 parser.ib = &fake_ib; 1414 parser.ib = &fake_ib;
1415 parser.track = track;
846 fake_ib.ptr = ib; 1416 fake_ib.ptr = ib;
847 r = radeon_cs_parser_init(&parser, data); 1417 r = radeon_cs_parser_init(&parser, data);
848 if (r) { 1418 if (r) {
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 30480881aed1..5b2e4d442823 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -883,6 +883,16 @@
883 883
884#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 884#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
885 885
886#define R_028C04_PA_SC_AA_CONFIG 0x028C04
887#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)
888#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)
889#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC
890#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
891#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
892#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
893#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)
894#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)
895#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF
886#define R_0280E0_CB_COLOR0_FRAG 0x0280E0 896#define R_0280E0_CB_COLOR0_FRAG 0x0280E0
887#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 897#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
888#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 898#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
@@ -905,6 +915,461 @@
905#define R_0280D4_CB_COLOR5_TILE 0x0280D4 915#define R_0280D4_CB_COLOR5_TILE 0x0280D4
906#define R_0280D8_CB_COLOR6_TILE 0x0280D8 916#define R_0280D8_CB_COLOR6_TILE 0x0280D8
907#define R_0280DC_CB_COLOR7_TILE 0x0280DC 917#define R_0280DC_CB_COLOR7_TILE 0x0280DC
908 918#define R_0280A0_CB_COLOR0_INFO 0x0280A0
919#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)
920#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)
921#define C_0280A0_ENDIAN 0xFFFFFFFC
922#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)
923#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)
924#define C_0280A0_FORMAT 0xFFFFFF03
925#define V_0280A0_COLOR_INVALID 0x00000000
926#define V_0280A0_COLOR_8 0x00000001
927#define V_0280A0_COLOR_4_4 0x00000002
928#define V_0280A0_COLOR_3_3_2 0x00000003
929#define V_0280A0_COLOR_16 0x00000005
930#define V_0280A0_COLOR_16_FLOAT 0x00000006
931#define V_0280A0_COLOR_8_8 0x00000007
932#define V_0280A0_COLOR_5_6_5 0x00000008
933#define V_0280A0_COLOR_6_5_5 0x00000009
934#define V_0280A0_COLOR_1_5_5_5 0x0000000A
935#define V_0280A0_COLOR_4_4_4_4 0x0000000B
936#define V_0280A0_COLOR_5_5_5_1 0x0000000C
937#define V_0280A0_COLOR_32 0x0000000D
938#define V_0280A0_COLOR_32_FLOAT 0x0000000E
939#define V_0280A0_COLOR_16_16 0x0000000F
940#define V_0280A0_COLOR_16_16_FLOAT 0x00000010
941#define V_0280A0_COLOR_8_24 0x00000011
942#define V_0280A0_COLOR_8_24_FLOAT 0x00000012
943#define V_0280A0_COLOR_24_8 0x00000013
944#define V_0280A0_COLOR_24_8_FLOAT 0x00000014
945#define V_0280A0_COLOR_10_11_11 0x00000015
946#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016
947#define V_0280A0_COLOR_11_11_10 0x00000017
948#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018
949#define V_0280A0_COLOR_2_10_10_10 0x00000019
950#define V_0280A0_COLOR_8_8_8_8 0x0000001A
951#define V_0280A0_COLOR_10_10_10_2 0x0000001B
952#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C
953#define V_0280A0_COLOR_32_32 0x0000001D
954#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E
955#define V_0280A0_COLOR_16_16_16_16 0x0000001F
956#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020
957#define V_0280A0_COLOR_32_32_32_32 0x00000022
958#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023
959#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)
960#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)
961#define C_0280A0_ARRAY_MODE 0xFFFFF0FF
962#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000
963#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001
964#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002
965#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004
966#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)
967#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
968#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF
969#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)
970#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)
971#define C_0280A0_READ_SIZE 0xFFFF7FFF
972#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)
973#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)
974#define C_0280A0_COMP_SWAP 0xFFFCFFFF
975#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
976#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
977#define C_0280A0_TILE_MODE 0xFFF3FFFF
978#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
979#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
980#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
981#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)
982#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)
983#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF
984#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)
985#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)
986#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF
987#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)
988#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)
989#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF
990#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)
991#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)
992#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF
993#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)
994#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)
995#define C_0280A0_ROUND_MODE 0xFDFFFFFF
996#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)
997#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)
998#define C_0280A0_TILE_COMPACT 0xFBFFFFFF
999#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)
1000#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)
1001#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF
1002#define R_0280A4_CB_COLOR1_INFO 0x0280A4
1003#define R_0280A8_CB_COLOR2_INFO 0x0280A8
1004#define R_0280AC_CB_COLOR3_INFO 0x0280AC
1005#define R_0280B0_CB_COLOR4_INFO 0x0280B0
1006#define R_0280B4_CB_COLOR5_INFO 0x0280B4
1007#define R_0280B8_CB_COLOR6_INFO 0x0280B8
1008#define R_0280BC_CB_COLOR7_INFO 0x0280BC
1009#define R_028060_CB_COLOR0_SIZE 0x028060
1010#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1011#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1012#define C_028060_PITCH_TILE_MAX 0xFFFFFC00
1013#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1014#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1015#define C_028060_SLICE_TILE_MAX 0xC00003FF
1016#define R_028064_CB_COLOR1_SIZE 0x028064
1017#define R_028068_CB_COLOR2_SIZE 0x028068
1018#define R_02806C_CB_COLOR3_SIZE 0x02806C
1019#define R_028070_CB_COLOR4_SIZE 0x028070
1020#define R_028074_CB_COLOR5_SIZE 0x028074
1021#define R_028078_CB_COLOR6_SIZE 0x028078
1022#define R_02807C_CB_COLOR7_SIZE 0x02807C
1023#define R_028238_CB_TARGET_MASK 0x028238
1024#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0)
1025#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF)
1026#define C_028238_TARGET0_ENABLE 0xFFFFFFF0
1027#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4)
1028#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF)
1029#define C_028238_TARGET1_ENABLE 0xFFFFFF0F
1030#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8)
1031#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF)
1032#define C_028238_TARGET2_ENABLE 0xFFFFF0FF
1033#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12)
1034#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF)
1035#define C_028238_TARGET3_ENABLE 0xFFFF0FFF
1036#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16)
1037#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF)
1038#define C_028238_TARGET4_ENABLE 0xFFF0FFFF
1039#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20)
1040#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF)
1041#define C_028238_TARGET5_ENABLE 0xFF0FFFFF
1042#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24)
1043#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF)
1044#define C_028238_TARGET6_ENABLE 0xF0FFFFFF
1045#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28)
1046#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF)
1047#define C_028238_TARGET7_ENABLE 0x0FFFFFFF
1048#define R_02823C_CB_SHADER_MASK 0x02823C
1049#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0)
1050#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF)
1051#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0
1052#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4)
1053#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF)
1054#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F
1055#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8)
1056#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF)
1057#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF
1058#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12)
1059#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF)
1060#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF
1061#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16)
1062#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF)
1063#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF
1064#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20)
1065#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF)
1066#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF
1067#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24)
1068#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF)
1069#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF
1070#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28)
1071#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF)
1072#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF
1073#define R_028AB0_VGT_STRMOUT_EN 0x028AB0
1074#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)
1075#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)
1076#define C_028AB0_STREAMOUT 0xFFFFFFFE
1077#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
1078#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)
1079#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)
1080#define C_028B20_BUFFER_0_EN 0xFFFFFFFE
1081#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)
1082#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)
1083#define C_028B20_BUFFER_1_EN 0xFFFFFFFD
1084#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)
1085#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)
1086#define C_028B20_BUFFER_2_EN 0xFFFFFFFB
1087#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)
1088#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)
1089#define C_028B20_BUFFER_3_EN 0xFFFFFFF7
1090#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1091#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1092#define C_028B20_SIZE 0x00000000
1093#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000
1094#define S_038000_DIM(x) (((x) & 0x7) << 0)
1095#define G_038000_DIM(x) (((x) >> 0) & 0x7)
1096#define C_038000_DIM 0xFFFFFFF8
1097#define V_038000_SQ_TEX_DIM_1D 0x00000000
1098#define V_038000_SQ_TEX_DIM_2D 0x00000001
1099#define V_038000_SQ_TEX_DIM_3D 0x00000002
1100#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003
1101#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004
1102#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005
1103#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006
1104#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
1105#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)
1106#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)
1107#define C_038000_TILE_MODE 0xFFFFFF87
1108#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)
1109#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)
1110#define C_038000_TILE_TYPE 0xFFFFFF7F
1111#define S_038000_PITCH(x) (((x) & 0x7FF) << 8)
1112#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)
1113#define C_038000_PITCH 0xFFF800FF
1114#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)
1115#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)
1116#define C_038000_TEX_WIDTH 0x0007FFFF
1117#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004
1118#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)
1119#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)
1120#define C_038004_TEX_HEIGHT 0xFFFFE000
1121#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)
1122#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)
1123#define C_038004_TEX_DEPTH 0xFC001FFF
1124#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)
1125#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)
1126#define C_038004_DATA_FORMAT 0x03FFFFFF
1127#define V_038004_COLOR_INVALID 0x00000000
1128#define V_038004_COLOR_8 0x00000001
1129#define V_038004_COLOR_4_4 0x00000002
1130#define V_038004_COLOR_3_3_2 0x00000003
1131#define V_038004_COLOR_16 0x00000005
1132#define V_038004_COLOR_16_FLOAT 0x00000006
1133#define V_038004_COLOR_8_8 0x00000007
1134#define V_038004_COLOR_5_6_5 0x00000008
1135#define V_038004_COLOR_6_5_5 0x00000009
1136#define V_038004_COLOR_1_5_5_5 0x0000000A
1137#define V_038004_COLOR_4_4_4_4 0x0000000B
1138#define V_038004_COLOR_5_5_5_1 0x0000000C
1139#define V_038004_COLOR_32 0x0000000D
1140#define V_038004_COLOR_32_FLOAT 0x0000000E
1141#define V_038004_COLOR_16_16 0x0000000F
1142#define V_038004_COLOR_16_16_FLOAT 0x00000010
1143#define V_038004_COLOR_8_24 0x00000011
1144#define V_038004_COLOR_8_24_FLOAT 0x00000012
1145#define V_038004_COLOR_24_8 0x00000013
1146#define V_038004_COLOR_24_8_FLOAT 0x00000014
1147#define V_038004_COLOR_10_11_11 0x00000015
1148#define V_038004_COLOR_10_11_11_FLOAT 0x00000016
1149#define V_038004_COLOR_11_11_10 0x00000017
1150#define V_038004_COLOR_11_11_10_FLOAT 0x00000018
1151#define V_038004_COLOR_2_10_10_10 0x00000019
1152#define V_038004_COLOR_8_8_8_8 0x0000001A
1153#define V_038004_COLOR_10_10_10_2 0x0000001B
1154#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C
1155#define V_038004_COLOR_32_32 0x0000001D
1156#define V_038004_COLOR_32_32_FLOAT 0x0000001E
1157#define V_038004_COLOR_16_16_16_16 0x0000001F
1158#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020
1159#define V_038004_COLOR_32_32_32_32 0x00000022
1160#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023
1161#define V_038004_FMT_1 0x00000025
1162#define V_038004_FMT_GB_GR 0x00000027
1163#define V_038004_FMT_BG_RG 0x00000028
1164#define V_038004_FMT_32_AS_8 0x00000029
1165#define V_038004_FMT_32_AS_8_8 0x0000002A
1166#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B
1167#define V_038004_FMT_8_8_8 0x0000002C
1168#define V_038004_FMT_16_16_16 0x0000002D
1169#define V_038004_FMT_16_16_16_FLOAT 0x0000002E
1170#define V_038004_FMT_32_32_32 0x0000002F
1171#define V_038004_FMT_32_32_32_FLOAT 0x00000030
1172#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010
1173#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
1174#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
1175#define C_038010_FORMAT_COMP_X 0xFFFFFFFC
1176#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
1177#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
1178#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3
1179#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
1180#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
1181#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF
1182#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
1183#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
1184#define C_038010_FORMAT_COMP_W 0xFFFFFF3F
1185#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
1186#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
1187#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF
1188#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
1189#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
1190#define C_038010_SRF_MODE_ALL 0xFFFFFBFF
1191#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
1192#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
1193#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF
1194#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
1195#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
1196#define C_038010_ENDIAN_SWAP 0xFFFFCFFF
1197#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)
1198#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)
1199#define C_038010_REQUEST_SIZE 0xFFFF3FFF
1200#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)
1201#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)
1202#define C_038010_DST_SEL_X 0xFFF8FFFF
1203#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)
1204#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
1205#define C_038010_DST_SEL_Y 0xFFC7FFFF
1206#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)
1207#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
1208#define C_038010_DST_SEL_Z 0xFE3FFFFF
1209#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)
1210#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)
1211#define C_038010_DST_SEL_W 0xF1FFFFFF
1212#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)
1213#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
1214#define C_038010_BASE_LEVEL 0x0FFFFFFF
1215#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014
1216#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)
1217#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
1218#define C_038014_LAST_LEVEL 0xFFFFFFF0
1219#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
1220#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
1221#define C_038014_BASE_ARRAY 0xFFFE000F
1222#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
1223#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
1224#define C_038014_LAST_ARRAY 0xC001FFFF
1225#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8
1226#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1227#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1228#define C_0288A8_ITEMSIZE 0xFFFF8000
1229#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44
1230#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1231#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1232#define C_008C44_MEM_SIZE 0x00000000
1233#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0
1234#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1235#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1236#define C_0288B0_ITEMSIZE 0xFFFF8000
1237#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54
1238#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1239#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1240#define C_008C54_MEM_SIZE 0x00000000
1241#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0
1242#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1243#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1244#define C_0288C0_ITEMSIZE 0xFFFF8000
1245#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74
1246#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1247#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1248#define C_008C74_MEM_SIZE 0x00000000
1249#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4
1250#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1251#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1252#define C_0288B4_ITEMSIZE 0xFFFF8000
1253#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C
1254#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1255#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1256#define C_008C5C_MEM_SIZE 0x00000000
1257#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC
1258#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1259#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1260#define C_0288AC_ITEMSIZE 0xFFFF8000
1261#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C
1262#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1263#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1264#define C_008C4C_MEM_SIZE 0x00000000
1265#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC
1266#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1267#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1268#define C_0288BC_ITEMSIZE 0xFFFF8000
1269#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C
1270#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1271#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1272#define C_008C6C_MEM_SIZE 0x00000000
1273#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4
1274#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1275#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1276#define C_0288C4_ITEMSIZE 0xFFFF8000
1277#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C
1278#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1279#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1280#define C_008C7C_MEM_SIZE 0x00000000
1281#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8
1282#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1283#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1284#define C_0288B8_ITEMSIZE 0xFFFF8000
1285#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64
1286#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1287#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1288#define C_008C64_MEM_SIZE 0x00000000
1289#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8
1290#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1291#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1292#define C_0288C8_ITEMSIZE 0xFFFF8000
1293#define R_028010_DB_DEPTH_INFO 0x028010
1294#define S_028010_FORMAT(x) (((x) & 0x7) << 0)
1295#define G_028010_FORMAT(x) (((x) >> 0) & 0x7)
1296#define C_028010_FORMAT 0xFFFFFFF8
1297#define V_028010_DEPTH_INVALID 0x00000000
1298#define V_028010_DEPTH_16 0x00000001
1299#define V_028010_DEPTH_X8_24 0x00000002
1300#define V_028010_DEPTH_8_24 0x00000003
1301#define V_028010_DEPTH_X8_24_FLOAT 0x00000004
1302#define V_028010_DEPTH_8_24_FLOAT 0x00000005
1303#define V_028010_DEPTH_32_FLOAT 0x00000006
1304#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007
1305#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)
1306#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)
1307#define C_028010_READ_SIZE 0xFFFFFFF7
1308#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)
1309#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)
1310#define C_028010_ARRAY_MODE 0xFFF87FFF
1311#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)
1312#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)
1313#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF
1314#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)
1315#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)
1316#define C_028010_TILE_COMPACT 0xFBFFFFFF
1317#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1318#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1319#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF
1320#define R_028000_DB_DEPTH_SIZE 0x028000
1321#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1322#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1323#define C_028000_PITCH_TILE_MAX 0xFFFFFC00
1324#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1325#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1326#define C_028000_SLICE_TILE_MAX 0xC00003FF
1327#define R_028004_DB_DEPTH_VIEW 0x028004
1328#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)
1329#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)
1330#define C_028004_SLICE_START 0xFFFFF800
1331#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1332#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1333#define C_028004_SLICE_MAX 0xFF001FFF
1334#define R_028800_DB_DEPTH_CONTROL 0x028800
1335#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
1336#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
1337#define C_028800_STENCIL_ENABLE 0xFFFFFFFE
1338#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
1339#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
1340#define C_028800_Z_ENABLE 0xFFFFFFFD
1341#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
1342#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
1343#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
1344#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
1345#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
1346#define C_028800_ZFUNC 0xFFFFFF8F
1347#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
1348#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
1349#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
1350#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
1351#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
1352#define C_028800_STENCILFUNC 0xFFFFF8FF
1353#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
1354#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
1355#define C_028800_STENCILFAIL 0xFFFFC7FF
1356#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
1357#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
1358#define C_028800_STENCILZPASS 0xFFFE3FFF
1359#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
1360#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
1361#define C_028800_STENCILZFAIL 0xFFF1FFFF
1362#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
1363#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
1364#define C_028800_STENCILFUNC_BF 0xFF8FFFFF
1365#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
1366#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
1367#define C_028800_STENCILFAIL_BF 0xFC7FFFFF
1368#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
1369#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
1370#define C_028800_STENCILZPASS_BF 0xE3FFFFFF
1371#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
1372#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
1373#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
909 1374
910#endif 1375#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index a7a96a240844..9eeca6f07222 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -808,6 +808,9 @@ struct r600_asic {
808 unsigned sx_max_export_pos_size; 808 unsigned sx_max_export_pos_size;
809 unsigned sx_max_export_smx_size; 809 unsigned sx_max_export_smx_size;
810 unsigned sq_num_cf_insts; 810 unsigned sq_num_cf_insts;
811 unsigned tiling_nbanks;
812 unsigned tiling_npipes;
813 unsigned tiling_group_size;
811}; 814};
812 815
813struct rv770_asic { 816struct rv770_asic {
@@ -828,6 +831,9 @@ struct rv770_asic {
828 unsigned sc_prim_fifo_size; 831 unsigned sc_prim_fifo_size;
829 unsigned sc_hiz_tile_fifo_size; 832 unsigned sc_hiz_tile_fifo_size;
830 unsigned sc_earlyz_tile_fifo_fize; 833 unsigned sc_earlyz_tile_fifo_fize;
834 unsigned tiling_nbanks;
835 unsigned tiling_npipes;
836 unsigned tiling_group_size;
831}; 837};
832 838
833union radeon_asic_config { 839union radeon_asic_config {
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index e13785282a82..b058316e311f 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -294,6 +294,9 @@ typedef struct drm_radeon_private {
294 int r700_sc_prim_fifo_size; 294 int r700_sc_prim_fifo_size;
295 int r700_sc_hiz_tile_fifo_size; 295 int r700_sc_hiz_tile_fifo_size;
296 int r700_sc_earlyz_tile_fifo_fize; 296 int r700_sc_earlyz_tile_fifo_fize;
297 int r600_group_size;
298 int r600_npipes;
299 int r600_nbanks;
297 300
298 struct mutex cs_mutex; 301 struct mutex cs_mutex;
299 u32 cs_id_scnt; 302 u32 cs_id_scnt;
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
new file mode 100644
index 000000000000..8f414a5f520f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -0,0 +1,837 @@
1r600 0x9400
20x000287A0 R7xx_CB_SHADER_CONTROL
30x00028230 R7xx_PA_SC_EDGERULE
40x000286C8 R7xx_SPI_THREAD_GROUPING
50x00008D8C R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
60x000088C4 VGT_CACHE_INVALIDATION
70x00028A50 VGT_ENHANCE
80x000088CC VGT_ES_PER_GS
90x00028A2C VGT_GROUP_DECR
100x00028A28 VGT_GROUP_FIRST_DECR
110x00028A24 VGT_GROUP_PRIM_TYPE
120x00028A30 VGT_GROUP_VECT_0_CNTL
130x00028A38 VGT_GROUP_VECT_0_FMT_CNTL
140x00028A34 VGT_GROUP_VECT_1_CNTL
150x00028A3C VGT_GROUP_VECT_1_FMT_CNTL
160x00028A40 VGT_GS_MODE
170x00028A6C VGT_GS_OUT_PRIM_TYPE
180x000088C8 VGT_GS_PER_ES
190x000088E8 VGT_GS_PER_VS
200x000088D4 VGT_GS_VERTEX_REUSE
210x00028A14 VGT_HOS_CNTL
220x00028A18 VGT_HOS_MAX_TESS_LEVEL
230x00028A1C VGT_HOS_MIN_TESS_LEVEL
240x00028A20 VGT_HOS_REUSE_DEPTH
250x0000895C VGT_INDEX_TYPE
260x00028408 VGT_INDX_OFFSET
270x00028AA0 VGT_INSTANCE_STEP_RATE_0
280x00028AA4 VGT_INSTANCE_STEP_RATE_1
290x000088C0 VGT_LAST_COPY_STATE
300x00028400 VGT_MAX_VTX_INDX
310x000088D8 VGT_MC_LAT_CNTL
320x00028404 VGT_MIN_VTX_INDX
330x00028A94 VGT_MULTI_PRIM_IB_RESET_EN
340x0002840C VGT_MULTI_PRIM_IB_RESET_INDX
350x00008970 VGT_NUM_INDICES
360x00008974 VGT_NUM_INSTANCES
370x00028A10 VGT_OUTPUT_PATH_CNTL
380x00028C5C VGT_OUT_DEALLOC_CNTL
390x00028A84 VGT_PRIMITIVEID_EN
400x00008958 VGT_PRIMITIVE_TYPE
410x00028AB4 VGT_REUSE_OFF
420x00028C58 VGT_VERTEX_REUSE_BLOCK_CNTL
430x00028AB8 VGT_VTX_CNT_EN
440x000088B0 VGT_VTX_VECT_EJECT_REG
450x00028810 PA_CL_CLIP_CNTL
460x00008A14 PA_CL_ENHANCE
470x00028C14 PA_CL_GB_HORZ_CLIP_ADJ
480x00028C18 PA_CL_GB_HORZ_DISC_ADJ
490x00028C0C PA_CL_GB_VERT_CLIP_ADJ
500x00028C10 PA_CL_GB_VERT_DISC_ADJ
510x00028820 PA_CL_NANINF_CNTL
520x00028E1C PA_CL_POINT_CULL_RAD
530x00028E18 PA_CL_POINT_SIZE
540x00028E10 PA_CL_POINT_X_RAD
550x00028E14 PA_CL_POINT_Y_RAD
560x00028E2C PA_CL_UCP_0_W
570x00028E3C PA_CL_UCP_1_W
580x00028E4C PA_CL_UCP_2_W
590x00028E5C PA_CL_UCP_3_W
600x00028E6C PA_CL_UCP_4_W
610x00028E7C PA_CL_UCP_5_W
620x00028E20 PA_CL_UCP_0_X
630x00028E30 PA_CL_UCP_1_X
640x00028E40 PA_CL_UCP_2_X
650x00028E50 PA_CL_UCP_3_X
660x00028E60 PA_CL_UCP_4_X
670x00028E70 PA_CL_UCP_5_X
680x00028E24 PA_CL_UCP_0_Y
690x00028E34 PA_CL_UCP_1_Y
700x00028E44 PA_CL_UCP_2_Y
710x00028E54 PA_CL_UCP_3_Y
720x00028E64 PA_CL_UCP_4_Y
730x00028E74 PA_CL_UCP_5_Y
740x00028E28 PA_CL_UCP_0_Z
750x00028E38 PA_CL_UCP_1_Z
760x00028E48 PA_CL_UCP_2_Z
770x00028E58 PA_CL_UCP_3_Z
780x00028E68 PA_CL_UCP_4_Z
790x00028E78 PA_CL_UCP_5_Z
800x00028440 PA_CL_VPORT_XOFFSET_0
810x00028458 PA_CL_VPORT_XOFFSET_1
820x00028470 PA_CL_VPORT_XOFFSET_2
830x00028488 PA_CL_VPORT_XOFFSET_3
840x000284A0 PA_CL_VPORT_XOFFSET_4
850x000284B8 PA_CL_VPORT_XOFFSET_5
860x000284D0 PA_CL_VPORT_XOFFSET_6
870x000284E8 PA_CL_VPORT_XOFFSET_7
880x00028500 PA_CL_VPORT_XOFFSET_8
890x00028518 PA_CL_VPORT_XOFFSET_9
900x00028530 PA_CL_VPORT_XOFFSET_10
910x00028548 PA_CL_VPORT_XOFFSET_11
920x00028560 PA_CL_VPORT_XOFFSET_12
930x00028578 PA_CL_VPORT_XOFFSET_13
940x00028590 PA_CL_VPORT_XOFFSET_14
950x000285A8 PA_CL_VPORT_XOFFSET_15
960x0002843C PA_CL_VPORT_XSCALE_0
970x00028454 PA_CL_VPORT_XSCALE_1
980x0002846C PA_CL_VPORT_XSCALE_2
990x00028484 PA_CL_VPORT_XSCALE_3
1000x0002849C PA_CL_VPORT_XSCALE_4
1010x000284B4 PA_CL_VPORT_XSCALE_5
1020x000284CC PA_CL_VPORT_XSCALE_6
1030x000284E4 PA_CL_VPORT_XSCALE_7
1040x000284FC PA_CL_VPORT_XSCALE_8
1050x00028514 PA_CL_VPORT_XSCALE_9
1060x0002852C PA_CL_VPORT_XSCALE_10
1070x00028544 PA_CL_VPORT_XSCALE_11
1080x0002855C PA_CL_VPORT_XSCALE_12
1090x00028574 PA_CL_VPORT_XSCALE_13
1100x0002858C PA_CL_VPORT_XSCALE_14
1110x000285A4 PA_CL_VPORT_XSCALE_15
1120x00028448 PA_CL_VPORT_YOFFSET_0
1130x00028460 PA_CL_VPORT_YOFFSET_1
1140x00028478 PA_CL_VPORT_YOFFSET_2
1150x00028490 PA_CL_VPORT_YOFFSET_3
1160x000284A8 PA_CL_VPORT_YOFFSET_4
1170x000284C0 PA_CL_VPORT_YOFFSET_5
1180x000284D8 PA_CL_VPORT_YOFFSET_6
1190x000284F0 PA_CL_VPORT_YOFFSET_7
1200x00028508 PA_CL_VPORT_YOFFSET_8
1210x00028520 PA_CL_VPORT_YOFFSET_9
1220x00028538 PA_CL_VPORT_YOFFSET_10
1230x00028550 PA_CL_VPORT_YOFFSET_11
1240x00028568 PA_CL_VPORT_YOFFSET_12
1250x00028580 PA_CL_VPORT_YOFFSET_13
1260x00028598 PA_CL_VPORT_YOFFSET_14
1270x000285B0 PA_CL_VPORT_YOFFSET_15
1280x00028444 PA_CL_VPORT_YSCALE_0
1290x0002845C PA_CL_VPORT_YSCALE_1
1300x00028474 PA_CL_VPORT_YSCALE_2
1310x0002848C PA_CL_VPORT_YSCALE_3
1320x000284A4 PA_CL_VPORT_YSCALE_4
1330x000284BC PA_CL_VPORT_YSCALE_5
1340x000284D4 PA_CL_VPORT_YSCALE_6
1350x000284EC PA_CL_VPORT_YSCALE_7
1360x00028504 PA_CL_VPORT_YSCALE_8
1370x0002851C PA_CL_VPORT_YSCALE_9
1380x00028534 PA_CL_VPORT_YSCALE_10
1390x0002854C PA_CL_VPORT_YSCALE_11
1400x00028564 PA_CL_VPORT_YSCALE_12
1410x0002857C PA_CL_VPORT_YSCALE_13
1420x00028594 PA_CL_VPORT_YSCALE_14
1430x000285AC PA_CL_VPORT_YSCALE_15
1440x00028450 PA_CL_VPORT_ZOFFSET_0
1450x00028468 PA_CL_VPORT_ZOFFSET_1
1460x00028480 PA_CL_VPORT_ZOFFSET_2
1470x00028498 PA_CL_VPORT_ZOFFSET_3
1480x000284B0 PA_CL_VPORT_ZOFFSET_4
1490x000284C8 PA_CL_VPORT_ZOFFSET_5
1500x000284E0 PA_CL_VPORT_ZOFFSET_6
1510x000284F8 PA_CL_VPORT_ZOFFSET_7
1520x00028510 PA_CL_VPORT_ZOFFSET_8
1530x00028528 PA_CL_VPORT_ZOFFSET_9
1540x00028540 PA_CL_VPORT_ZOFFSET_10
1550x00028558 PA_CL_VPORT_ZOFFSET_11
1560x00028570 PA_CL_VPORT_ZOFFSET_12
1570x00028588 PA_CL_VPORT_ZOFFSET_13
1580x000285A0 PA_CL_VPORT_ZOFFSET_14
1590x000285B8 PA_CL_VPORT_ZOFFSET_15
1600x0002844C PA_CL_VPORT_ZSCALE_0
1610x00028464 PA_CL_VPORT_ZSCALE_1
1620x0002847C PA_CL_VPORT_ZSCALE_2
1630x00028494 PA_CL_VPORT_ZSCALE_3
1640x000284AC PA_CL_VPORT_ZSCALE_4
1650x000284C4 PA_CL_VPORT_ZSCALE_5
1660x000284DC PA_CL_VPORT_ZSCALE_6
1670x000284F4 PA_CL_VPORT_ZSCALE_7
1680x0002850C PA_CL_VPORT_ZSCALE_8
1690x00028524 PA_CL_VPORT_ZSCALE_9
1700x0002853C PA_CL_VPORT_ZSCALE_10
1710x00028554 PA_CL_VPORT_ZSCALE_11
1720x0002856C PA_CL_VPORT_ZSCALE_12
1730x00028584 PA_CL_VPORT_ZSCALE_13
1740x0002859C PA_CL_VPORT_ZSCALE_14
1750x000285B4 PA_CL_VPORT_ZSCALE_15
1760x0002881C PA_CL_VS_OUT_CNTL
1770x00028818 PA_CL_VTE_CNTL
1780x00028C48 PA_SC_AA_MASK
1790x00008B40 PA_SC_AA_SAMPLE_LOCS_2S
1800x00008B44 PA_SC_AA_SAMPLE_LOCS_4S
1810x00008B48 PA_SC_AA_SAMPLE_LOCS_8S_WD0
1820x00008B4C PA_SC_AA_SAMPLE_LOCS_8S_WD1
1830x00028C20 PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX
1840x00028C1C PA_SC_AA_SAMPLE_LOCS_MCTX
1850x00028214 PA_SC_CLIPRECT_0_BR
1860x0002821C PA_SC_CLIPRECT_1_BR
1870x00028224 PA_SC_CLIPRECT_2_BR
1880x0002822C PA_SC_CLIPRECT_3_BR
1890x00028210 PA_SC_CLIPRECT_0_TL
1900x00028218 PA_SC_CLIPRECT_1_TL
1910x00028220 PA_SC_CLIPRECT_2_TL
1920x00028228 PA_SC_CLIPRECT_3_TL
1930x0002820C PA_SC_CLIPRECT_RULE
1940x00008BF0 PA_SC_ENHANCE
1950x00028244 PA_SC_GENERIC_SCISSOR_BR
1960x00028240 PA_SC_GENERIC_SCISSOR_TL
1970x00028C00 PA_SC_LINE_CNTL
1980x00028A0C PA_SC_LINE_STIPPLE
1990x00008B10 PA_SC_LINE_STIPPLE_STATE
2000x00028A4C PA_SC_MODE_CNTL
2010x00028A48 PA_SC_MPASS_PS_CNTL
2020x00008B20 PA_SC_MULTI_CHIP_CNTL
2030x00028034 PA_SC_SCREEN_SCISSOR_BR
2040x00028030 PA_SC_SCREEN_SCISSOR_TL
2050x00028254 PA_SC_VPORT_SCISSOR_0_BR
2060x0002825C PA_SC_VPORT_SCISSOR_1_BR
2070x00028264 PA_SC_VPORT_SCISSOR_2_BR
2080x0002826C PA_SC_VPORT_SCISSOR_3_BR
2090x00028274 PA_SC_VPORT_SCISSOR_4_BR
2100x0002827C PA_SC_VPORT_SCISSOR_5_BR
2110x00028284 PA_SC_VPORT_SCISSOR_6_BR
2120x0002828C PA_SC_VPORT_SCISSOR_7_BR
2130x00028294 PA_SC_VPORT_SCISSOR_8_BR
2140x0002829C PA_SC_VPORT_SCISSOR_9_BR
2150x000282A4 PA_SC_VPORT_SCISSOR_10_BR
2160x000282AC PA_SC_VPORT_SCISSOR_11_BR
2170x000282B4 PA_SC_VPORT_SCISSOR_12_BR
2180x000282BC PA_SC_VPORT_SCISSOR_13_BR
2190x000282C4 PA_SC_VPORT_SCISSOR_14_BR
2200x000282CC PA_SC_VPORT_SCISSOR_15_BR
2210x00028250 PA_SC_VPORT_SCISSOR_0_TL
2220x00028258 PA_SC_VPORT_SCISSOR_1_TL
2230x00028260 PA_SC_VPORT_SCISSOR_2_TL
2240x00028268 PA_SC_VPORT_SCISSOR_3_TL
2250x00028270 PA_SC_VPORT_SCISSOR_4_TL
2260x00028278 PA_SC_VPORT_SCISSOR_5_TL
2270x00028280 PA_SC_VPORT_SCISSOR_6_TL
2280x00028288 PA_SC_VPORT_SCISSOR_7_TL
2290x00028290 PA_SC_VPORT_SCISSOR_8_TL
2300x00028298 PA_SC_VPORT_SCISSOR_9_TL
2310x000282A0 PA_SC_VPORT_SCISSOR_10_TL
2320x000282A8 PA_SC_VPORT_SCISSOR_11_TL
2330x000282B0 PA_SC_VPORT_SCISSOR_12_TL
2340x000282B8 PA_SC_VPORT_SCISSOR_13_TL
2350x000282C0 PA_SC_VPORT_SCISSOR_14_TL
2360x000282C8 PA_SC_VPORT_SCISSOR_15_TL
2370x000282D4 PA_SC_VPORT_ZMAX_0
2380x000282DC PA_SC_VPORT_ZMAX_1
2390x000282E4 PA_SC_VPORT_ZMAX_2
2400x000282EC PA_SC_VPORT_ZMAX_3
2410x000282F4 PA_SC_VPORT_ZMAX_4
2420x000282FC PA_SC_VPORT_ZMAX_5
2430x00028304 PA_SC_VPORT_ZMAX_6
2440x0002830C PA_SC_VPORT_ZMAX_7
2450x00028314 PA_SC_VPORT_ZMAX_8
2460x0002831C PA_SC_VPORT_ZMAX_9
2470x00028324 PA_SC_VPORT_ZMAX_10
2480x0002832C PA_SC_VPORT_ZMAX_11
2490x00028334 PA_SC_VPORT_ZMAX_12
2500x0002833C PA_SC_VPORT_ZMAX_13
2510x00028344 PA_SC_VPORT_ZMAX_14
2520x0002834C PA_SC_VPORT_ZMAX_15
2530x000282D0 PA_SC_VPORT_ZMIN_0
2540x000282D8 PA_SC_VPORT_ZMIN_1
2550x000282E0 PA_SC_VPORT_ZMIN_2
2560x000282E8 PA_SC_VPORT_ZMIN_3
2570x000282F0 PA_SC_VPORT_ZMIN_4
2580x000282F8 PA_SC_VPORT_ZMIN_5
2590x00028300 PA_SC_VPORT_ZMIN_6
2600x00028308 PA_SC_VPORT_ZMIN_7
2610x00028310 PA_SC_VPORT_ZMIN_8
2620x00028318 PA_SC_VPORT_ZMIN_9
2630x00028320 PA_SC_VPORT_ZMIN_10
2640x00028328 PA_SC_VPORT_ZMIN_11
2650x00028330 PA_SC_VPORT_ZMIN_12
2660x00028338 PA_SC_VPORT_ZMIN_13
2670x00028340 PA_SC_VPORT_ZMIN_14
2680x00028348 PA_SC_VPORT_ZMIN_15
2690x00028200 PA_SC_WINDOW_OFFSET
2700x00028208 PA_SC_WINDOW_SCISSOR_BR
2710x00028204 PA_SC_WINDOW_SCISSOR_TL
2720x00028A08 PA_SU_LINE_CNTL
2730x00028A04 PA_SU_POINT_MINMAX
2740x00028A00 PA_SU_POINT_SIZE
2750x00028E0C PA_SU_POLY_OFFSET_BACK_OFFSET
2760x00028E08 PA_SU_POLY_OFFSET_BACK_SCALE
2770x00028DFC PA_SU_POLY_OFFSET_CLAMP
2780x00028DF8 PA_SU_POLY_OFFSET_DB_FMT_CNTL
2790x00028E04 PA_SU_POLY_OFFSET_FRONT_OFFSET
2800x00028E00 PA_SU_POLY_OFFSET_FRONT_SCALE
2810x00028814 PA_SU_SC_MODE_CNTL
2820x00028C08 PA_SU_VTX_CNTL
2830x00008C00 SQ_CONFIG
2840x00008C04 SQ_GPR_RESOURCE_MGMT_1
2850x00008C08 SQ_GPR_RESOURCE_MGMT_2
2860x00008C10 SQ_STACK_RESOURCE_MGMT_1
2870x00008C14 SQ_STACK_RESOURCE_MGMT_2
2880x00008C0C SQ_THREAD_RESOURCE_MGMT
2890x00028380 SQ_VTX_SEMANTIC_0
2900x00028384 SQ_VTX_SEMANTIC_1
2910x00028388 SQ_VTX_SEMANTIC_2
2920x0002838C SQ_VTX_SEMANTIC_3
2930x00028390 SQ_VTX_SEMANTIC_4
2940x00028394 SQ_VTX_SEMANTIC_5
2950x00028398 SQ_VTX_SEMANTIC_6
2960x0002839C SQ_VTX_SEMANTIC_7
2970x000283A0 SQ_VTX_SEMANTIC_8
2980x000283A4 SQ_VTX_SEMANTIC_9
2990x000283A8 SQ_VTX_SEMANTIC_10
3000x000283AC SQ_VTX_SEMANTIC_11
3010x000283B0 SQ_VTX_SEMANTIC_12
3020x000283B4 SQ_VTX_SEMANTIC_13
3030x000283B8 SQ_VTX_SEMANTIC_14
3040x000283BC SQ_VTX_SEMANTIC_15
3050x000283C0 SQ_VTX_SEMANTIC_16
3060x000283C4 SQ_VTX_SEMANTIC_17
3070x000283C8 SQ_VTX_SEMANTIC_18
3080x000283CC SQ_VTX_SEMANTIC_19
3090x000283D0 SQ_VTX_SEMANTIC_20
3100x000283D4 SQ_VTX_SEMANTIC_21
3110x000283D8 SQ_VTX_SEMANTIC_22
3120x000283DC SQ_VTX_SEMANTIC_23
3130x000283E0 SQ_VTX_SEMANTIC_24
3140x000283E4 SQ_VTX_SEMANTIC_25
3150x000283E8 SQ_VTX_SEMANTIC_26
3160x000283EC SQ_VTX_SEMANTIC_27
3170x000283F0 SQ_VTX_SEMANTIC_28
3180x000283F4 SQ_VTX_SEMANTIC_29
3190x000283F8 SQ_VTX_SEMANTIC_30
3200x000283FC SQ_VTX_SEMANTIC_31
3210x000288E0 SQ_VTX_SEMANTIC_CLEAR
3220x0003CFF4 SQ_VTX_START_INST_LOC
3230x0003C000 SQ_TEX_SAMPLER_WORD0_0
3240x0003C004 SQ_TEX_SAMPLER_WORD1_0
3250x0003C008 SQ_TEX_SAMPLER_WORD2_0
3260x00030000 SQ_ALU_CONSTANT0_0
3270x00030004 SQ_ALU_CONSTANT1_0
3280x00030008 SQ_ALU_CONSTANT2_0
3290x0003000C SQ_ALU_CONSTANT3_0
3300x0003E380 SQ_BOOL_CONST_0
3310x0003E384 SQ_BOOL_CONST_1
3320x0003E388 SQ_BOOL_CONST_2
3330x0003E200 SQ_LOOP_CONST_0
3340x0003E200 SQ_LOOP_CONST_DX10_0
3350x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0
3360x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1
3370x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2
3380x000281CC SQ_ALU_CONST_BUFFER_SIZE_GS_3
3390x000281D0 SQ_ALU_CONST_BUFFER_SIZE_GS_4
3400x000281D4 SQ_ALU_CONST_BUFFER_SIZE_GS_5
3410x000281D8 SQ_ALU_CONST_BUFFER_SIZE_GS_6
3420x000281DC SQ_ALU_CONST_BUFFER_SIZE_GS_7
3430x000281E0 SQ_ALU_CONST_BUFFER_SIZE_GS_8
3440x000281E4 SQ_ALU_CONST_BUFFER_SIZE_GS_9
3450x000281E8 SQ_ALU_CONST_BUFFER_SIZE_GS_10
3460x000281EC SQ_ALU_CONST_BUFFER_SIZE_GS_11
3470x000281F0 SQ_ALU_CONST_BUFFER_SIZE_GS_12
3480x000281F4 SQ_ALU_CONST_BUFFER_SIZE_GS_13
3490x000281F8 SQ_ALU_CONST_BUFFER_SIZE_GS_14
3500x000281FC SQ_ALU_CONST_BUFFER_SIZE_GS_15
3510x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0
3520x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1
3530x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2
3540x0002814C SQ_ALU_CONST_BUFFER_SIZE_PS_3
3550x00028150 SQ_ALU_CONST_BUFFER_SIZE_PS_4
3560x00028154 SQ_ALU_CONST_BUFFER_SIZE_PS_5
3570x00028158 SQ_ALU_CONST_BUFFER_SIZE_PS_6
3580x0002815C SQ_ALU_CONST_BUFFER_SIZE_PS_7
3590x00028160 SQ_ALU_CONST_BUFFER_SIZE_PS_8
3600x00028164 SQ_ALU_CONST_BUFFER_SIZE_PS_9
3610x00028168 SQ_ALU_CONST_BUFFER_SIZE_PS_10
3620x0002816C SQ_ALU_CONST_BUFFER_SIZE_PS_11
3630x00028170 SQ_ALU_CONST_BUFFER_SIZE_PS_12
3640x00028174 SQ_ALU_CONST_BUFFER_SIZE_PS_13
3650x00028178 SQ_ALU_CONST_BUFFER_SIZE_PS_14
3660x0002817C SQ_ALU_CONST_BUFFER_SIZE_PS_15
3670x00028180 SQ_ALU_CONST_BUFFER_SIZE_VS_0
3680x00028184 SQ_ALU_CONST_BUFFER_SIZE_VS_1
3690x00028188 SQ_ALU_CONST_BUFFER_SIZE_VS_2
3700x0002818C SQ_ALU_CONST_BUFFER_SIZE_VS_3
3710x00028190 SQ_ALU_CONST_BUFFER_SIZE_VS_4
3720x00028194 SQ_ALU_CONST_BUFFER_SIZE_VS_5
3730x00028198 SQ_ALU_CONST_BUFFER_SIZE_VS_6
3740x0002819C SQ_ALU_CONST_BUFFER_SIZE_VS_7
3750x000281A0 SQ_ALU_CONST_BUFFER_SIZE_VS_8
3760x000281A4 SQ_ALU_CONST_BUFFER_SIZE_VS_9
3770x000281A8 SQ_ALU_CONST_BUFFER_SIZE_VS_10
3780x000281AC SQ_ALU_CONST_BUFFER_SIZE_VS_11
3790x000281B0 SQ_ALU_CONST_BUFFER_SIZE_VS_12
3800x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13
3810x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14
3820x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15
3830x000289C0 SQ_ALU_CONST_CACHE_GS_0
3840x000289C4 SQ_ALU_CONST_CACHE_GS_1
3850x000289C8 SQ_ALU_CONST_CACHE_GS_2
3860x000289CC SQ_ALU_CONST_CACHE_GS_3
3870x000289D0 SQ_ALU_CONST_CACHE_GS_4
3880x000289D4 SQ_ALU_CONST_CACHE_GS_5
3890x000289D8 SQ_ALU_CONST_CACHE_GS_6
3900x000289DC SQ_ALU_CONST_CACHE_GS_7
3910x000289E0 SQ_ALU_CONST_CACHE_GS_8
3920x000289E4 SQ_ALU_CONST_CACHE_GS_9
3930x000289E8 SQ_ALU_CONST_CACHE_GS_10
3940x000289EC SQ_ALU_CONST_CACHE_GS_11
3950x000289F0 SQ_ALU_CONST_CACHE_GS_12
3960x000289F4 SQ_ALU_CONST_CACHE_GS_13
3970x000289F8 SQ_ALU_CONST_CACHE_GS_14
3980x000289FC SQ_ALU_CONST_CACHE_GS_15
3990x00028940 SQ_ALU_CONST_CACHE_PS_0
4000x00028944 SQ_ALU_CONST_CACHE_PS_1
4010x00028948 SQ_ALU_CONST_CACHE_PS_2
4020x0002894C SQ_ALU_CONST_CACHE_PS_3
4030x00028950 SQ_ALU_CONST_CACHE_PS_4
4040x00028954 SQ_ALU_CONST_CACHE_PS_5
4050x00028958 SQ_ALU_CONST_CACHE_PS_6
4060x0002895C SQ_ALU_CONST_CACHE_PS_7
4070x00028960 SQ_ALU_CONST_CACHE_PS_8
4080x00028964 SQ_ALU_CONST_CACHE_PS_9
4090x00028968 SQ_ALU_CONST_CACHE_PS_10
4100x0002896C SQ_ALU_CONST_CACHE_PS_11
4110x00028970 SQ_ALU_CONST_CACHE_PS_12
4120x00028974 SQ_ALU_CONST_CACHE_PS_13
4130x00028978 SQ_ALU_CONST_CACHE_PS_14
4140x0002897C SQ_ALU_CONST_CACHE_PS_15
4150x00028980 SQ_ALU_CONST_CACHE_VS_0
4160x00028984 SQ_ALU_CONST_CACHE_VS_1
4170x00028988 SQ_ALU_CONST_CACHE_VS_2
4180x0002898C SQ_ALU_CONST_CACHE_VS_3
4190x00028990 SQ_ALU_CONST_CACHE_VS_4
4200x00028994 SQ_ALU_CONST_CACHE_VS_5
4210x00028998 SQ_ALU_CONST_CACHE_VS_6
4220x0002899C SQ_ALU_CONST_CACHE_VS_7
4230x000289A0 SQ_ALU_CONST_CACHE_VS_8
4240x000289A4 SQ_ALU_CONST_CACHE_VS_9
4250x000289A8 SQ_ALU_CONST_CACHE_VS_10
4260x000289AC SQ_ALU_CONST_CACHE_VS_11
4270x000289B0 SQ_ALU_CONST_CACHE_VS_12
4280x000289B4 SQ_ALU_CONST_CACHE_VS_13
4290x000289B8 SQ_ALU_CONST_CACHE_VS_14
4300x000289BC SQ_ALU_CONST_CACHE_VS_15
4310x000288D8 SQ_PGM_CF_OFFSET_ES
4320x000288DC SQ_PGM_CF_OFFSET_FS
4330x000288D4 SQ_PGM_CF_OFFSET_GS
4340x000288CC SQ_PGM_CF_OFFSET_PS
4350x000288D0 SQ_PGM_CF_OFFSET_VS
4360x00028854 SQ_PGM_EXPORTS_PS
4370x00028890 SQ_PGM_RESOURCES_ES
4380x000288A4 SQ_PGM_RESOURCES_FS
4390x0002887C SQ_PGM_RESOURCES_GS
4400x00028850 SQ_PGM_RESOURCES_PS
4410x00028868 SQ_PGM_RESOURCES_VS
4420x00009100 SPI_CONFIG_CNTL
4430x0000913C SPI_CONFIG_CNTL_1
4440x000286DC SPI_FOG_CNTL
4450x000286E4 SPI_FOG_FUNC_BIAS
4460x000286E0 SPI_FOG_FUNC_SCALE
4470x000286D8 SPI_INPUT_Z
4480x000286D4 SPI_INTERP_CONTROL_0
4490x00028644 SPI_PS_INPUT_CNTL_0
4500x00028648 SPI_PS_INPUT_CNTL_1
4510x0002864C SPI_PS_INPUT_CNTL_2
4520x00028650 SPI_PS_INPUT_CNTL_3
4530x00028654 SPI_PS_INPUT_CNTL_4
4540x00028658 SPI_PS_INPUT_CNTL_5
4550x0002865C SPI_PS_INPUT_CNTL_6
4560x00028660 SPI_PS_INPUT_CNTL_7
4570x00028664 SPI_PS_INPUT_CNTL_8
4580x00028668 SPI_PS_INPUT_CNTL_9
4590x0002866C SPI_PS_INPUT_CNTL_10
4600x00028670 SPI_PS_INPUT_CNTL_11
4610x00028674 SPI_PS_INPUT_CNTL_12
4620x00028678 SPI_PS_INPUT_CNTL_13
4630x0002867C SPI_PS_INPUT_CNTL_14
4640x00028680 SPI_PS_INPUT_CNTL_15
4650x00028684 SPI_PS_INPUT_CNTL_16
4660x00028688 SPI_PS_INPUT_CNTL_17
4670x0002868C SPI_PS_INPUT_CNTL_18
4680x00028690 SPI_PS_INPUT_CNTL_19
4690x00028694 SPI_PS_INPUT_CNTL_20
4700x00028698 SPI_PS_INPUT_CNTL_21
4710x0002869C SPI_PS_INPUT_CNTL_22
4720x000286A0 SPI_PS_INPUT_CNTL_23
4730x000286A4 SPI_PS_INPUT_CNTL_24
4740x000286A8 SPI_PS_INPUT_CNTL_25
4750x000286AC SPI_PS_INPUT_CNTL_26
4760x000286B0 SPI_PS_INPUT_CNTL_27
4770x000286B4 SPI_PS_INPUT_CNTL_28
4780x000286B8 SPI_PS_INPUT_CNTL_29
4790x000286BC SPI_PS_INPUT_CNTL_30
4800x000286C0 SPI_PS_INPUT_CNTL_31
4810x000286CC SPI_PS_IN_CONTROL_0
4820x000286D0 SPI_PS_IN_CONTROL_1
4830x000286C4 SPI_VS_OUT_CONFIG
4840x00028614 SPI_VS_OUT_ID_0
4850x00028618 SPI_VS_OUT_ID_1
4860x0002861C SPI_VS_OUT_ID_2
4870x00028620 SPI_VS_OUT_ID_3
4880x00028624 SPI_VS_OUT_ID_4
4890x00028628 SPI_VS_OUT_ID_5
4900x0002862C SPI_VS_OUT_ID_6
4910x00028630 SPI_VS_OUT_ID_7
4920x00028634 SPI_VS_OUT_ID_8
4930x00028638 SPI_VS_OUT_ID_9
4940x00028438 SX_ALPHA_REF
4950x00028410 SX_ALPHA_TEST_CONTROL
4960x00028350 SX_MISC
4970x0000A020 SMX_DC_CTL0
4980x0000A024 SMX_DC_CTL1
4990x0000A028 SMX_DC_CTL2
5000x00009608 TC_CNTL
5010x00009604 TC_INVALIDATE
5020x00009490 TD_CNTL
5030x00009400 TD_FILTER4
5040x00009404 TD_FILTER4_1
5050x00009408 TD_FILTER4_2
5060x0000940C TD_FILTER4_3
5070x00009410 TD_FILTER4_4
5080x00009414 TD_FILTER4_5
5090x00009418 TD_FILTER4_6
5100x0000941C TD_FILTER4_7
5110x00009420 TD_FILTER4_8
5120x00009424 TD_FILTER4_9
5130x00009428 TD_FILTER4_10
5140x0000942C TD_FILTER4_11
5150x00009430 TD_FILTER4_12
5160x00009434 TD_FILTER4_13
5170x00009438 TD_FILTER4_14
5180x0000943C TD_FILTER4_15
5190x00009440 TD_FILTER4_16
5200x00009444 TD_FILTER4_17
5210x00009448 TD_FILTER4_18
5220x0000944C TD_FILTER4_19
5230x00009450 TD_FILTER4_20
5240x00009454 TD_FILTER4_21
5250x00009458 TD_FILTER4_22
5260x0000945C TD_FILTER4_23
5270x00009460 TD_FILTER4_24
5280x00009464 TD_FILTER4_25
5290x00009468 TD_FILTER4_26
5300x0000946C TD_FILTER4_27
5310x00009470 TD_FILTER4_28
5320x00009474 TD_FILTER4_29
5330x00009478 TD_FILTER4_30
5340x0000947C TD_FILTER4_31
5350x00009480 TD_FILTER4_32
5360x00009484 TD_FILTER4_33
5370x00009488 TD_FILTER4_34
5380x0000948C TD_FILTER4_35
5390x0000A80C TD_GS_SAMPLER0_BORDER_ALPHA
5400x0000A81C TD_GS_SAMPLER1_BORDER_ALPHA
5410x0000A82C TD_GS_SAMPLER2_BORDER_ALPHA
5420x0000A83C TD_GS_SAMPLER3_BORDER_ALPHA
5430x0000A84C TD_GS_SAMPLER4_BORDER_ALPHA
5440x0000A85C TD_GS_SAMPLER5_BORDER_ALPHA
5450x0000A86C TD_GS_SAMPLER6_BORDER_ALPHA
5460x0000A87C TD_GS_SAMPLER7_BORDER_ALPHA
5470x0000A88C TD_GS_SAMPLER8_BORDER_ALPHA
5480x0000A89C TD_GS_SAMPLER9_BORDER_ALPHA
5490x0000A8AC TD_GS_SAMPLER10_BORDER_ALPHA
5500x0000A8BC TD_GS_SAMPLER11_BORDER_ALPHA
5510x0000A8CC TD_GS_SAMPLER12_BORDER_ALPHA
5520x0000A8DC TD_GS_SAMPLER13_BORDER_ALPHA
5530x0000A8EC TD_GS_SAMPLER14_BORDER_ALPHA
5540x0000A8FC TD_GS_SAMPLER15_BORDER_ALPHA
5550x0000A90C TD_GS_SAMPLER16_BORDER_ALPHA
5560x0000A91C TD_GS_SAMPLER17_BORDER_ALPHA
5570x0000A808 TD_GS_SAMPLER0_BORDER_BLUE
5580x0000A818 TD_GS_SAMPLER1_BORDER_BLUE
5590x0000A828 TD_GS_SAMPLER2_BORDER_BLUE
5600x0000A838 TD_GS_SAMPLER3_BORDER_BLUE
5610x0000A848 TD_GS_SAMPLER4_BORDER_BLUE
5620x0000A858 TD_GS_SAMPLER5_BORDER_BLUE
5630x0000A868 TD_GS_SAMPLER6_BORDER_BLUE
5640x0000A878 TD_GS_SAMPLER7_BORDER_BLUE
5650x0000A888 TD_GS_SAMPLER8_BORDER_BLUE
5660x0000A898 TD_GS_SAMPLER9_BORDER_BLUE
5670x0000A8A8 TD_GS_SAMPLER10_BORDER_BLUE
5680x0000A8B8 TD_GS_SAMPLER11_BORDER_BLUE
5690x0000A8C8 TD_GS_SAMPLER12_BORDER_BLUE
5700x0000A8D8 TD_GS_SAMPLER13_BORDER_BLUE
5710x0000A8E8 TD_GS_SAMPLER14_BORDER_BLUE
5720x0000A8F8 TD_GS_SAMPLER15_BORDER_BLUE
5730x0000A908 TD_GS_SAMPLER16_BORDER_BLUE
5740x0000A918 TD_GS_SAMPLER17_BORDER_BLUE
5750x0000A804 TD_GS_SAMPLER0_BORDER_GREEN
5760x0000A814 TD_GS_SAMPLER1_BORDER_GREEN
5770x0000A824 TD_GS_SAMPLER2_BORDER_GREEN
5780x0000A834 TD_GS_SAMPLER3_BORDER_GREEN
5790x0000A844 TD_GS_SAMPLER4_BORDER_GREEN
5800x0000A854 TD_GS_SAMPLER5_BORDER_GREEN
5810x0000A864 TD_GS_SAMPLER6_BORDER_GREEN
5820x0000A874 TD_GS_SAMPLER7_BORDER_GREEN
5830x0000A884 TD_GS_SAMPLER8_BORDER_GREEN
5840x0000A894 TD_GS_SAMPLER9_BORDER_GREEN
5850x0000A8A4 TD_GS_SAMPLER10_BORDER_GREEN
5860x0000A8B4 TD_GS_SAMPLER11_BORDER_GREEN
5870x0000A8C4 TD_GS_SAMPLER12_BORDER_GREEN
5880x0000A8D4 TD_GS_SAMPLER13_BORDER_GREEN
5890x0000A8E4 TD_GS_SAMPLER14_BORDER_GREEN
5900x0000A8F4 TD_GS_SAMPLER15_BORDER_GREEN
5910x0000A904 TD_GS_SAMPLER16_BORDER_GREEN
5920x0000A914 TD_GS_SAMPLER17_BORDER_GREEN
5930x0000A800 TD_GS_SAMPLER0_BORDER_RED
5940x0000A810 TD_GS_SAMPLER1_BORDER_RED
5950x0000A820 TD_GS_SAMPLER2_BORDER_RED
5960x0000A830 TD_GS_SAMPLER3_BORDER_RED
5970x0000A840 TD_GS_SAMPLER4_BORDER_RED
5980x0000A850 TD_GS_SAMPLER5_BORDER_RED
5990x0000A860 TD_GS_SAMPLER6_BORDER_RED
6000x0000A870 TD_GS_SAMPLER7_BORDER_RED
6010x0000A880 TD_GS_SAMPLER8_BORDER_RED
6020x0000A890 TD_GS_SAMPLER9_BORDER_RED
6030x0000A8A0 TD_GS_SAMPLER10_BORDER_RED
6040x0000A8B0 TD_GS_SAMPLER11_BORDER_RED
6050x0000A8C0 TD_GS_SAMPLER12_BORDER_RED
6060x0000A8D0 TD_GS_SAMPLER13_BORDER_RED
6070x0000A8E0 TD_GS_SAMPLER14_BORDER_RED
6080x0000A8F0 TD_GS_SAMPLER15_BORDER_RED
6090x0000A900 TD_GS_SAMPLER16_BORDER_RED
6100x0000A910 TD_GS_SAMPLER17_BORDER_RED
6110x0000A40C TD_PS_SAMPLER0_BORDER_ALPHA
6120x0000A41C TD_PS_SAMPLER1_BORDER_ALPHA
6130x0000A42C TD_PS_SAMPLER2_BORDER_ALPHA
6140x0000A43C TD_PS_SAMPLER3_BORDER_ALPHA
6150x0000A44C TD_PS_SAMPLER4_BORDER_ALPHA
6160x0000A45C TD_PS_SAMPLER5_BORDER_ALPHA
6170x0000A46C TD_PS_SAMPLER6_BORDER_ALPHA
6180x0000A47C TD_PS_SAMPLER7_BORDER_ALPHA
6190x0000A48C TD_PS_SAMPLER8_BORDER_ALPHA
6200x0000A49C TD_PS_SAMPLER9_BORDER_ALPHA
6210x0000A4AC TD_PS_SAMPLER10_BORDER_ALPHA
6220x0000A4BC TD_PS_SAMPLER11_BORDER_ALPHA
6230x0000A4CC TD_PS_SAMPLER12_BORDER_ALPHA
6240x0000A4DC TD_PS_SAMPLER13_BORDER_ALPHA
6250x0000A4EC TD_PS_SAMPLER14_BORDER_ALPHA
6260x0000A4FC TD_PS_SAMPLER15_BORDER_ALPHA
6270x0000A50C TD_PS_SAMPLER16_BORDER_ALPHA
6280x0000A51C TD_PS_SAMPLER17_BORDER_ALPHA
6290x0000A408 TD_PS_SAMPLER0_BORDER_BLUE
6300x0000A418 TD_PS_SAMPLER1_BORDER_BLUE
6310x0000A428 TD_PS_SAMPLER2_BORDER_BLUE
6320x0000A438 TD_PS_SAMPLER3_BORDER_BLUE
6330x0000A448 TD_PS_SAMPLER4_BORDER_BLUE
6340x0000A458 TD_PS_SAMPLER5_BORDER_BLUE
6350x0000A468 TD_PS_SAMPLER6_BORDER_BLUE
6360x0000A478 TD_PS_SAMPLER7_BORDER_BLUE
6370x0000A488 TD_PS_SAMPLER8_BORDER_BLUE
6380x0000A498 TD_PS_SAMPLER9_BORDER_BLUE
6390x0000A4A8 TD_PS_SAMPLER10_BORDER_BLUE
6400x0000A4B8 TD_PS_SAMPLER11_BORDER_BLUE
6410x0000A4C8 TD_PS_SAMPLER12_BORDER_BLUE
6420x0000A4D8 TD_PS_SAMPLER13_BORDER_BLUE
6430x0000A4E8 TD_PS_SAMPLER14_BORDER_BLUE
6440x0000A4F8 TD_PS_SAMPLER15_BORDER_BLUE
6450x0000A508 TD_PS_SAMPLER16_BORDER_BLUE
6460x0000A518 TD_PS_SAMPLER17_BORDER_BLUE
6470x0000A404 TD_PS_SAMPLER0_BORDER_GREEN
6480x0000A414 TD_PS_SAMPLER1_BORDER_GREEN
6490x0000A424 TD_PS_SAMPLER2_BORDER_GREEN
6500x0000A434 TD_PS_SAMPLER3_BORDER_GREEN
6510x0000A444 TD_PS_SAMPLER4_BORDER_GREEN
6520x0000A454 TD_PS_SAMPLER5_BORDER_GREEN
6530x0000A464 TD_PS_SAMPLER6_BORDER_GREEN
6540x0000A474 TD_PS_SAMPLER7_BORDER_GREEN
6550x0000A484 TD_PS_SAMPLER8_BORDER_GREEN
6560x0000A494 TD_PS_SAMPLER9_BORDER_GREEN
6570x0000A4A4 TD_PS_SAMPLER10_BORDER_GREEN
6580x0000A4B4 TD_PS_SAMPLER11_BORDER_GREEN
6590x0000A4C4 TD_PS_SAMPLER12_BORDER_GREEN
6600x0000A4D4 TD_PS_SAMPLER13_BORDER_GREEN
6610x0000A4E4 TD_PS_SAMPLER14_BORDER_GREEN
6620x0000A4F4 TD_PS_SAMPLER15_BORDER_GREEN
6630x0000A504 TD_PS_SAMPLER16_BORDER_GREEN
6640x0000A514 TD_PS_SAMPLER17_BORDER_GREEN
6650x0000A400 TD_PS_SAMPLER0_BORDER_RED
6660x0000A410 TD_PS_SAMPLER1_BORDER_RED
6670x0000A420 TD_PS_SAMPLER2_BORDER_RED
6680x0000A430 TD_PS_SAMPLER3_BORDER_RED
6690x0000A440 TD_PS_SAMPLER4_BORDER_RED
6700x0000A450 TD_PS_SAMPLER5_BORDER_RED
6710x0000A460 TD_PS_SAMPLER6_BORDER_RED
6720x0000A470 TD_PS_SAMPLER7_BORDER_RED
6730x0000A480 TD_PS_SAMPLER8_BORDER_RED
6740x0000A490 TD_PS_SAMPLER9_BORDER_RED
6750x0000A4A0 TD_PS_SAMPLER10_BORDER_RED
6760x0000A4B0 TD_PS_SAMPLER11_BORDER_RED
6770x0000A4C0 TD_PS_SAMPLER12_BORDER_RED
6780x0000A4D0 TD_PS_SAMPLER13_BORDER_RED
6790x0000A4E0 TD_PS_SAMPLER14_BORDER_RED
6800x0000A4F0 TD_PS_SAMPLER15_BORDER_RED
6810x0000A500 TD_PS_SAMPLER16_BORDER_RED
6820x0000A510 TD_PS_SAMPLER17_BORDER_RED
6830x0000AA00 TD_PS_SAMPLER0_CLEARTYPE_KERNEL
6840x0000AA04 TD_PS_SAMPLER1_CLEARTYPE_KERNEL
6850x0000AA08 TD_PS_SAMPLER2_CLEARTYPE_KERNEL
6860x0000AA0C TD_PS_SAMPLER3_CLEARTYPE_KERNEL
6870x0000AA10 TD_PS_SAMPLER4_CLEARTYPE_KERNEL
6880x0000AA14 TD_PS_SAMPLER5_CLEARTYPE_KERNEL
6890x0000AA18 TD_PS_SAMPLER6_CLEARTYPE_KERNEL
6900x0000AA1C TD_PS_SAMPLER7_CLEARTYPE_KERNEL
6910x0000AA20 TD_PS_SAMPLER8_CLEARTYPE_KERNEL
6920x0000AA24 TD_PS_SAMPLER9_CLEARTYPE_KERNEL
6930x0000AA28 TD_PS_SAMPLER10_CLEARTYPE_KERNEL
6940x0000AA2C TD_PS_SAMPLER11_CLEARTYPE_KERNEL
6950x0000AA30 TD_PS_SAMPLER12_CLEARTYPE_KERNEL
6960x0000AA34 TD_PS_SAMPLER13_CLEARTYPE_KERNEL
6970x0000AA38 TD_PS_SAMPLER14_CLEARTYPE_KERNEL
6980x0000AA3C TD_PS_SAMPLER15_CLEARTYPE_KERNEL
6990x0000AA40 TD_PS_SAMPLER16_CLEARTYPE_KERNEL
7000x0000AA44 TD_PS_SAMPLER17_CLEARTYPE_KERNEL
7010x0000A60C TD_VS_SAMPLER0_BORDER_ALPHA
7020x0000A61C TD_VS_SAMPLER1_BORDER_ALPHA
7030x0000A62C TD_VS_SAMPLER2_BORDER_ALPHA
7040x0000A63C TD_VS_SAMPLER3_BORDER_ALPHA
7050x0000A64C TD_VS_SAMPLER4_BORDER_ALPHA
7060x0000A65C TD_VS_SAMPLER5_BORDER_ALPHA
7070x0000A66C TD_VS_SAMPLER6_BORDER_ALPHA
7080x0000A67C TD_VS_SAMPLER7_BORDER_ALPHA
7090x0000A68C TD_VS_SAMPLER8_BORDER_ALPHA
7100x0000A69C TD_VS_SAMPLER9_BORDER_ALPHA
7110x0000A6AC TD_VS_SAMPLER10_BORDER_ALPHA
7120x0000A6BC TD_VS_SAMPLER11_BORDER_ALPHA
7130x0000A6CC TD_VS_SAMPLER12_BORDER_ALPHA
7140x0000A6DC TD_VS_SAMPLER13_BORDER_ALPHA
7150x0000A6EC TD_VS_SAMPLER14_BORDER_ALPHA
7160x0000A6FC TD_VS_SAMPLER15_BORDER_ALPHA
7170x0000A70C TD_VS_SAMPLER16_BORDER_ALPHA
7180x0000A71C TD_VS_SAMPLER17_BORDER_ALPHA
7190x0000A608 TD_VS_SAMPLER0_BORDER_BLUE
7200x0000A618 TD_VS_SAMPLER1_BORDER_BLUE
7210x0000A628 TD_VS_SAMPLER2_BORDER_BLUE
7220x0000A638 TD_VS_SAMPLER3_BORDER_BLUE
7230x0000A648 TD_VS_SAMPLER4_BORDER_BLUE
7240x0000A658 TD_VS_SAMPLER5_BORDER_BLUE
7250x0000A668 TD_VS_SAMPLER6_BORDER_BLUE
7260x0000A678 TD_VS_SAMPLER7_BORDER_BLUE
7270x0000A688 TD_VS_SAMPLER8_BORDER_BLUE
7280x0000A698 TD_VS_SAMPLER9_BORDER_BLUE
7290x0000A6A8 TD_VS_SAMPLER10_BORDER_BLUE
7300x0000A6B8 TD_VS_SAMPLER11_BORDER_BLUE
7310x0000A6C8 TD_VS_SAMPLER12_BORDER_BLUE
7320x0000A6D8 TD_VS_SAMPLER13_BORDER_BLUE
7330x0000A6E8 TD_VS_SAMPLER14_BORDER_BLUE
7340x0000A6F8 TD_VS_SAMPLER15_BORDER_BLUE
7350x0000A708 TD_VS_SAMPLER16_BORDER_BLUE
7360x0000A718 TD_VS_SAMPLER17_BORDER_BLUE
7370x0000A604 TD_VS_SAMPLER0_BORDER_GREEN
7380x0000A614 TD_VS_SAMPLER1_BORDER_GREEN
7390x0000A624 TD_VS_SAMPLER2_BORDER_GREEN
7400x0000A634 TD_VS_SAMPLER3_BORDER_GREEN
7410x0000A644 TD_VS_SAMPLER4_BORDER_GREEN
7420x0000A654 TD_VS_SAMPLER5_BORDER_GREEN
7430x0000A664 TD_VS_SAMPLER6_BORDER_GREEN
7440x0000A674 TD_VS_SAMPLER7_BORDER_GREEN
7450x0000A684 TD_VS_SAMPLER8_BORDER_GREEN
7460x0000A694 TD_VS_SAMPLER9_BORDER_GREEN
7470x0000A6A4 TD_VS_SAMPLER10_BORDER_GREEN
7480x0000A6B4 TD_VS_SAMPLER11_BORDER_GREEN
7490x0000A6C4 TD_VS_SAMPLER12_BORDER_GREEN
7500x0000A6D4 TD_VS_SAMPLER13_BORDER_GREEN
7510x0000A6E4 TD_VS_SAMPLER14_BORDER_GREEN
7520x0000A6F4 TD_VS_SAMPLER15_BORDER_GREEN
7530x0000A704 TD_VS_SAMPLER16_BORDER_GREEN
7540x0000A714 TD_VS_SAMPLER17_BORDER_GREEN
7550x0000A600 TD_VS_SAMPLER0_BORDER_RED
7560x0000A610 TD_VS_SAMPLER1_BORDER_RED
7570x0000A620 TD_VS_SAMPLER2_BORDER_RED
7580x0000A630 TD_VS_SAMPLER3_BORDER_RED
7590x0000A640 TD_VS_SAMPLER4_BORDER_RED
7600x0000A650 TD_VS_SAMPLER5_BORDER_RED
7610x0000A660 TD_VS_SAMPLER6_BORDER_RED
7620x0000A670 TD_VS_SAMPLER7_BORDER_RED
7630x0000A680 TD_VS_SAMPLER8_BORDER_RED
7640x0000A690 TD_VS_SAMPLER9_BORDER_RED
7650x0000A6A0 TD_VS_SAMPLER10_BORDER_RED
7660x0000A6B0 TD_VS_SAMPLER11_BORDER_RED
7670x0000A6C0 TD_VS_SAMPLER12_BORDER_RED
7680x0000A6D0 TD_VS_SAMPLER13_BORDER_RED
7690x0000A6E0 TD_VS_SAMPLER14_BORDER_RED
7700x0000A6F0 TD_VS_SAMPLER15_BORDER_RED
7710x0000A700 TD_VS_SAMPLER16_BORDER_RED
7720x0000A710 TD_VS_SAMPLER17_BORDER_RED
7730x00009508 TA_CNTL_AUX
7740x0002802C DB_DEPTH_CLEAR
7750x00028D24 DB_HTILE_SURFACE
7760x00028D34 DB_PREFETCH_LIMIT
7770x00028D30 DB_PRELOAD_CONTROL
7780x00028D0C DB_RENDER_CONTROL
7790x00028D10 DB_RENDER_OVERRIDE
7800x0002880C DB_SHADER_CONTROL
7810x00028D2C DB_SRESULTS_COMPARE_STATE1
7820x00028430 DB_STENCILREFMASK
7830x00028434 DB_STENCILREFMASK_BF
7840x00028028 DB_STENCIL_CLEAR
7850x00028780 CB_BLEND0_CONTROL
7860x00028784 CB_BLEND1_CONTROL
7870x00028788 CB_BLEND2_CONTROL
7880x0002878C CB_BLEND3_CONTROL
7890x00028790 CB_BLEND4_CONTROL
7900x00028794 CB_BLEND5_CONTROL
7910x00028798 CB_BLEND6_CONTROL
7920x0002879C CB_BLEND7_CONTROL
7930x00028804 CB_BLEND_CONTROL
7940x00028420 CB_BLEND_ALPHA
7950x0002841C CB_BLEND_BLUE
7960x00028418 CB_BLEND_GREEN
7970x00028414 CB_BLEND_RED
7980x0002812C CB_CLEAR_ALPHA
7990x00028128 CB_CLEAR_BLUE
8000x00028124 CB_CLEAR_GREEN
8010x00028120 CB_CLEAR_RED
8020x00028C30 CB_CLRCMP_CONTROL
8030x00028C38 CB_CLRCMP_DST
8040x00028C3C CB_CLRCMP_MSK
8050x00028C34 CB_CLRCMP_SRC
8060x00028100 CB_COLOR0_MASK
8070x00028104 CB_COLOR1_MASK
8080x00028108 CB_COLOR2_MASK
8090x0002810C CB_COLOR3_MASK
8100x00028110 CB_COLOR4_MASK
8110x00028114 CB_COLOR5_MASK
8120x00028118 CB_COLOR6_MASK
8130x0002811C CB_COLOR7_MASK
8140x00028080 CB_COLOR0_VIEW
8150x00028084 CB_COLOR1_VIEW
8160x00028088 CB_COLOR2_VIEW
8170x0002808C CB_COLOR3_VIEW
8180x00028090 CB_COLOR4_VIEW
8190x00028094 CB_COLOR5_VIEW
8200x00028098 CB_COLOR6_VIEW
8210x0002809C CB_COLOR7_VIEW
8220x00028808 CB_COLOR_CONTROL
8230x0002842C CB_FOG_BLUE
8240x00028428 CB_FOG_GREEN
8250x00028424 CB_FOG_RED
8260x00008040 WAIT_UNTIL
8270x00008950 CC_GC_SHADER_PIPE_CONFIG
8280x00008954 GC_USER_SHADER_PIPE_CONFIG
8290x00009714 VC_ENHANCE
8300x00009830 DB_DEBUG
8310x00009838 DB_WATERMARKS
8320x00028D28 DB_SRESULTS_COMPARE_STATE0
8330x00028D44 DB_ALPHA_TO_MASK
8340x00009504 TA_CNTL
8350x00009700 VC_CNTL
8360x00009718 VC_CONFIG
8370x0000A02C SMX_DC_MC_INTF_CTL
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index c9320e727986..3ecd138815d8 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -516,15 +516,19 @@ static void rv770_gpu_init(struct radeon_device *rdev)
516 switch (rdev->config.rv770.max_tile_pipes) { 516 switch (rdev->config.rv770.max_tile_pipes) {
517 case 1: 517 case 1:
518 gb_tiling_config |= PIPE_TILING(0); 518 gb_tiling_config |= PIPE_TILING(0);
519 rdev->config.rv770.tiling_npipes = 1;
519 break; 520 break;
520 case 2: 521 case 2:
521 gb_tiling_config |= PIPE_TILING(1); 522 gb_tiling_config |= PIPE_TILING(1);
523 rdev->config.rv770.tiling_npipes = 2;
522 break; 524 break;
523 case 4: 525 case 4:
524 gb_tiling_config |= PIPE_TILING(2); 526 gb_tiling_config |= PIPE_TILING(2);
527 rdev->config.rv770.tiling_npipes = 4;
525 break; 528 break;
526 case 8: 529 case 8:
527 gb_tiling_config |= PIPE_TILING(3); 530 gb_tiling_config |= PIPE_TILING(3);
531 rdev->config.rv770.tiling_npipes = 8;
528 break; 532 break;
529 default: 533 default:
530 break; 534 break;
@@ -534,8 +538,10 @@ static void rv770_gpu_init(struct radeon_device *rdev)
534 gb_tiling_config |= BANK_TILING(1); 538 gb_tiling_config |= BANK_TILING(1);
535 else 539 else
536 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 540 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
541 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
537 542
538 gb_tiling_config |= GROUP_SIZE(0); 543 gb_tiling_config |= GROUP_SIZE(0);
544 rdev->config.rv770.tiling_group_size = 256;
539 545
540 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { 546 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
541 gb_tiling_config |= ROW_TILING(3); 547 gb_tiling_config |= ROW_TILING(3);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 02:38:27 -0500