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authorDavid Woodhouse <David.Woodhouse@intel.com>2012-11-21 05:38:13 -0500
committerDavid Woodhouse <David.Woodhouse@intel.com>2012-11-21 05:38:13 -0500
commit851462444d421c223965b12b836bef63da61b57f (patch)
tree495baa14e638817941496c36e1443aed7dae0ea0 /drivers/gpu/drm/radeon
parent5a6ea4af0907f995dc06df21a9c9ef764c7cd3bc (diff)
parent6924d99fcdf1a688538a3cdebd1f135c22eec191 (diff)
Merge branch 'for-3.7' of git://git.infradead.org/users/dedekind/l2-mtd
Conflicts: drivers/mtd/nand/nand_base.c
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c8
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c5
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c7
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c3
-rw-r--r--drivers/gpu/drm/radeon/ni.c57
-rw-r--r--drivers/gpu/drm/radeon/nid.h1
-rw-r--r--drivers/gpu/drm/radeon/r600.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon.h14
-rw-r--r--drivers/gpu/drm/radeon/radeon_acpi.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_atpx_handler.c12
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c28
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c64
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c386
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c18
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c22
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c228
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c19
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c2
-rw-r--r--drivers/gpu/drm/radeon/si.c54
21 files changed, 658 insertions, 298 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 96184d02c8d9..2e566e123e9e 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1690,10 +1690,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1690 } 1690 }
1691 /* all other cases */ 1691 /* all other cases */
1692 pll_in_use = radeon_get_pll_use_mask(crtc); 1692 pll_in_use = radeon_get_pll_use_mask(crtc);
1693 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1694 return ATOM_PPLL2;
1695 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1693 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1696 return ATOM_PPLL1; 1694 return ATOM_PPLL1;
1695 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1696 return ATOM_PPLL2;
1697 DRM_ERROR("unable to allocate a PPLL\n"); 1697 DRM_ERROR("unable to allocate a PPLL\n");
1698 return ATOM_PPLL_INVALID; 1698 return ATOM_PPLL_INVALID;
1699 } else { 1699 } else {
@@ -1715,10 +1715,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1715 } 1715 }
1716 /* all other cases */ 1716 /* all other cases */
1717 pll_in_use = radeon_get_pll_use_mask(crtc); 1717 pll_in_use = radeon_get_pll_use_mask(crtc);
1718 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1719 return ATOM_PPLL2;
1720 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1718 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1721 return ATOM_PPLL1; 1719 return ATOM_PPLL1;
1720 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1721 return ATOM_PPLL2;
1722 DRM_ERROR("unable to allocate a PPLL\n"); 1722 DRM_ERROR("unable to allocate a PPLL\n");
1723 return ATOM_PPLL_INVALID; 1723 return ATOM_PPLL_INVALID;
1724 } else { 1724 } else {
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 49cbb3795a10..ba498f8e47a2 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -184,6 +184,7 @@ void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
184 struct radeon_backlight_privdata *pdata; 184 struct radeon_backlight_privdata *pdata;
185 struct radeon_encoder_atom_dig *dig; 185 struct radeon_encoder_atom_dig *dig;
186 u8 backlight_level; 186 u8 backlight_level;
187 char bl_name[16];
187 188
188 if (!radeon_encoder->enc_priv) 189 if (!radeon_encoder->enc_priv)
189 return; 190 return;
@@ -203,7 +204,9 @@ void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
203 memset(&props, 0, sizeof(props)); 204 memset(&props, 0, sizeof(props));
204 props.max_brightness = RADEON_MAX_BL_LEVEL; 205 props.max_brightness = RADEON_MAX_BL_LEVEL;
205 props.type = BACKLIGHT_RAW; 206 props.type = BACKLIGHT_RAW;
206 bd = backlight_device_register("radeon_bl", &drm_connector->kdev, 207 snprintf(bl_name, sizeof(bl_name),
208 "radeon_bl%d", dev->primary->index);
209 bd = backlight_device_register(bl_name, &drm_connector->kdev,
207 pdata, &radeon_atom_backlight_ops, &props); 210 pdata, &radeon_atom_backlight_ops, &props);
208 if (IS_ERR(bd)) { 211 if (IS_ERR(bd)) {
209 DRM_ERROR("Backlight registration failed\n"); 212 DRM_ERROR("Backlight registration failed\n");
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index a1f49c5fd74b..14313ad43b76 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3431,9 +3431,14 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3431 if (!(mask & DRM_PCIE_SPEED_50)) 3431 if (!(mask & DRM_PCIE_SPEED_50))
3432 return; 3432 return;
3433 3433
3434 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3435 if (speed_cntl & LC_CURRENT_DATA_RATE) {
3436 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3437 return;
3438 }
3439
3434 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 3440 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3435 3441
3436 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3437 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || 3442 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3438 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 3443 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3439 3444
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 573ed1bc6cf7..95e6318b6268 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -264,7 +264,7 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
264 /* macro tile width & height */ 264 /* macro tile width & height */
265 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; 265 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
266 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; 266 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
267 mtileb = (palign / 8) * (halign / 8) * tileb;; 267 mtileb = (palign / 8) * (halign / 8) * tileb;
268 mtile_pr = surf->nbx / palign; 268 mtile_pr = surf->nbx / palign;
269 mtile_ps = (mtile_pr * surf->nby) / halign; 269 mtile_ps = (mtile_pr * surf->nby) / halign;
270 surf->layer_size = mtile_ps * mtileb * slice_pt; 270 surf->layer_size = mtile_ps * mtileb * slice_pt;
@@ -2829,6 +2829,7 @@ static bool evergreen_vm_reg_valid(u32 reg)
2829 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS: 2829 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS:
2830 return true; 2830 return true;
2831 default: 2831 default:
2832 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2832 return false; 2833 return false;
2833 } 2834 }
2834} 2835}
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 8bcb554ea0c5..81e6a568c29d 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -770,9 +770,13 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
770 WREG32(0x15DC, 0); 770 WREG32(0x15DC, 0);
771 771
772 /* empty context1-7 */ 772 /* empty context1-7 */
773 /* Assign the pt base to something valid for now; the pts used for
774 * the VMs are determined by the application and setup and assigned
775 * on the fly in the vm part of radeon_gart.c
776 */
773 for (i = 1; i < 8; i++) { 777 for (i = 1; i < 8; i++) {
774 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); 778 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
775 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0); 779 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
776 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 780 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
777 rdev->gart.table_addr >> 12); 781 rdev->gart.table_addr >> 12);
778 } 782 }
@@ -1534,26 +1538,31 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
1534{ 1538{
1535 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index]; 1539 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
1536 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); 1540 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
1537 int i;
1538 1541
1539 radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, 1 + count * 2)); 1542 while (count) {
1540 radeon_ring_write(ring, pe); 1543 unsigned ndw = 1 + count * 2;
1541 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 1544 if (ndw > 0x3FFF)
1542 for (i = 0; i < count; ++i) { 1545 ndw = 0x3FFF;
1543 uint64_t value = 0; 1546
1544 if (flags & RADEON_VM_PAGE_SYSTEM) { 1547 radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw));
1545 value = radeon_vm_map_gart(rdev, addr); 1548 radeon_ring_write(ring, pe);
1546 value &= 0xFFFFFFFFFFFFF000ULL; 1549 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1547 addr += incr; 1550 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
1548 1551 uint64_t value = 0;
1549 } else if (flags & RADEON_VM_PAGE_VALID) { 1552 if (flags & RADEON_VM_PAGE_SYSTEM) {
1550 value = addr; 1553 value = radeon_vm_map_gart(rdev, addr);
1551 addr += incr; 1554 value &= 0xFFFFFFFFFFFFF000ULL;
1552 } 1555 addr += incr;
1556
1557 } else if (flags & RADEON_VM_PAGE_VALID) {
1558 value = addr;
1559 addr += incr;
1560 }
1553 1561
1554 value |= r600_flags; 1562 value |= r600_flags;
1555 radeon_ring_write(ring, value); 1563 radeon_ring_write(ring, value);
1556 radeon_ring_write(ring, upper_32_bits(value)); 1564 radeon_ring_write(ring, upper_32_bits(value));
1565 }
1557 } 1566 }
1558} 1567}
1559 1568
@@ -1572,12 +1581,6 @@ void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
1572 if (vm == NULL) 1581 if (vm == NULL)
1573 return; 1582 return;
1574 1583
1575 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0));
1576 radeon_ring_write(ring, 0);
1577
1578 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0));
1579 radeon_ring_write(ring, vm->last_pfn);
1580
1581 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0)); 1584 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
1582 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 1585 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
1583 1586
@@ -1588,4 +1591,8 @@ void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
1588 /* bits 0-7 are the VM contexts0-7 */ 1591 /* bits 0-7 are the VM contexts0-7 */
1589 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); 1592 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
1590 radeon_ring_write(ring, 1 << vm->id); 1593 radeon_ring_write(ring, 1 << vm->id);
1594
1595 /* sync PFP to ME, otherwise we might get invalid PFP reads */
1596 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
1597 radeon_ring_write(ring, 0x0);
1591} 1598}
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 2423d1b5d385..cbef6815907a 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -502,6 +502,7 @@
502#define PACKET3_MPEG_INDEX 0x3A 502#define PACKET3_MPEG_INDEX 0x3A
503#define PACKET3_WAIT_REG_MEM 0x3C 503#define PACKET3_WAIT_REG_MEM 0x3C
504#define PACKET3_MEM_WRITE 0x3D 504#define PACKET3_MEM_WRITE 0x3D
505#define PACKET3_PFP_SYNC_ME 0x42
505#define PACKET3_SURFACE_SYNC 0x43 506#define PACKET3_SURFACE_SYNC 0x43
506# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 507# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
507# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 508# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 70c800ff6190..cda280d157da 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3703,6 +3703,12 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3703 if (!(mask & DRM_PCIE_SPEED_50)) 3703 if (!(mask & DRM_PCIE_SPEED_50))
3704 return; 3704 return;
3705 3705
3706 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3707 if (speed_cntl & LC_CURRENT_DATA_RATE) {
3708 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3709 return;
3710 }
3711
3706 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 3712 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3707 3713
3708 /* 55 nm r6xx asics */ 3714 /* 55 nm r6xx asics */
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b04c06444d8b..8c42d54c2e26 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -663,9 +663,14 @@ struct radeon_vm {
663 struct list_head list; 663 struct list_head list;
664 struct list_head va; 664 struct list_head va;
665 unsigned id; 665 unsigned id;
666 unsigned last_pfn; 666
667 u64 pd_gpu_addr; 667 /* contains the page directory */
668 struct radeon_sa_bo *sa_bo; 668 struct radeon_sa_bo *page_directory;
669 uint64_t pd_gpu_addr;
670
671 /* array of page tables, one for each page directory entry */
672 struct radeon_sa_bo **page_tables;
673
669 struct mutex mutex; 674 struct mutex mutex;
670 /* last fence for cs using this vm */ 675 /* last fence for cs using this vm */
671 struct radeon_fence *fence; 676 struct radeon_fence *fence;
@@ -1843,9 +1848,10 @@ extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size
1843 */ 1848 */
1844int radeon_vm_manager_init(struct radeon_device *rdev); 1849int radeon_vm_manager_init(struct radeon_device *rdev);
1845void radeon_vm_manager_fini(struct radeon_device *rdev); 1850void radeon_vm_manager_fini(struct radeon_device *rdev);
1846int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 1851void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1847void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 1852void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1848int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 1853int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
1854void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
1849struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 1855struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
1850 struct radeon_vm *vm, int ring); 1856 struct radeon_vm *vm, int ring);
1851void radeon_vm_fence(struct radeon_device *rdev, 1857void radeon_vm_fence(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_acpi.c b/drivers/gpu/drm/radeon/radeon_acpi.c
index b0a5688c67f8..196d28d99570 100644
--- a/drivers/gpu/drm/radeon/radeon_acpi.c
+++ b/drivers/gpu/drm/radeon/radeon_acpi.c
@@ -201,7 +201,7 @@ static int radeon_atif_verify_interface(acpi_handle handle,
201 201
202 size = *(u16 *) info->buffer.pointer; 202 size = *(u16 *) info->buffer.pointer;
203 if (size < 12) { 203 if (size < 12) {
204 DRM_INFO("ATIF buffer is too small: %lu\n", size); 204 DRM_INFO("ATIF buffer is too small: %zu\n", size);
205 err = -EINVAL; 205 err = -EINVAL;
206 goto out; 206 goto out;
207 } 207 }
@@ -370,6 +370,7 @@ int radeon_atif_handler(struct radeon_device *rdev,
370 370
371 radeon_set_backlight_level(rdev, enc, req.backlight_level); 371 radeon_set_backlight_level(rdev, enc, req.backlight_level);
372 372
373#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
373 if (rdev->is_atom_bios) { 374 if (rdev->is_atom_bios) {
374 struct radeon_encoder_atom_dig *dig = enc->enc_priv; 375 struct radeon_encoder_atom_dig *dig = enc->enc_priv;
375 backlight_force_update(dig->bl_dev, 376 backlight_force_update(dig->bl_dev,
@@ -379,6 +380,7 @@ int radeon_atif_handler(struct radeon_device *rdev,
379 backlight_force_update(dig->bl_dev, 380 backlight_force_update(dig->bl_dev,
380 BACKLIGHT_UPDATE_HOTKEY); 381 BACKLIGHT_UPDATE_HOTKEY);
381 } 382 }
383#endif
382 } 384 }
383 } 385 }
384 /* TODO: check other events */ 386 /* TODO: check other events */
@@ -485,7 +487,7 @@ static int radeon_atcs_verify_interface(acpi_handle handle,
485 487
486 size = *(u16 *) info->buffer.pointer; 488 size = *(u16 *) info->buffer.pointer;
487 if (size < 8) { 489 if (size < 8) {
488 DRM_INFO("ATCS buffer is too small: %lu\n", size); 490 DRM_INFO("ATCS buffer is too small: %zu\n", size);
489 err = -EINVAL; 491 err = -EINVAL;
490 goto out; 492 goto out;
491 } 493 }
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index 582e99449c12..15f5ded65e0c 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -87,7 +87,7 @@ static union acpi_object *radeon_atpx_call(acpi_handle handle, int function,
87 atpx_arg_elements[1].integer.value = 0; 87 atpx_arg_elements[1].integer.value = 0;
88 } 88 }
89 89
90 status = acpi_evaluate_object(handle, "ATPX", &atpx_arg, &buffer); 90 status = acpi_evaluate_object(handle, NULL, &atpx_arg, &buffer);
91 91
92 /* Fail only if calling the method fails and ATPX is supported */ 92 /* Fail only if calling the method fails and ATPX is supported */
93 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 93 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
@@ -148,7 +148,7 @@ static int radeon_atpx_verify_interface(struct radeon_atpx *atpx)
148 148
149 size = *(u16 *) info->buffer.pointer; 149 size = *(u16 *) info->buffer.pointer;
150 if (size < 8) { 150 if (size < 8) {
151 printk("ATPX buffer is too small: %lu\n", size); 151 printk("ATPX buffer is too small: %zu\n", size);
152 err = -EINVAL; 152 err = -EINVAL;
153 goto out; 153 goto out;
154 } 154 }
@@ -352,9 +352,9 @@ static int radeon_atpx_switchto(enum vga_switcheroo_client_id id)
352} 352}
353 353
354/** 354/**
355 * radeon_atpx_switchto - switch to the requested GPU 355 * radeon_atpx_power_state - power down/up the requested GPU
356 * 356 *
357 * @id: GPU to switch to 357 * @id: GPU to power down/up
358 * @state: requested power state (0 = off, 1 = on) 358 * @state: requested power state (0 = off, 1 = on)
359 * 359 *
360 * Execute the necessary ATPX function to power down/up the discrete GPU 360 * Execute the necessary ATPX function to power down/up the discrete GPU
@@ -373,11 +373,11 @@ static int radeon_atpx_power_state(enum vga_switcheroo_client_id id,
373} 373}
374 374
375/** 375/**
376 * radeon_atpx_pci_probe_handle - look up the ATRM and ATPX handles 376 * radeon_atpx_pci_probe_handle - look up the ATPX handle
377 * 377 *
378 * @pdev: pci device 378 * @pdev: pci device
379 * 379 *
380 * Look up the ATPX and ATRM handles (all asics). 380 * Look up the ATPX handles (all asics).
381 * Returns true if the handles are found, false if not. 381 * Returns true if the handles are found, false if not.
382 */ 382 */
383static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev) 383static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 67cfc1795ecd..b884c362a8c2 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -941,7 +941,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
941 struct drm_mode_object *obj; 941 struct drm_mode_object *obj;
942 int i; 942 int i;
943 enum drm_connector_status ret = connector_status_disconnected; 943 enum drm_connector_status ret = connector_status_disconnected;
944 bool dret = false; 944 bool dret = false, broken_edid = false;
945 945
946 if (!force && radeon_check_hpd_status_unchanged(connector)) 946 if (!force && radeon_check_hpd_status_unchanged(connector))
947 return connector->status; 947 return connector->status;
@@ -965,6 +965,9 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
965 ret = connector_status_disconnected; 965 ret = connector_status_disconnected;
966 DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n", drm_get_connector_name(connector)); 966 DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n", drm_get_connector_name(connector));
967 radeon_connector->ddc_bus = NULL; 967 radeon_connector->ddc_bus = NULL;
968 } else {
969 ret = connector_status_connected;
970 broken_edid = true; /* defer use_digital to later */
968 } 971 }
969 } else { 972 } else {
970 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 973 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
@@ -1047,13 +1050,24 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
1047 1050
1048 encoder_funcs = encoder->helper_private; 1051 encoder_funcs = encoder->helper_private;
1049 if (encoder_funcs->detect) { 1052 if (encoder_funcs->detect) {
1050 if (ret != connector_status_connected) { 1053 if (!broken_edid) {
1051 ret = encoder_funcs->detect(encoder, connector); 1054 if (ret != connector_status_connected) {
1052 if (ret == connector_status_connected) { 1055 /* deal with analog monitors without DDC */
1053 radeon_connector->use_digital = false; 1056 ret = encoder_funcs->detect(encoder, connector);
1057 if (ret == connector_status_connected) {
1058 radeon_connector->use_digital = false;
1059 }
1060 if (ret != connector_status_disconnected)
1061 radeon_connector->detected_by_load = true;
1054 } 1062 }
1055 if (ret != connector_status_disconnected) 1063 } else {
1056 radeon_connector->detected_by_load = true; 1064 enum drm_connector_status lret;
1065 /* assume digital unless load detected otherwise */
1066 radeon_connector->use_digital = true;
1067 lret = encoder_funcs->detect(encoder, connector);
1068 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1069 if (lret == connector_status_connected)
1070 radeon_connector->use_digital = false;
1057 } 1071 }
1058 break; 1072 break;
1059 } 1073 }
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index cb7b7c062fef..41672cc563fb 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -478,6 +478,7 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
478 } 478 }
479 479
480out: 480out:
481 radeon_vm_add_to_lru(rdev, vm);
481 mutex_unlock(&vm->mutex); 482 mutex_unlock(&vm->mutex);
482 mutex_unlock(&rdev->vm_manager.lock); 483 mutex_unlock(&rdev->vm_manager.lock);
483 return r; 484 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 64a42647f08a..e2f5f888c374 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -355,6 +355,8 @@ int radeon_wb_init(struct radeon_device *rdev)
355 */ 355 */
356void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 356void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
357{ 357{
358 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
359
358 mc->vram_start = base; 360 mc->vram_start = base;
359 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { 361 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
360 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 362 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
@@ -368,8 +370,8 @@ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64
368 mc->mc_vram_size = mc->aper_size; 370 mc->mc_vram_size = mc->aper_size;
369 } 371 }
370 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 372 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
371 if (radeon_vram_limit && radeon_vram_limit < mc->real_vram_size) 373 if (limit && limit < mc->real_vram_size)
372 mc->real_vram_size = radeon_vram_limit; 374 mc->real_vram_size = limit;
373 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 375 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
374 mc->mc_vram_size >> 20, mc->vram_start, 376 mc->mc_vram_size >> 20, mc->vram_start,
375 mc->vram_end, mc->real_vram_size >> 20); 377 mc->vram_end, mc->real_vram_size >> 20);
@@ -835,6 +837,19 @@ static unsigned int radeon_vga_set_decode(void *cookie, bool state)
835} 837}
836 838
837/** 839/**
840 * radeon_check_pot_argument - check that argument is a power of two
841 *
842 * @arg: value to check
843 *
844 * Validates that a certain argument is a power of two (all asics).
845 * Returns true if argument is valid.
846 */
847static bool radeon_check_pot_argument(int arg)
848{
849 return (arg & (arg - 1)) == 0;
850}
851
852/**
838 * radeon_check_arguments - validate module params 853 * radeon_check_arguments - validate module params
839 * 854 *
840 * @rdev: radeon_device pointer 855 * @rdev: radeon_device pointer
@@ -845,52 +860,25 @@ static unsigned int radeon_vga_set_decode(void *cookie, bool state)
845static void radeon_check_arguments(struct radeon_device *rdev) 860static void radeon_check_arguments(struct radeon_device *rdev)
846{ 861{
847 /* vramlimit must be a power of two */ 862 /* vramlimit must be a power of two */
848 switch (radeon_vram_limit) { 863 if (!radeon_check_pot_argument(radeon_vram_limit)) {
849 case 0:
850 case 4:
851 case 8:
852 case 16:
853 case 32:
854 case 64:
855 case 128:
856 case 256:
857 case 512:
858 case 1024:
859 case 2048:
860 case 4096:
861 break;
862 default:
863 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 864 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
864 radeon_vram_limit); 865 radeon_vram_limit);
865 radeon_vram_limit = 0; 866 radeon_vram_limit = 0;
866 break;
867 } 867 }
868 radeon_vram_limit = radeon_vram_limit << 20; 868
869 /* gtt size must be power of two and greater or equal to 32M */ 869 /* gtt size must be power of two and greater or equal to 32M */
870 switch (radeon_gart_size) { 870 if (radeon_gart_size < 32) {
871 case 4:
872 case 8:
873 case 16:
874 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", 871 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
875 radeon_gart_size); 872 radeon_gart_size);
876 radeon_gart_size = 512; 873 radeon_gart_size = 512;
877 break; 874
878 case 32: 875 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
879 case 64:
880 case 128:
881 case 256:
882 case 512:
883 case 1024:
884 case 2048:
885 case 4096:
886 break;
887 default:
888 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 876 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
889 radeon_gart_size); 877 radeon_gart_size);
890 radeon_gart_size = 512; 878 radeon_gart_size = 512;
891 break;
892 } 879 }
893 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 880 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
881
894 /* AGP mode can only be -1, 1, 2, 4, 8 */ 882 /* AGP mode can only be -1, 1, 2, 4, 8 */
895 switch (radeon_agpmode) { 883 switch (radeon_agpmode) {
896 case -1: 884 case -1:
@@ -1018,6 +1006,10 @@ int radeon_device_init(struct radeon_device *rdev,
1018 return r; 1006 return r;
1019 /* initialize vm here */ 1007 /* initialize vm here */
1020 mutex_init(&rdev->vm_manager.lock); 1008 mutex_init(&rdev->vm_manager.lock);
1009 /* Adjust VM size here.
1010 * Currently set to 4GB ((1 << 20) 4k pages).
1011 * Max GPUVM size for cayman and SI is 40 bits.
1012 */
1021 rdev->vm_manager.max_pfn = 1 << 20; 1013 rdev->vm_manager.max_pfn = 1 << 20;
1022 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm); 1014 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1023 1015
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index f0c06d196b75..4debd60e5aa6 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -355,14 +355,13 @@ int radeon_gart_init(struct radeon_device *rdev)
355 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 355 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
356 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); 356 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
357 /* Allocate pages table */ 357 /* Allocate pages table */
358 rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages, 358 rdev->gart.pages = vzalloc(sizeof(void *) * rdev->gart.num_cpu_pages);
359 GFP_KERNEL);
360 if (rdev->gart.pages == NULL) { 359 if (rdev->gart.pages == NULL) {
361 radeon_gart_fini(rdev); 360 radeon_gart_fini(rdev);
362 return -ENOMEM; 361 return -ENOMEM;
363 } 362 }
364 rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) * 363 rdev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) *
365 rdev->gart.num_cpu_pages, GFP_KERNEL); 364 rdev->gart.num_cpu_pages);
366 if (rdev->gart.pages_addr == NULL) { 365 if (rdev->gart.pages_addr == NULL) {
367 radeon_gart_fini(rdev); 366 radeon_gart_fini(rdev);
368 return -ENOMEM; 367 return -ENOMEM;
@@ -388,8 +387,8 @@ void radeon_gart_fini(struct radeon_device *rdev)
388 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); 387 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
389 } 388 }
390 rdev->gart.ready = false; 389 rdev->gart.ready = false;
391 kfree(rdev->gart.pages); 390 vfree(rdev->gart.pages);
392 kfree(rdev->gart.pages_addr); 391 vfree(rdev->gart.pages_addr);
393 rdev->gart.pages = NULL; 392 rdev->gart.pages = NULL;
394 rdev->gart.pages_addr = NULL; 393 rdev->gart.pages_addr = NULL;
395 394
@@ -423,6 +422,18 @@ void radeon_gart_fini(struct radeon_device *rdev)
423 */ 422 */
424 423
425/** 424/**
425 * radeon_vm_num_pde - return the number of page directory entries
426 *
427 * @rdev: radeon_device pointer
428 *
429 * Calculate the number of page directory entries (cayman+).
430 */
431static unsigned radeon_vm_num_pdes(struct radeon_device *rdev)
432{
433 return rdev->vm_manager.max_pfn >> RADEON_VM_BLOCK_SIZE;
434}
435
436/**
426 * radeon_vm_directory_size - returns the size of the page directory in bytes 437 * radeon_vm_directory_size - returns the size of the page directory in bytes
427 * 438 *
428 * @rdev: radeon_device pointer 439 * @rdev: radeon_device pointer
@@ -431,7 +442,7 @@ void radeon_gart_fini(struct radeon_device *rdev)
431 */ 442 */
432static unsigned radeon_vm_directory_size(struct radeon_device *rdev) 443static unsigned radeon_vm_directory_size(struct radeon_device *rdev)
433{ 444{
434 return (rdev->vm_manager.max_pfn >> RADEON_VM_BLOCK_SIZE) * 8; 445 return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8);
435} 446}
436 447
437/** 448/**
@@ -451,11 +462,11 @@ int radeon_vm_manager_init(struct radeon_device *rdev)
451 462
452 if (!rdev->vm_manager.enabled) { 463 if (!rdev->vm_manager.enabled) {
453 /* allocate enough for 2 full VM pts */ 464 /* allocate enough for 2 full VM pts */
454 size = RADEON_GPU_PAGE_ALIGN(radeon_vm_directory_size(rdev)); 465 size = radeon_vm_directory_size(rdev);
455 size += RADEON_GPU_PAGE_ALIGN(rdev->vm_manager.max_pfn * 8); 466 size += rdev->vm_manager.max_pfn * 8;
456 size *= 2; 467 size *= 2;
457 r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager, 468 r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager,
458 size, 469 RADEON_GPU_PAGE_ALIGN(size),
459 RADEON_GEM_DOMAIN_VRAM); 470 RADEON_GEM_DOMAIN_VRAM);
460 if (r) { 471 if (r) {
461 dev_err(rdev->dev, "failed to allocate vm bo (%dKB)\n", 472 dev_err(rdev->dev, "failed to allocate vm bo (%dKB)\n",
@@ -476,7 +487,7 @@ int radeon_vm_manager_init(struct radeon_device *rdev)
476 487
477 /* restore page table */ 488 /* restore page table */
478 list_for_each_entry(vm, &rdev->vm_manager.lru_vm, list) { 489 list_for_each_entry(vm, &rdev->vm_manager.lru_vm, list) {
479 if (vm->sa_bo == NULL) 490 if (vm->page_directory == NULL)
480 continue; 491 continue;
481 492
482 list_for_each_entry(bo_va, &vm->va, vm_list) { 493 list_for_each_entry(bo_va, &vm->va, vm_list) {
@@ -500,16 +511,25 @@ static void radeon_vm_free_pt(struct radeon_device *rdev,
500 struct radeon_vm *vm) 511 struct radeon_vm *vm)
501{ 512{
502 struct radeon_bo_va *bo_va; 513 struct radeon_bo_va *bo_va;
514 int i;
503 515
504 if (!vm->sa_bo) 516 if (!vm->page_directory)
505 return; 517 return;
506 518
507 list_del_init(&vm->list); 519 list_del_init(&vm->list);
508 radeon_sa_bo_free(rdev, &vm->sa_bo, vm->fence); 520 radeon_sa_bo_free(rdev, &vm->page_directory, vm->fence);
509 521
510 list_for_each_entry(bo_va, &vm->va, vm_list) { 522 list_for_each_entry(bo_va, &vm->va, vm_list) {
511 bo_va->valid = false; 523 bo_va->valid = false;
512 } 524 }
525
526 if (vm->page_tables == NULL)
527 return;
528
529 for (i = 0; i < radeon_vm_num_pdes(rdev); i++)
530 radeon_sa_bo_free(rdev, &vm->page_tables[i], vm->fence);
531
532 kfree(vm->page_tables);
513} 533}
514 534
515/** 535/**
@@ -546,63 +566,106 @@ void radeon_vm_manager_fini(struct radeon_device *rdev)
546} 566}
547 567
548/** 568/**
569 * radeon_vm_evict - evict page table to make room for new one
570 *
571 * @rdev: radeon_device pointer
572 * @vm: VM we want to allocate something for
573 *
574 * Evict a VM from the lru, making sure that it isn't @vm. (cayman+).
575 * Returns 0 for success, -ENOMEM for failure.
576 *
577 * Global and local mutex must be locked!
578 */
579static int radeon_vm_evict(struct radeon_device *rdev, struct radeon_vm *vm)
580{
581 struct radeon_vm *vm_evict;
582
583 if (list_empty(&rdev->vm_manager.lru_vm))
584 return -ENOMEM;
585
586 vm_evict = list_first_entry(&rdev->vm_manager.lru_vm,
587 struct radeon_vm, list);
588 if (vm_evict == vm)
589 return -ENOMEM;
590
591 mutex_lock(&vm_evict->mutex);
592 radeon_vm_free_pt(rdev, vm_evict);
593 mutex_unlock(&vm_evict->mutex);
594 return 0;
595}
596
597/**
549 * radeon_vm_alloc_pt - allocates a page table for a VM 598 * radeon_vm_alloc_pt - allocates a page table for a VM
550 * 599 *
551 * @rdev: radeon_device pointer 600 * @rdev: radeon_device pointer
552 * @vm: vm to bind 601 * @vm: vm to bind
553 * 602 *
554 * Allocate a page table for the requested vm (cayman+). 603 * Allocate a page table for the requested vm (cayman+).
555 * Also starts to populate the page table.
556 * Returns 0 for success, error for failure. 604 * Returns 0 for success, error for failure.
557 * 605 *
558 * Global and local mutex must be locked! 606 * Global and local mutex must be locked!
559 */ 607 */
560int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm) 608int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm)
561{ 609{
562 struct radeon_vm *vm_evict; 610 unsigned pd_size, pts_size;
563 int r;
564 u64 *pd_addr; 611 u64 *pd_addr;
565 int tables_size; 612 int r;
566 613
567 if (vm == NULL) { 614 if (vm == NULL) {
568 return -EINVAL; 615 return -EINVAL;
569 } 616 }
570 617
571 /* allocate enough to cover the current VM size */ 618 if (vm->page_directory != NULL) {
572 tables_size = RADEON_GPU_PAGE_ALIGN(radeon_vm_directory_size(rdev));
573 tables_size += RADEON_GPU_PAGE_ALIGN(vm->last_pfn * 8);
574
575 if (vm->sa_bo != NULL) {
576 /* update lru */
577 list_del_init(&vm->list);
578 list_add_tail(&vm->list, &rdev->vm_manager.lru_vm);
579 return 0; 619 return 0;
580 } 620 }
581 621
582retry: 622retry:
583 r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager, &vm->sa_bo, 623 pd_size = RADEON_GPU_PAGE_ALIGN(radeon_vm_directory_size(rdev));
584 tables_size, RADEON_GPU_PAGE_SIZE, false); 624 r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager,
625 &vm->page_directory, pd_size,
626 RADEON_GPU_PAGE_SIZE, false);
585 if (r == -ENOMEM) { 627 if (r == -ENOMEM) {
586 if (list_empty(&rdev->vm_manager.lru_vm)) { 628 r = radeon_vm_evict(rdev, vm);
629 if (r)
587 return r; 630 return r;
588 }
589 vm_evict = list_first_entry(&rdev->vm_manager.lru_vm, struct radeon_vm, list);
590 mutex_lock(&vm_evict->mutex);
591 radeon_vm_free_pt(rdev, vm_evict);
592 mutex_unlock(&vm_evict->mutex);
593 goto retry; 631 goto retry;
594 632
595 } else if (r) { 633 } else if (r) {
596 return r; 634 return r;
597 } 635 }
598 636
599 pd_addr = radeon_sa_bo_cpu_addr(vm->sa_bo); 637 vm->pd_gpu_addr = radeon_sa_bo_gpu_addr(vm->page_directory);
600 vm->pd_gpu_addr = radeon_sa_bo_gpu_addr(vm->sa_bo); 638
601 memset(pd_addr, 0, tables_size); 639 /* Initially clear the page directory */
640 pd_addr = radeon_sa_bo_cpu_addr(vm->page_directory);
641 memset(pd_addr, 0, pd_size);
642
643 pts_size = radeon_vm_num_pdes(rdev) * sizeof(struct radeon_sa_bo *);
644 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
645
646 if (vm->page_tables == NULL) {
647 DRM_ERROR("Cannot allocate memory for page table array\n");
648 radeon_sa_bo_free(rdev, &vm->page_directory, vm->fence);
649 return -ENOMEM;
650 }
651
652 return 0;
653}
602 654
655/**
656 * radeon_vm_add_to_lru - add VMs page table to LRU list
657 *
658 * @rdev: radeon_device pointer
659 * @vm: vm to add to LRU
660 *
661 * Add the allocated page table to the LRU list (cayman+).
662 *
663 * Global mutex must be locked!
664 */
665void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm)
666{
667 list_del_init(&vm->list);
603 list_add_tail(&vm->list, &rdev->vm_manager.lru_vm); 668 list_add_tail(&vm->list, &rdev->vm_manager.lru_vm);
604 return radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo,
605 &rdev->ring_tmp_bo.bo->tbo.mem);
606} 669}
607 670
608/** 671/**
@@ -793,20 +856,6 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
793 } 856 }
794 857
795 mutex_lock(&vm->mutex); 858 mutex_lock(&vm->mutex);
796 if (last_pfn > vm->last_pfn) {
797 /* release mutex and lock in right order */
798 mutex_unlock(&vm->mutex);
799 mutex_lock(&rdev->vm_manager.lock);
800 mutex_lock(&vm->mutex);
801 /* and check again */
802 if (last_pfn > vm->last_pfn) {
803 /* grow va space 32M by 32M */
804 unsigned align = ((32 << 20) >> 12) - 1;
805 radeon_vm_free_pt(rdev, vm);
806 vm->last_pfn = (last_pfn + align) & ~align;
807 }
808 mutex_unlock(&rdev->vm_manager.lock);
809 }
810 head = &vm->va; 859 head = &vm->va;
811 last_offset = 0; 860 last_offset = 0;
812 list_for_each_entry(tmp, &vm->va, vm_list) { 861 list_for_each_entry(tmp, &vm->va, vm_list) {
@@ -865,6 +914,154 @@ uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
865} 914}
866 915
867/** 916/**
917 * radeon_vm_update_pdes - make sure that page directory is valid
918 *
919 * @rdev: radeon_device pointer
920 * @vm: requested vm
921 * @start: start of GPU address range
922 * @end: end of GPU address range
923 *
924 * Allocates new page tables if necessary
925 * and updates the page directory (cayman+).
926 * Returns 0 for success, error for failure.
927 *
928 * Global and local mutex must be locked!
929 */
930static int radeon_vm_update_pdes(struct radeon_device *rdev,
931 struct radeon_vm *vm,
932 uint64_t start, uint64_t end)
933{
934 static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;
935
936 uint64_t last_pde = ~0, last_pt = ~0;
937 unsigned count = 0;
938 uint64_t pt_idx;
939 int r;
940
941 start = (start / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE;
942 end = (end / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE;
943
944 /* walk over the address space and update the page directory */
945 for (pt_idx = start; pt_idx <= end; ++pt_idx) {
946 uint64_t pde, pt;
947
948 if (vm->page_tables[pt_idx])
949 continue;
950
951retry:
952 r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager,
953 &vm->page_tables[pt_idx],
954 RADEON_VM_PTE_COUNT * 8,
955 RADEON_GPU_PAGE_SIZE, false);
956
957 if (r == -ENOMEM) {
958 r = radeon_vm_evict(rdev, vm);
959 if (r)
960 return r;
961 goto retry;
962 } else if (r) {
963 return r;
964 }
965
966 pde = vm->pd_gpu_addr + pt_idx * 8;
967
968 pt = radeon_sa_bo_gpu_addr(vm->page_tables[pt_idx]);
969
970 if (((last_pde + 8 * count) != pde) ||
971 ((last_pt + incr * count) != pt)) {
972
973 if (count) {
974 radeon_asic_vm_set_page(rdev, last_pde,
975 last_pt, count, incr,
976 RADEON_VM_PAGE_VALID);
977 }
978
979 count = 1;
980 last_pde = pde;
981 last_pt = pt;
982 } else {
983 ++count;
984 }
985 }
986
987 if (count) {
988 radeon_asic_vm_set_page(rdev, last_pde, last_pt, count,
989 incr, RADEON_VM_PAGE_VALID);
990
991 }
992
993 return 0;
994}
995
996/**
997 * radeon_vm_update_ptes - make sure that page tables are valid
998 *
999 * @rdev: radeon_device pointer
1000 * @vm: requested vm
1001 * @start: start of GPU address range
1002 * @end: end of GPU address range
1003 * @dst: destination address to map to
1004 * @flags: mapping flags
1005 *
1006 * Update the page tables in the range @start - @end (cayman+).
1007 *
1008 * Global and local mutex must be locked!
1009 */
1010static void radeon_vm_update_ptes(struct radeon_device *rdev,
1011 struct radeon_vm *vm,
1012 uint64_t start, uint64_t end,
1013 uint64_t dst, uint32_t flags)
1014{
1015 static const uint64_t mask = RADEON_VM_PTE_COUNT - 1;
1016
1017 uint64_t last_pte = ~0, last_dst = ~0;
1018 unsigned count = 0;
1019 uint64_t addr;
1020
1021 start = start / RADEON_GPU_PAGE_SIZE;
1022 end = end / RADEON_GPU_PAGE_SIZE;
1023
1024 /* walk over the address space and update the page tables */
1025 for (addr = start; addr < end; ) {
1026 uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE;
1027 unsigned nptes;
1028 uint64_t pte;
1029
1030 if ((addr & ~mask) == (end & ~mask))
1031 nptes = end - addr;
1032 else
1033 nptes = RADEON_VM_PTE_COUNT - (addr & mask);
1034
1035 pte = radeon_sa_bo_gpu_addr(vm->page_tables[pt_idx]);
1036 pte += (addr & mask) * 8;
1037
1038 if ((last_pte + 8 * count) != pte) {
1039
1040 if (count) {
1041 radeon_asic_vm_set_page(rdev, last_pte,
1042 last_dst, count,
1043 RADEON_GPU_PAGE_SIZE,
1044 flags);
1045 }
1046
1047 count = nptes;
1048 last_pte = pte;
1049 last_dst = dst;
1050 } else {
1051 count += nptes;
1052 }
1053
1054 addr += nptes;
1055 dst += nptes * RADEON_GPU_PAGE_SIZE;
1056 }
1057
1058 if (count) {
1059 radeon_asic_vm_set_page(rdev, last_pte, last_dst, count,
1060 RADEON_GPU_PAGE_SIZE, flags);
1061 }
1062}
1063
1064/**
868 * radeon_vm_bo_update_pte - map a bo into the vm page table 1065 * radeon_vm_bo_update_pte - map a bo into the vm page table
869 * 1066 *
870 * @rdev: radeon_device pointer 1067 * @rdev: radeon_device pointer
@@ -887,12 +1084,11 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
887 struct radeon_semaphore *sem = NULL; 1084 struct radeon_semaphore *sem = NULL;
888 struct radeon_bo_va *bo_va; 1085 struct radeon_bo_va *bo_va;
889 unsigned nptes, npdes, ndw; 1086 unsigned nptes, npdes, ndw;
890 uint64_t pe, addr; 1087 uint64_t addr;
891 uint64_t pfn;
892 int r; 1088 int r;
893 1089
894 /* nothing to do if vm isn't bound */ 1090 /* nothing to do if vm isn't bound */
895 if (vm->sa_bo == NULL) 1091 if (vm->page_directory == NULL)
896 return 0; 1092 return 0;
897 1093
898 bo_va = radeon_vm_bo_find(vm, bo); 1094 bo_va = radeon_vm_bo_find(vm, bo);
@@ -939,25 +1135,29 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
939 } 1135 }
940 } 1136 }
941 1137
942 /* estimate number of dw needed */
943 /* reserve space for 32-bit padding */
944 ndw = 32;
945
946 nptes = radeon_bo_ngpu_pages(bo); 1138 nptes = radeon_bo_ngpu_pages(bo);
947 1139
948 pfn = (bo_va->soffset / RADEON_GPU_PAGE_SIZE); 1140 /* assume two extra pdes in case the mapping overlaps the borders */
1141 npdes = (nptes >> RADEON_VM_BLOCK_SIZE) + 2;
949 1142
950 /* handle cases where a bo spans several pdes */ 1143 /* estimate number of dw needed */
951 npdes = (ALIGN(pfn + nptes, RADEON_VM_PTE_COUNT) - 1144 /* semaphore, fence and padding */
952 (pfn & ~(RADEON_VM_PTE_COUNT - 1))) >> RADEON_VM_BLOCK_SIZE; 1145 ndw = 32;
1146
1147 if (RADEON_VM_BLOCK_SIZE > 11)
1148 /* reserve space for one header for every 2k dwords */
1149 ndw += (nptes >> 11) * 4;
1150 else
1151 /* reserve space for one header for
1152 every (1 << BLOCK_SIZE) entries */
1153 ndw += (nptes >> RADEON_VM_BLOCK_SIZE) * 4;
953 1154
954 /* reserve space for one header for every 2k dwords */
955 ndw += (nptes >> 11) * 3;
956 /* reserve space for pte addresses */ 1155 /* reserve space for pte addresses */
957 ndw += nptes * 2; 1156 ndw += nptes * 2;
958 1157
959 /* reserve space for one header for every 2k dwords */ 1158 /* reserve space for one header for every 2k dwords */
960 ndw += (npdes >> 11) * 3; 1159 ndw += (npdes >> 11) * 4;
1160
961 /* reserve space for pde addresses */ 1161 /* reserve space for pde addresses */
962 ndw += npdes * 2; 1162 ndw += npdes * 2;
963 1163
@@ -971,22 +1171,14 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
971 radeon_fence_note_sync(vm->fence, ridx); 1171 radeon_fence_note_sync(vm->fence, ridx);
972 } 1172 }
973 1173
974 /* update page table entries */ 1174 r = radeon_vm_update_pdes(rdev, vm, bo_va->soffset, bo_va->eoffset);
975 pe = vm->pd_gpu_addr; 1175 if (r) {
976 pe += radeon_vm_directory_size(rdev); 1176 radeon_ring_unlock_undo(rdev, ring);
977 pe += (bo_va->soffset / RADEON_GPU_PAGE_SIZE) * 8; 1177 return r;
978 1178 }
979 radeon_asic_vm_set_page(rdev, pe, addr, nptes,
980 RADEON_GPU_PAGE_SIZE, bo_va->flags);
981
982 /* update page directory entries */
983 addr = pe;
984
985 pe = vm->pd_gpu_addr;
986 pe += ((bo_va->soffset / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE) * 8;
987 1179
988 radeon_asic_vm_set_page(rdev, pe, addr, npdes, 1180 radeon_vm_update_ptes(rdev, vm, bo_va->soffset, bo_va->eoffset,
989 RADEON_VM_PTE_COUNT * 8, RADEON_VM_PAGE_VALID); 1181 addr, bo_va->flags);
990 1182
991 radeon_fence_unref(&vm->fence); 1183 radeon_fence_unref(&vm->fence);
992 r = radeon_fence_emit(rdev, &vm->fence, ridx); 1184 r = radeon_fence_emit(rdev, &vm->fence, ridx);
@@ -997,6 +1189,7 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
997 radeon_ring_unlock_commit(rdev, ring); 1189 radeon_ring_unlock_commit(rdev, ring);
998 radeon_semaphore_free(rdev, &sem, vm->fence); 1190 radeon_semaphore_free(rdev, &sem, vm->fence);
999 radeon_fence_unref(&vm->last_flush); 1191 radeon_fence_unref(&vm->last_flush);
1192
1000 return 0; 1193 return 0;
1001} 1194}
1002 1195
@@ -1056,31 +1249,15 @@ void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1056 * @rdev: radeon_device pointer 1249 * @rdev: radeon_device pointer
1057 * @vm: requested vm 1250 * @vm: requested vm
1058 * 1251 *
1059 * Init @vm (cayman+). 1252 * Init @vm fields (cayman+).
1060 * Map the IB pool and any other shared objects into the VM
1061 * by default as it's used by all VMs.
1062 * Returns 0 for success, error for failure.
1063 */ 1253 */
1064int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm) 1254void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
1065{ 1255{
1066 struct radeon_bo_va *bo_va;
1067 int r;
1068
1069 vm->id = 0; 1256 vm->id = 0;
1070 vm->fence = NULL; 1257 vm->fence = NULL;
1071 vm->last_pfn = 0;
1072 mutex_init(&vm->mutex); 1258 mutex_init(&vm->mutex);
1073 INIT_LIST_HEAD(&vm->list); 1259 INIT_LIST_HEAD(&vm->list);
1074 INIT_LIST_HEAD(&vm->va); 1260 INIT_LIST_HEAD(&vm->va);
1075
1076 /* map the ib pool buffer at 0 in virtual address space, set
1077 * read only
1078 */
1079 bo_va = radeon_vm_bo_add(rdev, vm, rdev->ring_tmp_bo.bo);
1080 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
1081 RADEON_VM_PAGE_READABLE |
1082 RADEON_VM_PAGE_SNOOPED);
1083 return r;
1084} 1261}
1085 1262
1086/** 1263/**
@@ -1102,17 +1279,6 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
1102 radeon_vm_free_pt(rdev, vm); 1279 radeon_vm_free_pt(rdev, vm);
1103 mutex_unlock(&rdev->vm_manager.lock); 1280 mutex_unlock(&rdev->vm_manager.lock);
1104 1281
1105 /* remove all bo at this point non are busy any more because unbind
1106 * waited for the last vm fence to signal
1107 */
1108 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
1109 if (!r) {
1110 bo_va = radeon_vm_bo_find(vm, rdev->ring_tmp_bo.bo);
1111 list_del_init(&bo_va->bo_list);
1112 list_del_init(&bo_va->vm_list);
1113 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
1114 kfree(bo_va);
1115 }
1116 if (!list_empty(&vm->va)) { 1282 if (!list_empty(&vm->va)) {
1117 dev_err(rdev->dev, "still active bo inside vm\n"); 1283 dev_err(rdev->dev, "still active bo inside vm\n");
1118 } 1284 }
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index f38fbcc46935..fe5c1f6b7957 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -53,6 +53,7 @@ int radeon_gem_object_create(struct radeon_device *rdev, int size,
53 struct drm_gem_object **obj) 53 struct drm_gem_object **obj)
54{ 54{
55 struct radeon_bo *robj; 55 struct radeon_bo *robj;
56 unsigned long max_size;
56 int r; 57 int r;
57 58
58 *obj = NULL; 59 *obj = NULL;
@@ -60,11 +61,26 @@ int radeon_gem_object_create(struct radeon_device *rdev, int size,
60 if (alignment < PAGE_SIZE) { 61 if (alignment < PAGE_SIZE) {
61 alignment = PAGE_SIZE; 62 alignment = PAGE_SIZE;
62 } 63 }
64
65 /* maximun bo size is the minimun btw visible vram and gtt size */
66 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
67 if (size > max_size) {
68 printk(KERN_WARNING "%s:%d alloc size %dMb bigger than %ldMb limit\n",
69 __func__, __LINE__, size >> 20, max_size >> 20);
70 return -ENOMEM;
71 }
72
73retry:
63 r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain, NULL, &robj); 74 r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain, NULL, &robj);
64 if (r) { 75 if (r) {
65 if (r != -ERESTARTSYS) 76 if (r != -ERESTARTSYS) {
77 if (initial_domain == RADEON_GEM_DOMAIN_VRAM) {
78 initial_domain |= RADEON_GEM_DOMAIN_GTT;
79 goto retry;
80 }
66 DRM_ERROR("Failed to allocate GEM object (%d, %d, %u, %d)\n", 81 DRM_ERROR("Failed to allocate GEM object (%d, %d, %u, %d)\n",
67 size, initial_domain, alignment, r); 82 size, initial_domain, alignment, r);
83 }
68 return r; 84 return r;
69 } 85 }
70 *obj = &robj->gem_base; 86 *obj = &robj->gem_base;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 83b8d8aa71c0..dc781c49b96b 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -419,6 +419,7 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
419 /* new gpu have virtual address space support */ 419 /* new gpu have virtual address space support */
420 if (rdev->family >= CHIP_CAYMAN) { 420 if (rdev->family >= CHIP_CAYMAN) {
421 struct radeon_fpriv *fpriv; 421 struct radeon_fpriv *fpriv;
422 struct radeon_bo_va *bo_va;
422 int r; 423 int r;
423 424
424 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 425 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
@@ -426,7 +427,15 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
426 return -ENOMEM; 427 return -ENOMEM;
427 } 428 }
428 429
429 r = radeon_vm_init(rdev, &fpriv->vm); 430 radeon_vm_init(rdev, &fpriv->vm);
431
432 /* map the ib pool buffer read only into
433 * virtual address space */
434 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
435 rdev->ring_tmp_bo.bo);
436 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
437 RADEON_VM_PAGE_READABLE |
438 RADEON_VM_PAGE_SNOOPED);
430 if (r) { 439 if (r) {
431 radeon_vm_fini(rdev, &fpriv->vm); 440 radeon_vm_fini(rdev, &fpriv->vm);
432 kfree(fpriv); 441 kfree(fpriv);
@@ -454,6 +463,17 @@ void radeon_driver_postclose_kms(struct drm_device *dev,
454 /* new gpu have virtual address space support */ 463 /* new gpu have virtual address space support */
455 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 464 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
456 struct radeon_fpriv *fpriv = file_priv->driver_priv; 465 struct radeon_fpriv *fpriv = file_priv->driver_priv;
466 struct radeon_bo_va *bo_va;
467 int r;
468
469 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
470 if (!r) {
471 bo_va = radeon_vm_bo_find(&fpriv->vm,
472 rdev->ring_tmp_bo.bo);
473 if (bo_va)
474 radeon_vm_bo_rmv(rdev, bo_va);
475 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
476 }
457 477
458 radeon_vm_fini(rdev, &fpriv->vm); 478 radeon_vm_fini(rdev, &fpriv->vm);
459 kfree(fpriv); 479 kfree(fpriv);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 5677a424b585..6857cb4efb76 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -295,6 +295,7 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
295 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 295 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
296 struct drm_device *dev = crtc->dev; 296 struct drm_device *dev = crtc->dev;
297 struct radeon_device *rdev = dev->dev_private; 297 struct radeon_device *rdev = dev->dev_private;
298 uint32_t crtc_ext_cntl = 0;
298 uint32_t mask; 299 uint32_t mask;
299 300
300 if (radeon_crtc->crtc_id) 301 if (radeon_crtc->crtc_id)
@@ -307,6 +308,16 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
307 RADEON_CRTC_VSYNC_DIS | 308 RADEON_CRTC_VSYNC_DIS |
308 RADEON_CRTC_HSYNC_DIS); 309 RADEON_CRTC_HSYNC_DIS);
309 310
311 /*
312 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
313 * Therefore it is set in the DAC DMPS function.
314 * This is different for GPU's with a single CRTC but a primary and a
315 * TV DAC: here it controls the single CRTC no matter where it is
316 * routed. Therefore we set it here.
317 */
318 if (rdev->flags & RADEON_SINGLE_CRTC)
319 crtc_ext_cntl = RADEON_CRTC_CRT_ON;
320
310 switch (mode) { 321 switch (mode) {
311 case DRM_MODE_DPMS_ON: 322 case DRM_MODE_DPMS_ON:
312 radeon_crtc->enabled = true; 323 radeon_crtc->enabled = true;
@@ -317,7 +328,7 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
317 else { 328 else {
318 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 329 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
319 RADEON_CRTC_DISP_REQ_EN_B)); 330 RADEON_CRTC_DISP_REQ_EN_B));
320 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); 331 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
321 } 332 }
322 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 333 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
323 radeon_crtc_load_lut(crtc); 334 radeon_crtc_load_lut(crtc);
@@ -331,7 +342,7 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
331 else { 342 else {
332 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 343 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
333 RADEON_CRTC_DISP_REQ_EN_B)); 344 RADEON_CRTC_DISP_REQ_EN_B));
334 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); 345 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
335 } 346 }
336 radeon_crtc->enabled = false; 347 radeon_crtc->enabled = false;
337 /* adjust pm to dpms changes AFTER disabling crtcs */ 348 /* adjust pm to dpms changes AFTER disabling crtcs */
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 92487e614778..f5ba2241dacc 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -269,27 +269,6 @@ static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
269 .disable = radeon_legacy_encoder_disable, 269 .disable = radeon_legacy_encoder_disable,
270}; 270};
271 271
272#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
273
274static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
275{
276 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
277 uint8_t level;
278
279 /* Convert brightness to hardware level */
280 if (bd->props.brightness < 0)
281 level = 0;
282 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
283 level = RADEON_MAX_BL_LEVEL;
284 else
285 level = bd->props.brightness;
286
287 if (pdata->negative)
288 level = RADEON_MAX_BL_LEVEL - level;
289
290 return level;
291}
292
293u8 272u8
294radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder) 273radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
295{ 274{
@@ -331,6 +310,27 @@ radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 leve
331 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); 310 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
332} 311}
333 312
313#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
314
315static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
316{
317 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
318 uint8_t level;
319
320 /* Convert brightness to hardware level */
321 if (bd->props.brightness < 0)
322 level = 0;
323 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
324 level = RADEON_MAX_BL_LEVEL;
325 else
326 level = bd->props.brightness;
327
328 if (pdata->negative)
329 level = RADEON_MAX_BL_LEVEL - level;
330
331 return level;
332}
333
334static int radeon_legacy_backlight_update_status(struct backlight_device *bd) 334static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
335{ 335{
336 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 336 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
@@ -370,6 +370,7 @@ void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
370 struct backlight_properties props; 370 struct backlight_properties props;
371 struct radeon_backlight_privdata *pdata; 371 struct radeon_backlight_privdata *pdata;
372 uint8_t backlight_level; 372 uint8_t backlight_level;
373 char bl_name[16];
373 374
374 if (!radeon_encoder->enc_priv) 375 if (!radeon_encoder->enc_priv)
375 return; 376 return;
@@ -389,7 +390,9 @@ void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
389 memset(&props, 0, sizeof(props)); 390 memset(&props, 0, sizeof(props));
390 props.max_brightness = RADEON_MAX_BL_LEVEL; 391 props.max_brightness = RADEON_MAX_BL_LEVEL;
391 props.type = BACKLIGHT_RAW; 392 props.type = BACKLIGHT_RAW;
392 bd = backlight_device_register("radeon_bl", &drm_connector->kdev, 393 snprintf(bl_name, sizeof(bl_name),
394 "radeon_bl%d", dev->primary->index);
395 bd = backlight_device_register(bl_name, &drm_connector->kdev,
393 pdata, &radeon_backlight_ops, &props); 396 pdata, &radeon_backlight_ops, &props);
394 if (IS_ERR(bd)) { 397 if (IS_ERR(bd)) {
395 DRM_ERROR("Backlight registration failed\n"); 398 DRM_ERROR("Backlight registration failed\n");
@@ -534,7 +537,9 @@ static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode
534 break; 537 break;
535 } 538 }
536 539
537 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 540 /* handled in radeon_crtc_dpms() */
541 if (!(rdev->flags & RADEON_SINGLE_CRTC))
542 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
538 WREG32(RADEON_DAC_CNTL, dac_cntl); 543 WREG32(RADEON_DAC_CNTL, dac_cntl);
539 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 544 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
540 545
@@ -659,6 +664,8 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc
659 664
660 if (ASIC_IS_R300(rdev)) 665 if (ASIC_IS_R300(rdev))
661 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 666 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
667 else if (ASIC_IS_RV100(rdev))
668 tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
662 else 669 else
663 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 670 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
664 671
@@ -668,6 +675,7 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc
668 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; 675 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
669 WREG32(RADEON_DAC_CNTL, tmp); 676 WREG32(RADEON_DAC_CNTL, tmp);
670 677
678 tmp = dac_macro_cntl;
671 tmp &= ~(RADEON_DAC_PDWN_R | 679 tmp &= ~(RADEON_DAC_PDWN_R |
672 RADEON_DAC_PDWN_G | 680 RADEON_DAC_PDWN_G |
673 RADEON_DAC_PDWN_B); 681 RADEON_DAC_PDWN_B);
@@ -991,11 +999,7 @@ static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
991static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder) 999static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
992{ 1000{
993 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1001 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
994 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 1002 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
995 if (tmds) {
996 if (tmds->i2c_bus)
997 radeon_i2c_destroy(tmds->i2c_bus);
998 }
999 kfree(radeon_encoder->enc_priv); 1003 kfree(radeon_encoder->enc_priv);
1000 drm_encoder_cleanup(encoder); 1004 drm_encoder_cleanup(encoder);
1001 kfree(radeon_encoder); 1005 kfree(radeon_encoder);
@@ -1093,7 +1097,8 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1093 } else { 1097 } else {
1094 if (is_tv) 1098 if (is_tv)
1095 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1099 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1096 else 1100 /* handled in radeon_crtc_dpms() */
1101 else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1097 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1102 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1098 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1103 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1099 } 1104 }
@@ -1417,13 +1422,104 @@ static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1417 return found; 1422 return found;
1418} 1423}
1419 1424
1425static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1426 struct drm_connector *connector)
1427{
1428 struct drm_device *dev = encoder->dev;
1429 struct radeon_device *rdev = dev->dev_private;
1430 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1431 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1432 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1433 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1434 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1435 bool found = false;
1436 int i;
1437
1438 /* save the regs we need */
1439 gpio_monid = RREG32(RADEON_GPIO_MONID);
1440 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1441 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1442 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1443 disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1444 disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1445 disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1446 disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1447 disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1448 disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1449 crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1450 crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1451 crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1452 crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1453
1454 tmp = RREG32(RADEON_GPIO_MONID);
1455 tmp &= ~RADEON_GPIO_A_0;
1456 WREG32(RADEON_GPIO_MONID, tmp);
1457
1458 WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1459 RADEON_FP2_PANEL_FORMAT |
1460 R200_FP2_SOURCE_SEL_TRANS_UNIT |
1461 RADEON_FP2_DVO_EN |
1462 R200_FP2_DVO_RATE_SEL_SDR));
1463
1464 WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1465 RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1466
1467 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1468 RADEON_CRTC2_DISP_REQ_EN_B));
1469
1470 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1471 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1472 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1473 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1474 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1475 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1476
1477 WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1478 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1479 WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1480 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1481
1482 for (i = 0; i < 200; i++) {
1483 tmp = RREG32(RADEON_GPIO_MONID);
1484 if (tmp & RADEON_GPIO_Y_0)
1485 found = true;
1486
1487 if (found)
1488 break;
1489
1490 if (!drm_can_sleep())
1491 mdelay(1);
1492 else
1493 msleep(1);
1494 }
1495
1496 /* restore the regs we used */
1497 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1498 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1499 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1500 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1501 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1502 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1503 WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1504 WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1505 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1506 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1507 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1508 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1509 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1510 WREG32(RADEON_GPIO_MONID, gpio_monid);
1511
1512 return found;
1513}
1514
1420static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, 1515static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1421 struct drm_connector *connector) 1516 struct drm_connector *connector)
1422{ 1517{
1423 struct drm_device *dev = encoder->dev; 1518 struct drm_device *dev = encoder->dev;
1424 struct radeon_device *rdev = dev->dev_private; 1519 struct radeon_device *rdev = dev->dev_private;
1425 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1520 uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1426 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; 1521 uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1522 uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1427 enum drm_connector_status found = connector_status_disconnected; 1523 enum drm_connector_status found = connector_status_disconnected;
1428 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1524 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1429 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1525 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
@@ -1460,12 +1556,27 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
1460 return connector_status_disconnected; 1556 return connector_status_disconnected;
1461 } 1557 }
1462 1558
1559 /* R200 uses an external DAC for secondary DAC */
1560 if (rdev->family == CHIP_R200) {
1561 if (radeon_legacy_ext_dac_detect(encoder, connector))
1562 found = connector_status_connected;
1563 return found;
1564 }
1565
1463 /* save the regs we need */ 1566 /* save the regs we need */
1464 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 1567 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1465 gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0; 1568
1466 disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0; 1569 if (rdev->flags & RADEON_SINGLE_CRTC) {
1467 disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG); 1570 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1468 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1571 } else {
1572 if (ASIC_IS_R300(rdev)) {
1573 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1574 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1575 } else {
1576 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1577 }
1578 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1579 }
1469 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1580 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1470 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1581 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1471 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1582 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
@@ -1474,22 +1585,24 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
1474 | RADEON_PIX2CLK_DAC_ALWAYS_ONb); 1585 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1475 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 1586 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1476 1587
1477 if (ASIC_IS_R300(rdev)) 1588 if (rdev->flags & RADEON_SINGLE_CRTC) {
1478 WREG32_P(RADEON_GPIOPAD_A, 1, ~1); 1589 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1479 1590 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1480 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1481 tmp |= RADEON_CRTC2_CRT2_ON |
1482 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1483
1484 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1485
1486 if (ASIC_IS_R300(rdev)) {
1487 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1488 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1489 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1490 } else { 1591 } else {
1491 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; 1592 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1492 WREG32(RADEON_DISP_HW_DEBUG, tmp); 1593 tmp |= RADEON_CRTC2_CRT2_ON |
1594 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1595 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1596
1597 if (ASIC_IS_R300(rdev)) {
1598 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1599 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1600 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1601 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1602 } else {
1603 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1604 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1605 }
1493 } 1606 }
1494 1607
1495 tmp = RADEON_TV_DAC_NBLANK | 1608 tmp = RADEON_TV_DAC_NBLANK |
@@ -1531,14 +1644,19 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
1531 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1644 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1532 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1645 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1533 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1646 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1534 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1535 1647
1536 if (ASIC_IS_R300(rdev)) { 1648 if (rdev->flags & RADEON_SINGLE_CRTC) {
1537 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1649 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1538 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1539 } else { 1650 } else {
1540 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1651 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1652 if (ASIC_IS_R300(rdev)) {
1653 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1654 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1655 } else {
1656 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1657 }
1541 } 1658 }
1659
1542 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1660 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1543 1661
1544 return found; 1662 return found;
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 8b27dd6e3144..b91118ccef86 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -105,7 +105,6 @@ int radeon_bo_create(struct radeon_device *rdev,
105 struct radeon_bo *bo; 105 struct radeon_bo *bo;
106 enum ttm_bo_type type; 106 enum ttm_bo_type type;
107 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 107 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
108 unsigned long max_size = 0;
109 size_t acc_size; 108 size_t acc_size;
110 int r; 109 int r;
111 110
@@ -121,18 +120,9 @@ int radeon_bo_create(struct radeon_device *rdev,
121 } 120 }
122 *bo_ptr = NULL; 121 *bo_ptr = NULL;
123 122
124 /* maximun bo size is the minimun btw visible vram and gtt size */
125 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
126 if ((page_align << PAGE_SHIFT) >= max_size) {
127 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
128 __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20);
129 return -ENOMEM;
130 }
131
132 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 123 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
133 sizeof(struct radeon_bo)); 124 sizeof(struct radeon_bo));
134 125
135retry:
136 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 126 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
137 if (bo == NULL) 127 if (bo == NULL)
138 return -ENOMEM; 128 return -ENOMEM;
@@ -154,15 +144,6 @@ retry:
154 acc_size, sg, &radeon_ttm_bo_destroy); 144 acc_size, sg, &radeon_ttm_bo_destroy);
155 up_read(&rdev->pm.mclk_lock); 145 up_read(&rdev->pm.mclk_lock);
156 if (unlikely(r != 0)) { 146 if (unlikely(r != 0)) {
157 if (r != -ERESTARTSYS) {
158 if (domain == RADEON_GEM_DOMAIN_VRAM) {
159 domain |= RADEON_GEM_DOMAIN_GTT;
160 goto retry;
161 }
162 dev_err(rdev->dev,
163 "object_init failed for (%lu, 0x%08X)\n",
164 size, domain);
165 }
166 return r; 147 return r;
167 } 148 }
168 *bo_ptr = bo; 149 *bo_ptr = bo;
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index bba66902c83b..47634f27f2e5 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -305,7 +305,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
305{ 305{
306#if DRM_DEBUG_CODE 306#if DRM_DEBUG_CODE
307 if (ring->count_dw <= 0) { 307 if (ring->count_dw <= 0) {
308 DRM_ERROR("radeon: writting more dword to ring than expected !\n"); 308 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
309 } 309 }
310#endif 310#endif
311 ring->ring[ring->wptr++] = v; 311 ring->ring[ring->wptr++] = v;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index f79633a036c3..b0db712060fb 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2407,12 +2407,13 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
2407 WREG32(0x15DC, 0); 2407 WREG32(0x15DC, 0);
2408 2408
2409 /* empty context1-15 */ 2409 /* empty context1-15 */
2410 /* FIXME start with 4G, once using 2 level pt switch to full
2411 * vm size space
2412 */
2413 /* set vm size, must be a multiple of 4 */ 2410 /* set vm size, must be a multiple of 4 */
2414 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 2411 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
2415 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); 2412 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
2413 /* Assign the pt base to something valid for now; the pts used for
2414 * the VMs are determined by the application and setup and assigned
2415 * on the fly in the vm part of radeon_gart.c
2416 */
2416 for (i = 1; i < 16; i++) { 2417 for (i = 1; i < 16; i++) {
2417 if (i < 8) 2418 if (i < 8)
2418 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 2419 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
@@ -2807,26 +2808,31 @@ void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
2807{ 2808{
2808 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index]; 2809 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
2809 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); 2810 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
2810 int i;
2811 uint64_t value;
2812 2811
2813 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 2 + count * 2)); 2812 while (count) {
2814 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2813 unsigned ndw = 2 + count * 2;
2815 WRITE_DATA_DST_SEL(1))); 2814 if (ndw > 0x3FFE)
2816 radeon_ring_write(ring, pe); 2815 ndw = 0x3FFE;
2817 radeon_ring_write(ring, upper_32_bits(pe)); 2816
2818 for (i = 0; i < count; ++i) { 2817 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw));
2819 if (flags & RADEON_VM_PAGE_SYSTEM) { 2818 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2820 value = radeon_vm_map_gart(rdev, addr); 2819 WRITE_DATA_DST_SEL(1)));
2821 value &= 0xFFFFFFFFFFFFF000ULL; 2820 radeon_ring_write(ring, pe);
2822 } else if (flags & RADEON_VM_PAGE_VALID) 2821 radeon_ring_write(ring, upper_32_bits(pe));
2823 value = addr; 2822 for (; ndw > 2; ndw -= 2, --count, pe += 8) {
2824 else 2823 uint64_t value;
2825 value = 0; 2824 if (flags & RADEON_VM_PAGE_SYSTEM) {
2826 addr += incr; 2825 value = radeon_vm_map_gart(rdev, addr);
2827 value |= r600_flags; 2826 value &= 0xFFFFFFFFFFFFF000ULL;
2828 radeon_ring_write(ring, value); 2827 } else if (flags & RADEON_VM_PAGE_VALID)
2829 radeon_ring_write(ring, upper_32_bits(value)); 2828 value = addr;
2829 else
2830 value = 0;
2831 addr += incr;
2832 value |= r600_flags;
2833 radeon_ring_write(ring, value);
2834 radeon_ring_write(ring, upper_32_bits(value));
2835 }
2830 } 2836 }
2831} 2837}
2832 2838
@@ -2867,6 +2873,10 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2867 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 2873 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
2868 radeon_ring_write(ring, 0); 2874 radeon_ring_write(ring, 0);
2869 radeon_ring_write(ring, 1 << vm->id); 2875 radeon_ring_write(ring, 1 << vm->id);
2876
2877 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2878 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2879 radeon_ring_write(ring, 0x0);
2870} 2880}
2871 2881
2872/* 2882/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 13:02:53 -0500