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authorAlex Deucher <alexander.deucher@amd.com>2012-03-20 17:18:15 -0400
committerDave Airlie <airlied@redhat.com>2012-03-21 02:55:53 -0400
commit498dd8b35ae798c3a6c6c9da029db1806dc2cf93 (patch)
treea8ab6d73ee56a12320cf4d2ce5c737e1def029b3 /drivers/gpu/drm/radeon
parentdfcf5f36529d69eb35f4fdedfa6f244c5249698c (diff)
drm/radeon/kms: add VM CS checker for SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/si.c309
-rw-r--r--drivers/gpu/drm/radeon/sid.h31
2 files changed, 340 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index ad91c5fbb61b..30b379e3f3f5 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1882,6 +1882,315 @@ void si_pcie_gart_fini(struct radeon_device *rdev)
1882 radeon_gart_fini(rdev); 1882 radeon_gart_fini(rdev);
1883} 1883}
1884 1884
1885/* vm parser */
1886static bool si_vm_reg_valid(u32 reg)
1887{
1888 /* context regs are fine */
1889 if (reg >= 0x28000)
1890 return true;
1891
1892 /* check config regs */
1893 switch (reg) {
1894 case GRBM_GFX_INDEX:
1895 case VGT_VTX_VECT_EJECT_REG:
1896 case VGT_CACHE_INVALIDATION:
1897 case VGT_ESGS_RING_SIZE:
1898 case VGT_GSVS_RING_SIZE:
1899 case VGT_GS_VERTEX_REUSE:
1900 case VGT_PRIMITIVE_TYPE:
1901 case VGT_INDEX_TYPE:
1902 case VGT_NUM_INDICES:
1903 case VGT_NUM_INSTANCES:
1904 case VGT_TF_RING_SIZE:
1905 case VGT_HS_OFFCHIP_PARAM:
1906 case VGT_TF_MEMORY_BASE:
1907 case PA_CL_ENHANCE:
1908 case PA_SU_LINE_STIPPLE_VALUE:
1909 case PA_SC_LINE_STIPPLE_STATE:
1910 case PA_SC_ENHANCE:
1911 case SQC_CACHES:
1912 case SPI_STATIC_THREAD_MGMT_1:
1913 case SPI_STATIC_THREAD_MGMT_2:
1914 case SPI_STATIC_THREAD_MGMT_3:
1915 case SPI_PS_MAX_WAVE_ID:
1916 case SPI_CONFIG_CNTL:
1917 case SPI_CONFIG_CNTL_1:
1918 case TA_CNTL_AUX:
1919 return true;
1920 default:
1921 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
1922 return false;
1923 }
1924}
1925
1926static int si_vm_packet3_ce_check(struct radeon_device *rdev,
1927 u32 *ib, struct radeon_cs_packet *pkt)
1928{
1929 switch (pkt->opcode) {
1930 case PACKET3_NOP:
1931 case PACKET3_SET_BASE:
1932 case PACKET3_SET_CE_DE_COUNTERS:
1933 case PACKET3_LOAD_CONST_RAM:
1934 case PACKET3_WRITE_CONST_RAM:
1935 case PACKET3_WRITE_CONST_RAM_OFFSET:
1936 case PACKET3_DUMP_CONST_RAM:
1937 case PACKET3_INCREMENT_CE_COUNTER:
1938 case PACKET3_WAIT_ON_DE_COUNTER:
1939 case PACKET3_CE_WRITE:
1940 break;
1941 default:
1942 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
1943 return -EINVAL;
1944 }
1945 return 0;
1946}
1947
1948static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
1949 u32 *ib, struct radeon_cs_packet *pkt)
1950{
1951 u32 idx = pkt->idx + 1;
1952 u32 idx_value = ib[idx];
1953 u32 start_reg, end_reg, reg, i;
1954
1955 switch (pkt->opcode) {
1956 case PACKET3_NOP:
1957 case PACKET3_SET_BASE:
1958 case PACKET3_CLEAR_STATE:
1959 case PACKET3_INDEX_BUFFER_SIZE:
1960 case PACKET3_DISPATCH_DIRECT:
1961 case PACKET3_DISPATCH_INDIRECT:
1962 case PACKET3_ALLOC_GDS:
1963 case PACKET3_WRITE_GDS_RAM:
1964 case PACKET3_ATOMIC_GDS:
1965 case PACKET3_ATOMIC:
1966 case PACKET3_OCCLUSION_QUERY:
1967 case PACKET3_SET_PREDICATION:
1968 case PACKET3_COND_EXEC:
1969 case PACKET3_PRED_EXEC:
1970 case PACKET3_DRAW_INDIRECT:
1971 case PACKET3_DRAW_INDEX_INDIRECT:
1972 case PACKET3_INDEX_BASE:
1973 case PACKET3_DRAW_INDEX_2:
1974 case PACKET3_CONTEXT_CONTROL:
1975 case PACKET3_INDEX_TYPE:
1976 case PACKET3_DRAW_INDIRECT_MULTI:
1977 case PACKET3_DRAW_INDEX_AUTO:
1978 case PACKET3_DRAW_INDEX_IMMD:
1979 case PACKET3_NUM_INSTANCES:
1980 case PACKET3_DRAW_INDEX_MULTI_AUTO:
1981 case PACKET3_STRMOUT_BUFFER_UPDATE:
1982 case PACKET3_DRAW_INDEX_OFFSET_2:
1983 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
1984 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
1985 case PACKET3_MPEG_INDEX:
1986 case PACKET3_WAIT_REG_MEM:
1987 case PACKET3_MEM_WRITE:
1988 case PACKET3_PFP_SYNC_ME:
1989 case PACKET3_SURFACE_SYNC:
1990 case PACKET3_EVENT_WRITE:
1991 case PACKET3_EVENT_WRITE_EOP:
1992 case PACKET3_EVENT_WRITE_EOS:
1993 case PACKET3_SET_CONTEXT_REG:
1994 case PACKET3_SET_CONTEXT_REG_INDIRECT:
1995 case PACKET3_SET_SH_REG:
1996 case PACKET3_SET_SH_REG_OFFSET:
1997 case PACKET3_INCREMENT_DE_COUNTER:
1998 case PACKET3_WAIT_ON_CE_COUNTER:
1999 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2000 case PACKET3_ME_WRITE:
2001 break;
2002 case PACKET3_COPY_DATA:
2003 if ((idx_value & 0xf00) == 0) {
2004 reg = ib[idx + 3] * 4;
2005 if (!si_vm_reg_valid(reg))
2006 return -EINVAL;
2007 }
2008 break;
2009 case PACKET3_WRITE_DATA:
2010 if ((idx_value & 0xf00) == 0) {
2011 start_reg = ib[idx + 1] * 4;
2012 if (idx_value & 0x10000) {
2013 if (!si_vm_reg_valid(start_reg))
2014 return -EINVAL;
2015 } else {
2016 for (i = 0; i < (pkt->count - 2); i++) {
2017 reg = start_reg + (4 * i);
2018 if (!si_vm_reg_valid(reg))
2019 return -EINVAL;
2020 }
2021 }
2022 }
2023 break;
2024 case PACKET3_COND_WRITE:
2025 if (idx_value & 0x100) {
2026 reg = ib[idx + 5] * 4;
2027 if (!si_vm_reg_valid(reg))
2028 return -EINVAL;
2029 }
2030 break;
2031 case PACKET3_COPY_DW:
2032 if (idx_value & 0x2) {
2033 reg = ib[idx + 3] * 4;
2034 if (!si_vm_reg_valid(reg))
2035 return -EINVAL;
2036 }
2037 break;
2038 case PACKET3_SET_CONFIG_REG:
2039 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2040 end_reg = 4 * pkt->count + start_reg - 4;
2041 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2042 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2043 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2044 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2045 return -EINVAL;
2046 }
2047 for (i = 0; i < pkt->count; i++) {
2048 reg = start_reg + (4 * i);
2049 if (!si_vm_reg_valid(reg))
2050 return -EINVAL;
2051 }
2052 break;
2053 default:
2054 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2055 return -EINVAL;
2056 }
2057 return 0;
2058}
2059
2060static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2061 u32 *ib, struct radeon_cs_packet *pkt)
2062{
2063 u32 idx = pkt->idx + 1;
2064 u32 idx_value = ib[idx];
2065 u32 start_reg, reg, i;
2066
2067 switch (pkt->opcode) {
2068 case PACKET3_NOP:
2069 case PACKET3_SET_BASE:
2070 case PACKET3_CLEAR_STATE:
2071 case PACKET3_DISPATCH_DIRECT:
2072 case PACKET3_DISPATCH_INDIRECT:
2073 case PACKET3_ALLOC_GDS:
2074 case PACKET3_WRITE_GDS_RAM:
2075 case PACKET3_ATOMIC_GDS:
2076 case PACKET3_ATOMIC:
2077 case PACKET3_OCCLUSION_QUERY:
2078 case PACKET3_SET_PREDICATION:
2079 case PACKET3_COND_EXEC:
2080 case PACKET3_PRED_EXEC:
2081 case PACKET3_CONTEXT_CONTROL:
2082 case PACKET3_STRMOUT_BUFFER_UPDATE:
2083 case PACKET3_WAIT_REG_MEM:
2084 case PACKET3_MEM_WRITE:
2085 case PACKET3_PFP_SYNC_ME:
2086 case PACKET3_SURFACE_SYNC:
2087 case PACKET3_EVENT_WRITE:
2088 case PACKET3_EVENT_WRITE_EOP:
2089 case PACKET3_EVENT_WRITE_EOS:
2090 case PACKET3_SET_CONTEXT_REG:
2091 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2092 case PACKET3_SET_SH_REG:
2093 case PACKET3_SET_SH_REG_OFFSET:
2094 case PACKET3_INCREMENT_DE_COUNTER:
2095 case PACKET3_WAIT_ON_CE_COUNTER:
2096 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2097 case PACKET3_ME_WRITE:
2098 break;
2099 case PACKET3_COPY_DATA:
2100 if ((idx_value & 0xf00) == 0) {
2101 reg = ib[idx + 3] * 4;
2102 if (!si_vm_reg_valid(reg))
2103 return -EINVAL;
2104 }
2105 break;
2106 case PACKET3_WRITE_DATA:
2107 if ((idx_value & 0xf00) == 0) {
2108 start_reg = ib[idx + 1] * 4;
2109 if (idx_value & 0x10000) {
2110 if (!si_vm_reg_valid(start_reg))
2111 return -EINVAL;
2112 } else {
2113 for (i = 0; i < (pkt->count - 2); i++) {
2114 reg = start_reg + (4 * i);
2115 if (!si_vm_reg_valid(reg))
2116 return -EINVAL;
2117 }
2118 }
2119 }
2120 break;
2121 case PACKET3_COND_WRITE:
2122 if (idx_value & 0x100) {
2123 reg = ib[idx + 5] * 4;
2124 if (!si_vm_reg_valid(reg))
2125 return -EINVAL;
2126 }
2127 break;
2128 case PACKET3_COPY_DW:
2129 if (idx_value & 0x2) {
2130 reg = ib[idx + 3] * 4;
2131 if (!si_vm_reg_valid(reg))
2132 return -EINVAL;
2133 }
2134 break;
2135 default:
2136 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2137 return -EINVAL;
2138 }
2139 return 0;
2140}
2141
2142int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2143{
2144 int ret = 0;
2145 u32 idx = 0;
2146 struct radeon_cs_packet pkt;
2147
2148 do {
2149 pkt.idx = idx;
2150 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2151 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2152 pkt.one_reg_wr = 0;
2153 switch (pkt.type) {
2154 case PACKET_TYPE0:
2155 dev_err(rdev->dev, "Packet0 not allowed!\n");
2156 ret = -EINVAL;
2157 break;
2158 case PACKET_TYPE2:
2159 idx += 1;
2160 break;
2161 case PACKET_TYPE3:
2162 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2163 if (ib->is_const_ib)
2164 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2165 else {
2166 switch (ib->fence->ring) {
2167 case RADEON_RING_TYPE_GFX_INDEX:
2168 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
2169 break;
2170 case CAYMAN_RING_TYPE_CP1_INDEX:
2171 case CAYMAN_RING_TYPE_CP2_INDEX:
2172 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
2173 break;
2174 default:
2175 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->fence->ring);
2176 ret = -EINVAL;
2177 break;
2178 }
2179 }
2180 idx += pkt.count + 2;
2181 break;
2182 default:
2183 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2184 ret = -EINVAL;
2185 break;
2186 }
2187 if (ret)
2188 break;
2189 } while (idx < ib->length_dw);
2190
2191 return ret;
2192}
2193
1885/* 2194/*
1886 * vm 2195 * vm
1887 */ 2196 */
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 4d9cdc813d81..ed1b1e5f5dd5 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -255,6 +255,8 @@
255#define SOFT_RESET_VGT (1 << 14) 255#define SOFT_RESET_VGT (1 << 14)
256#define SOFT_RESET_IA (1 << 15) 256#define SOFT_RESET_IA (1 << 15)
257 257
258#define GRBM_GFX_INDEX 0x802C
259
258#define CP_ME_CNTL 0x86D8 260#define CP_ME_CNTL 0x86D8
259#define CP_CE_HALT (1 << 24) 261#define CP_CE_HALT (1 << 24)
260#define CP_PFP_HALT (1 << 26) 262#define CP_PFP_HALT (1 << 26)
@@ -271,6 +273,8 @@
271 273
272#define CP_PERFMON_CNTL 0x87FC 274#define CP_PERFMON_CNTL 0x87FC
273 275
276#define VGT_VTX_VECT_EJECT_REG 0x88B0
277
274#define VGT_CACHE_INVALIDATION 0x88C4 278#define VGT_CACHE_INVALIDATION 0x88C4
275#define CACHE_INVALIDATION(x) ((x) << 0) 279#define CACHE_INVALIDATION(x) ((x) << 0)
276#define VC_ONLY 0 280#define VC_ONLY 0
@@ -281,11 +285,23 @@
281#define ES_AUTO 1 285#define ES_AUTO 1
282#define GS_AUTO 2 286#define GS_AUTO 2
283#define ES_AND_GS_AUTO 3 287#define ES_AND_GS_AUTO 3
288#define VGT_ESGS_RING_SIZE 0x88C8
289#define VGT_GSVS_RING_SIZE 0x88CC
284 290
285#define VGT_GS_VERTEX_REUSE 0x88D4 291#define VGT_GS_VERTEX_REUSE 0x88D4
286 292
293#define VGT_PRIMITIVE_TYPE 0x8958
294#define VGT_INDEX_TYPE 0x895C
295
296#define VGT_NUM_INDICES 0x8970
287#define VGT_NUM_INSTANCES 0x8974 297#define VGT_NUM_INSTANCES 0x8974
288 298
299#define VGT_TF_RING_SIZE 0x8988
300
301#define VGT_HS_OFFCHIP_PARAM 0x89B0
302
303#define VGT_TF_MEMORY_BASE 0x89B8
304
289#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 305#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
290#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 306#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
291 307
@@ -293,6 +309,8 @@
293#define CLIP_VTX_REORDER_ENA (1 << 0) 309#define CLIP_VTX_REORDER_ENA (1 << 0)
294#define NUM_CLIP_SEQ(x) ((x) << 1) 310#define NUM_CLIP_SEQ(x) ((x) << 1)
295 311
312#define PA_SU_LINE_STIPPLE_VALUE 0x8A60
313
296#define PA_SC_LINE_STIPPLE_STATE 0x8B10 314#define PA_SC_LINE_STIPPLE_STATE 0x8B10
297 315
298#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 316#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
@@ -305,10 +323,21 @@
305#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 323#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
306#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 324#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
307 325
326#define PA_SC_ENHANCE 0x8BF0
327
308#define SQ_CONFIG 0x8C00 328#define SQ_CONFIG 0x8C00
309 329
330#define SQC_CACHES 0x8C08
331
310#define SX_DEBUG_1 0x9060 332#define SX_DEBUG_1 0x9060
311 333
334#define SPI_STATIC_THREAD_MGMT_1 0x90E0
335#define SPI_STATIC_THREAD_MGMT_2 0x90E4
336#define SPI_STATIC_THREAD_MGMT_3 0x90E8
337#define SPI_PS_MAX_WAVE_ID 0x90EC
338
339#define SPI_CONFIG_CNTL 0x9100
340
312#define SPI_CONFIG_CNTL_1 0x913C 341#define SPI_CONFIG_CNTL_1 0x913C
313#define VTX_DONE_DELAY(x) ((x) << 0) 342#define VTX_DONE_DELAY(x) ((x) << 0)
314#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 343#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
@@ -318,6 +347,8 @@
318#define TCC_DISABLE_MASK 0xFFFF0000 347#define TCC_DISABLE_MASK 0xFFFF0000
319#define TCC_DISABLE_SHIFT 16 348#define TCC_DISABLE_SHIFT 16
320 349
350#define TA_CNTL_AUX 0x9508
351
321#define CC_RB_BACKEND_DISABLE 0x98F4 352#define CC_RB_BACKEND_DISABLE 0x98F4
322#define BACKEND_DISABLE(x) ((x) << 16) 353#define BACKEND_DISABLE(x) ((x) << 16)
323#define GB_ADDR_CONFIG 0x98F8 354#define GB_ADDR_CONFIG 0x98F8
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-28 18:11:37 -0500