drm/radeon/kms: allow rendering while no colorbuffer is set on r300

Because hardware cannot disable all colorbuffers directly to do depth-only
rendering, a user should:
- disable reading from a colorbuffer in blending
- disable fastfill
- set the color channel mask to 0 to prevent writing to a colorbuffer

Signed-off-by: Dave Airlie <airlied@redhat.com>

3 files changed, 19 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 84e5df766d3f..71727460968f 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2881,6 +2881,10 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
 
         for (i = 0; i < track->num_cb; i++) {
                 if (track->cb[i].robj == NULL) {
+                        if (!(track->fastfill || track->color_channel_mask ||
+                              track->blend_read_enable)) {
+                                continue;
+                        }
                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
                         return -EINVAL;
                 }
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index 7188c3778ee2..b27a6999d219 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -67,13 +67,15 @@ struct r100_cs_track {
         unsigned                        immd_dwords;
         unsigned                        num_arrays;
         unsigned                        max_indx;
+        unsigned                        color_channel_mask;
         struct r100_cs_track_array      arrays[11];
         struct r100_cs_track_cb         cb[R300_MAX_CB];
         struct r100_cs_track_cb         zb;
         struct r100_cs_track_texture    textures[R300_TRACK_MAX_TEXTURE];
         bool                            z_enabled;
         bool                            separate_cube;
-
+        bool                            fastfill;
+        bool                            blend_read_enable;
 };
 
 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 83490c2b5061..6a5d1177afab 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -992,6 +992,18 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                 }
                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
                 break;
+        case 0x4e0c:
+                /* RB3D_COLOR_CHANNEL_MASK */
+                track->color_channel_mask = idx_value;
+                break;
+        case 0x4d1c:
+                /* ZB_BW_CNTL */
+                track->fastfill = !!(idx_value & (1 << 2));
+                break;
+        case 0x4e04:
+                /* RB3D_BLENDCNTL */
+                track->blend_read_enable = !!(idx_value & (1 << 2));
+                break;
         case 0x4be8:
                 /* valid register only on RV530 */
                 if (p->rdev->family == CHIP_RV530)