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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 22:40:34 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 22:40:34 -0400
commit20a2078ce7705a6e0722ef5184336eb8657a58d8 (patch)
tree5b927c96516380aa0ecd68d8a609f7cd72120ad5 /drivers/gpu/drm/radeon
parent0279b3c0ada1d78882f24acf94ac4595bd657a89 (diff)
parent307b9c022720f9de90d58e51743e01e9a42aec59 (diff)
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie: "This is the main drm pull request for 3.10. Wierd bits: - OMAP drm changes required OMAP dss changes, in drivers/video, so I took them in here. - one more fbcon fix for font handover - VT switch avoidance in pm code - scatterlist helpers for gpu drivers - have acks from akpm Highlights: - qxl kms driver - driver for the spice qxl virtual GPU Nouveau: - fermi/kepler VRAM compression - GK110/nvf0 modesetting support. Tegra: - host1x core merged with 2D engine support i915: - vt switchless resume - more valleyview support - vblank fixes - modesetting pipe config rework radeon: - UVD engine support - SI chip tiling support - GPU registers initialisation from golden values. exynos: - device tree changes - fimc block support Otherwise: - bunches of fixes all over the place." * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (513 commits) qxl: update to new idr interfaces. drm/nouveau: fix build with nv50->nvc0 drm/radeon: fix handling of v6 power tables drm/radeon: clarify family checks in pm table parsing drm/radeon: consolidate UVD clock programming drm/radeon: fix UPLL_REF_DIV_MASK definition radeon: add bo tracking debugfs drm/radeon: add new richland pci ids drm/radeon: add some new SI PCI ids drm/radeon: fix scratch reg handling for UVD fence drm/radeon: allocate SA bo in the requested domain drm/radeon: fix possible segfault when parsing pm tables drm/radeon: fix endian bugs in atom_allocate_fb_scratch() OMAPDSS: TFP410: return EPROBE_DEFER if the i2c adapter not found OMAPDSS: VENC: Add error handling for venc_probe_pdata OMAPDSS: HDMI: Add error handling for hdmi_probe_pdata OMAPDSS: RFBI: Add error handling for rfbi_probe_pdata OMAPDSS: DSI: Add error handling for dsi_probe_pdata OMAPDSS: SDI: Add error handling for sdi_probe_pdata OMAPDSS: DPI: Add error handling for dpi_probe_pdata ...
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/Makefile2
-rw-r--r--drivers/gpu/drm/radeon/atom.c6
-rw-r--r--drivers/gpu/drm/radeon/atombios.h2
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c3
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c17
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c1187
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c169
-rw-r--r--drivers/gpu/drm/radeon/evergreen_reg.h2
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h48
-rw-r--r--drivers/gpu/drm/radeon/ni.c414
-rw-r--r--drivers/gpu/drm/radeon/nid.h21
-rw-r--r--drivers/gpu/drm/radeon/r100.c77
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h2
-rw-r--r--drivers/gpu/drm/radeon/r600.c404
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c64
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c150
-rw-r--r--drivers/gpu/drm/radeon/r600d.h72
-rw-r--r--drivers/gpu/drm/radeon/radeon.h94
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c100
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h28
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c132
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c83
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c56
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c20
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c50
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c187
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h23
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c27
-rw-r--r--drivers/gpu/drm/radeon/radeon_sa.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_test.c72
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c831
-rw-r--r--drivers/gpu/drm/radeon/rs600.c52
-rw-r--r--drivers/gpu/drm/radeon/rs690.c23
-rw-r--r--drivers/gpu/drm/radeon/rs690d.h3
-rw-r--r--drivers/gpu/drm/radeon/rv515.c56
-rw-r--r--drivers/gpu/drm/radeon/rv770.c909
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h43
-rw-r--r--drivers/gpu/drm/radeon/si.c979
-rw-r--r--drivers/gpu/drm/radeon/sid.h40
43 files changed, 5916 insertions, 567 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index bf172522ea68..86c5e3611892 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -76,7 +76,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
76 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \ 76 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
77 evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ 77 evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
78 atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ 78 atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
79 si_blit_shaders.o radeon_prime.o 79 si_blit_shaders.o radeon_prime.o radeon_uvd.o
80 80
81radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 81radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
82radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o 82radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 46a9c3772850..fb441a790f3d 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -1394,10 +1394,10 @@ int atom_allocate_fb_scratch(struct atom_context *ctx)
1394 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); 1394 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1395 1395
1396 DRM_DEBUG("atom firmware requested %08x %dkb\n", 1396 DRM_DEBUG("atom firmware requested %08x %dkb\n",
1397 firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware, 1397 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1398 firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb); 1398 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1399 1399
1400 usage_bytes = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024; 1400 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1401 } 1401 }
1402 ctx->scratch_size_bytes = 0; 1402 ctx->scratch_size_bytes = 0;
1403 if (usage_bytes == 0) 1403 if (usage_bytes == 0)
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 4b04ba3828e8..0ee573743de9 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -458,6 +458,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
458 union 458 union
459 { 459 {
460 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 460 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
461 ULONG ulClockParams; //ULONG access for BE
461 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 462 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
462 }; 463 };
463 UCHAR ucRefDiv; //Output Parameter 464 UCHAR ucRefDiv; //Output Parameter
@@ -490,6 +491,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
490 union 491 union
491 { 492 {
492 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 493 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
494 ULONG ulClockParams; //ULONG access for BE
493 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 495 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
494 }; 496 };
495 UCHAR ucRefDiv; //Output Parameter 497 UCHAR ucRefDiv; //Output Parameter
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 21a892c6ab9c..6d6fdb3ba0d0 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -557,6 +557,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
557 /* use frac fb div on APUs */ 557 /* use frac fb div on APUs */
558 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 558 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
559 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 559 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
560 /* use frac fb div on RS780/RS880 */
561 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
562 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
560 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 563 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
561 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 564 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
562 } else { 565 } else {
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 4552d4aff317..44a7da66e081 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -2150,13 +2150,10 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2150 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2150 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2151 2151
2152 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2152 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2153 r600_hdmi_enable(encoder); 2153 if (rdev->asic->display.hdmi_enable)
2154 if (ASIC_IS_DCE6(rdev)) 2154 radeon_hdmi_enable(rdev, encoder, true);
2155 ; /* TODO (use pointers instead of if-s?) */ 2155 if (rdev->asic->display.hdmi_setmode)
2156 else if (ASIC_IS_DCE4(rdev)) 2156 radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2157 evergreen_hdmi_setmode(encoder, adjusted_mode);
2158 else
2159 r600_hdmi_setmode(encoder, adjusted_mode);
2160 } 2157 }
2161} 2158}
2162 2159
@@ -2413,8 +2410,10 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2413 2410
2414disable_done: 2411disable_done:
2415 if (radeon_encoder_is_digital(encoder)) { 2412 if (radeon_encoder_is_digital(encoder)) {
2416 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 2413 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2417 r600_hdmi_disable(encoder); 2414 if (rdev->asic->display.hdmi_enable)
2415 radeon_hdmi_enable(rdev, encoder, false);
2416 }
2418 dig = radeon_encoder->enc_priv; 2417 dig = radeon_encoder->enc_priv;
2419 dig->dig_encoder = -1; 2418 dig->dig_encoder = -1;
2420 } 2419 }
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 305a657bf215..105bafb6c29d 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -53,6 +53,864 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
53extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 53extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
54 int ring, u32 cp_int_cntl); 54 int ring, u32 cp_int_cntl);
55 55
56static const u32 evergreen_golden_registers[] =
57{
58 0x3f90, 0xffff0000, 0xff000000,
59 0x9148, 0xffff0000, 0xff000000,
60 0x3f94, 0xffff0000, 0xff000000,
61 0x914c, 0xffff0000, 0xff000000,
62 0x9b7c, 0xffffffff, 0x00000000,
63 0x8a14, 0xffffffff, 0x00000007,
64 0x8b10, 0xffffffff, 0x00000000,
65 0x960c, 0xffffffff, 0x54763210,
66 0x88c4, 0xffffffff, 0x000000c2,
67 0x88d4, 0xffffffff, 0x00000010,
68 0x8974, 0xffffffff, 0x00000000,
69 0xc78, 0x00000080, 0x00000080,
70 0x5eb4, 0xffffffff, 0x00000002,
71 0x5e78, 0xffffffff, 0x001000f0,
72 0x6104, 0x01000300, 0x00000000,
73 0x5bc0, 0x00300000, 0x00000000,
74 0x7030, 0xffffffff, 0x00000011,
75 0x7c30, 0xffffffff, 0x00000011,
76 0x10830, 0xffffffff, 0x00000011,
77 0x11430, 0xffffffff, 0x00000011,
78 0x12030, 0xffffffff, 0x00000011,
79 0x12c30, 0xffffffff, 0x00000011,
80 0xd02c, 0xffffffff, 0x08421000,
81 0x240c, 0xffffffff, 0x00000380,
82 0x8b24, 0xffffffff, 0x00ff0fff,
83 0x28a4c, 0x06000000, 0x06000000,
84 0x10c, 0x00000001, 0x00000001,
85 0x8d00, 0xffffffff, 0x100e4848,
86 0x8d04, 0xffffffff, 0x00164745,
87 0x8c00, 0xffffffff, 0xe4000003,
88 0x8c04, 0xffffffff, 0x40600060,
89 0x8c08, 0xffffffff, 0x001c001c,
90 0x8cf0, 0xffffffff, 0x08e00620,
91 0x8c20, 0xffffffff, 0x00800080,
92 0x8c24, 0xffffffff, 0x00800080,
93 0x8c18, 0xffffffff, 0x20202078,
94 0x8c1c, 0xffffffff, 0x00001010,
95 0x28350, 0xffffffff, 0x00000000,
96 0xa008, 0xffffffff, 0x00010000,
97 0x5cc, 0xffffffff, 0x00000001,
98 0x9508, 0xffffffff, 0x00000002,
99 0x913c, 0x0000000f, 0x0000000a
100};
101
102static const u32 evergreen_golden_registers2[] =
103{
104 0x2f4c, 0xffffffff, 0x00000000,
105 0x54f4, 0xffffffff, 0x00000000,
106 0x54f0, 0xffffffff, 0x00000000,
107 0x5498, 0xffffffff, 0x00000000,
108 0x549c, 0xffffffff, 0x00000000,
109 0x5494, 0xffffffff, 0x00000000,
110 0x53cc, 0xffffffff, 0x00000000,
111 0x53c8, 0xffffffff, 0x00000000,
112 0x53c4, 0xffffffff, 0x00000000,
113 0x53c0, 0xffffffff, 0x00000000,
114 0x53bc, 0xffffffff, 0x00000000,
115 0x53b8, 0xffffffff, 0x00000000,
116 0x53b4, 0xffffffff, 0x00000000,
117 0x53b0, 0xffffffff, 0x00000000
118};
119
120static const u32 cypress_mgcg_init[] =
121{
122 0x802c, 0xffffffff, 0xc0000000,
123 0x5448, 0xffffffff, 0x00000100,
124 0x55e4, 0xffffffff, 0x00000100,
125 0x160c, 0xffffffff, 0x00000100,
126 0x5644, 0xffffffff, 0x00000100,
127 0xc164, 0xffffffff, 0x00000100,
128 0x8a18, 0xffffffff, 0x00000100,
129 0x897c, 0xffffffff, 0x06000100,
130 0x8b28, 0xffffffff, 0x00000100,
131 0x9144, 0xffffffff, 0x00000100,
132 0x9a60, 0xffffffff, 0x00000100,
133 0x9868, 0xffffffff, 0x00000100,
134 0x8d58, 0xffffffff, 0x00000100,
135 0x9510, 0xffffffff, 0x00000100,
136 0x949c, 0xffffffff, 0x00000100,
137 0x9654, 0xffffffff, 0x00000100,
138 0x9030, 0xffffffff, 0x00000100,
139 0x9034, 0xffffffff, 0x00000100,
140 0x9038, 0xffffffff, 0x00000100,
141 0x903c, 0xffffffff, 0x00000100,
142 0x9040, 0xffffffff, 0x00000100,
143 0xa200, 0xffffffff, 0x00000100,
144 0xa204, 0xffffffff, 0x00000100,
145 0xa208, 0xffffffff, 0x00000100,
146 0xa20c, 0xffffffff, 0x00000100,
147 0x971c, 0xffffffff, 0x00000100,
148 0x977c, 0xffffffff, 0x00000100,
149 0x3f80, 0xffffffff, 0x00000100,
150 0xa210, 0xffffffff, 0x00000100,
151 0xa214, 0xffffffff, 0x00000100,
152 0x4d8, 0xffffffff, 0x00000100,
153 0x9784, 0xffffffff, 0x00000100,
154 0x9698, 0xffffffff, 0x00000100,
155 0x4d4, 0xffffffff, 0x00000200,
156 0x30cc, 0xffffffff, 0x00000100,
157 0xd0c0, 0xffffffff, 0xff000100,
158 0x802c, 0xffffffff, 0x40000000,
159 0x915c, 0xffffffff, 0x00010000,
160 0x9160, 0xffffffff, 0x00030002,
161 0x9178, 0xffffffff, 0x00070000,
162 0x917c, 0xffffffff, 0x00030002,
163 0x9180, 0xffffffff, 0x00050004,
164 0x918c, 0xffffffff, 0x00010006,
165 0x9190, 0xffffffff, 0x00090008,
166 0x9194, 0xffffffff, 0x00070000,
167 0x9198, 0xffffffff, 0x00030002,
168 0x919c, 0xffffffff, 0x00050004,
169 0x91a8, 0xffffffff, 0x00010006,
170 0x91ac, 0xffffffff, 0x00090008,
171 0x91b0, 0xffffffff, 0x00070000,
172 0x91b4, 0xffffffff, 0x00030002,
173 0x91b8, 0xffffffff, 0x00050004,
174 0x91c4, 0xffffffff, 0x00010006,
175 0x91c8, 0xffffffff, 0x00090008,
176 0x91cc, 0xffffffff, 0x00070000,
177 0x91d0, 0xffffffff, 0x00030002,
178 0x91d4, 0xffffffff, 0x00050004,
179 0x91e0, 0xffffffff, 0x00010006,
180 0x91e4, 0xffffffff, 0x00090008,
181 0x91e8, 0xffffffff, 0x00000000,
182 0x91ec, 0xffffffff, 0x00070000,
183 0x91f0, 0xffffffff, 0x00030002,
184 0x91f4, 0xffffffff, 0x00050004,
185 0x9200, 0xffffffff, 0x00010006,
186 0x9204, 0xffffffff, 0x00090008,
187 0x9208, 0xffffffff, 0x00070000,
188 0x920c, 0xffffffff, 0x00030002,
189 0x9210, 0xffffffff, 0x00050004,
190 0x921c, 0xffffffff, 0x00010006,
191 0x9220, 0xffffffff, 0x00090008,
192 0x9224, 0xffffffff, 0x00070000,
193 0x9228, 0xffffffff, 0x00030002,
194 0x922c, 0xffffffff, 0x00050004,
195 0x9238, 0xffffffff, 0x00010006,
196 0x923c, 0xffffffff, 0x00090008,
197 0x9240, 0xffffffff, 0x00070000,
198 0x9244, 0xffffffff, 0x00030002,
199 0x9248, 0xffffffff, 0x00050004,
200 0x9254, 0xffffffff, 0x00010006,
201 0x9258, 0xffffffff, 0x00090008,
202 0x925c, 0xffffffff, 0x00070000,
203 0x9260, 0xffffffff, 0x00030002,
204 0x9264, 0xffffffff, 0x00050004,
205 0x9270, 0xffffffff, 0x00010006,
206 0x9274, 0xffffffff, 0x00090008,
207 0x9278, 0xffffffff, 0x00070000,
208 0x927c, 0xffffffff, 0x00030002,
209 0x9280, 0xffffffff, 0x00050004,
210 0x928c, 0xffffffff, 0x00010006,
211 0x9290, 0xffffffff, 0x00090008,
212 0x9294, 0xffffffff, 0x00000000,
213 0x929c, 0xffffffff, 0x00000001,
214 0x802c, 0xffffffff, 0x40010000,
215 0x915c, 0xffffffff, 0x00010000,
216 0x9160, 0xffffffff, 0x00030002,
217 0x9178, 0xffffffff, 0x00070000,
218 0x917c, 0xffffffff, 0x00030002,
219 0x9180, 0xffffffff, 0x00050004,
220 0x918c, 0xffffffff, 0x00010006,
221 0x9190, 0xffffffff, 0x00090008,
222 0x9194, 0xffffffff, 0x00070000,
223 0x9198, 0xffffffff, 0x00030002,
224 0x919c, 0xffffffff, 0x00050004,
225 0x91a8, 0xffffffff, 0x00010006,
226 0x91ac, 0xffffffff, 0x00090008,
227 0x91b0, 0xffffffff, 0x00070000,
228 0x91b4, 0xffffffff, 0x00030002,
229 0x91b8, 0xffffffff, 0x00050004,
230 0x91c4, 0xffffffff, 0x00010006,
231 0x91c8, 0xffffffff, 0x00090008,
232 0x91cc, 0xffffffff, 0x00070000,
233 0x91d0, 0xffffffff, 0x00030002,
234 0x91d4, 0xffffffff, 0x00050004,
235 0x91e0, 0xffffffff, 0x00010006,
236 0x91e4, 0xffffffff, 0x00090008,
237 0x91e8, 0xffffffff, 0x00000000,
238 0x91ec, 0xffffffff, 0x00070000,
239 0x91f0, 0xffffffff, 0x00030002,
240 0x91f4, 0xffffffff, 0x00050004,
241 0x9200, 0xffffffff, 0x00010006,
242 0x9204, 0xffffffff, 0x00090008,
243 0x9208, 0xffffffff, 0x00070000,
244 0x920c, 0xffffffff, 0x00030002,
245 0x9210, 0xffffffff, 0x00050004,
246 0x921c, 0xffffffff, 0x00010006,
247 0x9220, 0xffffffff, 0x00090008,
248 0x9224, 0xffffffff, 0x00070000,
249 0x9228, 0xffffffff, 0x00030002,
250 0x922c, 0xffffffff, 0x00050004,
251 0x9238, 0xffffffff, 0x00010006,
252 0x923c, 0xffffffff, 0x00090008,
253 0x9240, 0xffffffff, 0x00070000,
254 0x9244, 0xffffffff, 0x00030002,
255 0x9248, 0xffffffff, 0x00050004,
256 0x9254, 0xffffffff, 0x00010006,
257 0x9258, 0xffffffff, 0x00090008,
258 0x925c, 0xffffffff, 0x00070000,
259 0x9260, 0xffffffff, 0x00030002,
260 0x9264, 0xffffffff, 0x00050004,
261 0x9270, 0xffffffff, 0x00010006,
262 0x9274, 0xffffffff, 0x00090008,
263 0x9278, 0xffffffff, 0x00070000,
264 0x927c, 0xffffffff, 0x00030002,
265 0x9280, 0xffffffff, 0x00050004,
266 0x928c, 0xffffffff, 0x00010006,
267 0x9290, 0xffffffff, 0x00090008,
268 0x9294, 0xffffffff, 0x00000000,
269 0x929c, 0xffffffff, 0x00000001,
270 0x802c, 0xffffffff, 0xc0000000
271};
272
273static const u32 redwood_mgcg_init[] =
274{
275 0x802c, 0xffffffff, 0xc0000000,
276 0x5448, 0xffffffff, 0x00000100,
277 0x55e4, 0xffffffff, 0x00000100,
278 0x160c, 0xffffffff, 0x00000100,
279 0x5644, 0xffffffff, 0x00000100,
280 0xc164, 0xffffffff, 0x00000100,
281 0x8a18, 0xffffffff, 0x00000100,
282 0x897c, 0xffffffff, 0x06000100,
283 0x8b28, 0xffffffff, 0x00000100,
284 0x9144, 0xffffffff, 0x00000100,
285 0x9a60, 0xffffffff, 0x00000100,
286 0x9868, 0xffffffff, 0x00000100,
287 0x8d58, 0xffffffff, 0x00000100,
288 0x9510, 0xffffffff, 0x00000100,
289 0x949c, 0xffffffff, 0x00000100,
290 0x9654, 0xffffffff, 0x00000100,
291 0x9030, 0xffffffff, 0x00000100,
292 0x9034, 0xffffffff, 0x00000100,
293 0x9038, 0xffffffff, 0x00000100,
294 0x903c, 0xffffffff, 0x00000100,
295 0x9040, 0xffffffff, 0x00000100,
296 0xa200, 0xffffffff, 0x00000100,
297 0xa204, 0xffffffff, 0x00000100,
298 0xa208, 0xffffffff, 0x00000100,
299 0xa20c, 0xffffffff, 0x00000100,
300 0x971c, 0xffffffff, 0x00000100,
301 0x977c, 0xffffffff, 0x00000100,
302 0x3f80, 0xffffffff, 0x00000100,
303 0xa210, 0xffffffff, 0x00000100,
304 0xa214, 0xffffffff, 0x00000100,
305 0x4d8, 0xffffffff, 0x00000100,
306 0x9784, 0xffffffff, 0x00000100,
307 0x9698, 0xffffffff, 0x00000100,
308 0x4d4, 0xffffffff, 0x00000200,
309 0x30cc, 0xffffffff, 0x00000100,
310 0xd0c0, 0xffffffff, 0xff000100,
311 0x802c, 0xffffffff, 0x40000000,
312 0x915c, 0xffffffff, 0x00010000,
313 0x9160, 0xffffffff, 0x00030002,
314 0x9178, 0xffffffff, 0x00070000,
315 0x917c, 0xffffffff, 0x00030002,
316 0x9180, 0xffffffff, 0x00050004,
317 0x918c, 0xffffffff, 0x00010006,
318 0x9190, 0xffffffff, 0x00090008,
319 0x9194, 0xffffffff, 0x00070000,
320 0x9198, 0xffffffff, 0x00030002,
321 0x919c, 0xffffffff, 0x00050004,
322 0x91a8, 0xffffffff, 0x00010006,
323 0x91ac, 0xffffffff, 0x00090008,
324 0x91b0, 0xffffffff, 0x00070000,
325 0x91b4, 0xffffffff, 0x00030002,
326 0x91b8, 0xffffffff, 0x00050004,
327 0x91c4, 0xffffffff, 0x00010006,
328 0x91c8, 0xffffffff, 0x00090008,
329 0x91cc, 0xffffffff, 0x00070000,
330 0x91d0, 0xffffffff, 0x00030002,
331 0x91d4, 0xffffffff, 0x00050004,
332 0x91e0, 0xffffffff, 0x00010006,
333 0x91e4, 0xffffffff, 0x00090008,
334 0x91e8, 0xffffffff, 0x00000000,
335 0x91ec, 0xffffffff, 0x00070000,
336 0x91f0, 0xffffffff, 0x00030002,
337 0x91f4, 0xffffffff, 0x00050004,
338 0x9200, 0xffffffff, 0x00010006,
339 0x9204, 0xffffffff, 0x00090008,
340 0x9294, 0xffffffff, 0x00000000,
341 0x929c, 0xffffffff, 0x00000001,
342 0x802c, 0xffffffff, 0xc0000000
343};
344
345static const u32 cedar_golden_registers[] =
346{
347 0x3f90, 0xffff0000, 0xff000000,
348 0x9148, 0xffff0000, 0xff000000,
349 0x3f94, 0xffff0000, 0xff000000,
350 0x914c, 0xffff0000, 0xff000000,
351 0x9b7c, 0xffffffff, 0x00000000,
352 0x8a14, 0xffffffff, 0x00000007,
353 0x8b10, 0xffffffff, 0x00000000,
354 0x960c, 0xffffffff, 0x54763210,
355 0x88c4, 0xffffffff, 0x000000c2,
356 0x88d4, 0xffffffff, 0x00000000,
357 0x8974, 0xffffffff, 0x00000000,
358 0xc78, 0x00000080, 0x00000080,
359 0x5eb4, 0xffffffff, 0x00000002,
360 0x5e78, 0xffffffff, 0x001000f0,
361 0x6104, 0x01000300, 0x00000000,
362 0x5bc0, 0x00300000, 0x00000000,
363 0x7030, 0xffffffff, 0x00000011,
364 0x7c30, 0xffffffff, 0x00000011,
365 0x10830, 0xffffffff, 0x00000011,
366 0x11430, 0xffffffff, 0x00000011,
367 0xd02c, 0xffffffff, 0x08421000,
368 0x240c, 0xffffffff, 0x00000380,
369 0x8b24, 0xffffffff, 0x00ff0fff,
370 0x28a4c, 0x06000000, 0x06000000,
371 0x10c, 0x00000001, 0x00000001,
372 0x8d00, 0xffffffff, 0x100e4848,
373 0x8d04, 0xffffffff, 0x00164745,
374 0x8c00, 0xffffffff, 0xe4000003,
375 0x8c04, 0xffffffff, 0x40600060,
376 0x8c08, 0xffffffff, 0x001c001c,
377 0x8cf0, 0xffffffff, 0x08e00410,
378 0x8c20, 0xffffffff, 0x00800080,
379 0x8c24, 0xffffffff, 0x00800080,
380 0x8c18, 0xffffffff, 0x20202078,
381 0x8c1c, 0xffffffff, 0x00001010,
382 0x28350, 0xffffffff, 0x00000000,
383 0xa008, 0xffffffff, 0x00010000,
384 0x5cc, 0xffffffff, 0x00000001,
385 0x9508, 0xffffffff, 0x00000002
386};
387
388static const u32 cedar_mgcg_init[] =
389{
390 0x802c, 0xffffffff, 0xc0000000,
391 0x5448, 0xffffffff, 0x00000100,
392 0x55e4, 0xffffffff, 0x00000100,
393 0x160c, 0xffffffff, 0x00000100,
394 0x5644, 0xffffffff, 0x00000100,
395 0xc164, 0xffffffff, 0x00000100,
396 0x8a18, 0xffffffff, 0x00000100,
397 0x897c, 0xffffffff, 0x06000100,
398 0x8b28, 0xffffffff, 0x00000100,
399 0x9144, 0xffffffff, 0x00000100,
400 0x9a60, 0xffffffff, 0x00000100,
401 0x9868, 0xffffffff, 0x00000100,
402 0x8d58, 0xffffffff, 0x00000100,
403 0x9510, 0xffffffff, 0x00000100,
404 0x949c, 0xffffffff, 0x00000100,
405 0x9654, 0xffffffff, 0x00000100,
406 0x9030, 0xffffffff, 0x00000100,
407 0x9034, 0xffffffff, 0x00000100,
408 0x9038, 0xffffffff, 0x00000100,
409 0x903c, 0xffffffff, 0x00000100,
410 0x9040, 0xffffffff, 0x00000100,
411 0xa200, 0xffffffff, 0x00000100,
412 0xa204, 0xffffffff, 0x00000100,
413 0xa208, 0xffffffff, 0x00000100,
414 0xa20c, 0xffffffff, 0x00000100,
415 0x971c, 0xffffffff, 0x00000100,
416 0x977c, 0xffffffff, 0x00000100,
417 0x3f80, 0xffffffff, 0x00000100,
418 0xa210, 0xffffffff, 0x00000100,
419 0xa214, 0xffffffff, 0x00000100,
420 0x4d8, 0xffffffff, 0x00000100,
421 0x9784, 0xffffffff, 0x00000100,
422 0x9698, 0xffffffff, 0x00000100,
423 0x4d4, 0xffffffff, 0x00000200,
424 0x30cc, 0xffffffff, 0x00000100,
425 0xd0c0, 0xffffffff, 0xff000100,
426 0x802c, 0xffffffff, 0x40000000,
427 0x915c, 0xffffffff, 0x00010000,
428 0x9178, 0xffffffff, 0x00050000,
429 0x917c, 0xffffffff, 0x00030002,
430 0x918c, 0xffffffff, 0x00010004,
431 0x9190, 0xffffffff, 0x00070006,
432 0x9194, 0xffffffff, 0x00050000,
433 0x9198, 0xffffffff, 0x00030002,
434 0x91a8, 0xffffffff, 0x00010004,
435 0x91ac, 0xffffffff, 0x00070006,
436 0x91e8, 0xffffffff, 0x00000000,
437 0x9294, 0xffffffff, 0x00000000,
438 0x929c, 0xffffffff, 0x00000001,
439 0x802c, 0xffffffff, 0xc0000000
440};
441
442static const u32 juniper_mgcg_init[] =
443{
444 0x802c, 0xffffffff, 0xc0000000,
445 0x5448, 0xffffffff, 0x00000100,
446 0x55e4, 0xffffffff, 0x00000100,
447 0x160c, 0xffffffff, 0x00000100,
448 0x5644, 0xffffffff, 0x00000100,
449 0xc164, 0xffffffff, 0x00000100,
450 0x8a18, 0xffffffff, 0x00000100,
451 0x897c, 0xffffffff, 0x06000100,
452 0x8b28, 0xffffffff, 0x00000100,
453 0x9144, 0xffffffff, 0x00000100,
454 0x9a60, 0xffffffff, 0x00000100,
455 0x9868, 0xffffffff, 0x00000100,
456 0x8d58, 0xffffffff, 0x00000100,
457 0x9510, 0xffffffff, 0x00000100,
458 0x949c, 0xffffffff, 0x00000100,
459 0x9654, 0xffffffff, 0x00000100,
460 0x9030, 0xffffffff, 0x00000100,
461 0x9034, 0xffffffff, 0x00000100,
462 0x9038, 0xffffffff, 0x00000100,
463 0x903c, 0xffffffff, 0x00000100,
464 0x9040, 0xffffffff, 0x00000100,
465 0xa200, 0xffffffff, 0x00000100,
466 0xa204, 0xffffffff, 0x00000100,
467 0xa208, 0xffffffff, 0x00000100,
468 0xa20c, 0xffffffff, 0x00000100,
469 0x971c, 0xffffffff, 0x00000100,
470 0xd0c0, 0xffffffff, 0xff000100,
471 0x802c, 0xffffffff, 0x40000000,
472 0x915c, 0xffffffff, 0x00010000,
473 0x9160, 0xffffffff, 0x00030002,
474 0x9178, 0xffffffff, 0x00070000,
475 0x917c, 0xffffffff, 0x00030002,
476 0x9180, 0xffffffff, 0x00050004,
477 0x918c, 0xffffffff, 0x00010006,
478 0x9190, 0xffffffff, 0x00090008,
479 0x9194, 0xffffffff, 0x00070000,
480 0x9198, 0xffffffff, 0x00030002,
481 0x919c, 0xffffffff, 0x00050004,
482 0x91a8, 0xffffffff, 0x00010006,
483 0x91ac, 0xffffffff, 0x00090008,
484 0x91b0, 0xffffffff, 0x00070000,
485 0x91b4, 0xffffffff, 0x00030002,
486 0x91b8, 0xffffffff, 0x00050004,
487 0x91c4, 0xffffffff, 0x00010006,
488 0x91c8, 0xffffffff, 0x00090008,
489 0x91cc, 0xffffffff, 0x00070000,
490 0x91d0, 0xffffffff, 0x00030002,
491 0x91d4, 0xffffffff, 0x00050004,
492 0x91e0, 0xffffffff, 0x00010006,
493 0x91e4, 0xffffffff, 0x00090008,
494 0x91e8, 0xffffffff, 0x00000000,
495 0x91ec, 0xffffffff, 0x00070000,
496 0x91f0, 0xffffffff, 0x00030002,
497 0x91f4, 0xffffffff, 0x00050004,
498 0x9200, 0xffffffff, 0x00010006,
499 0x9204, 0xffffffff, 0x00090008,
500 0x9208, 0xffffffff, 0x00070000,
501 0x920c, 0xffffffff, 0x00030002,
502 0x9210, 0xffffffff, 0x00050004,
503 0x921c, 0xffffffff, 0x00010006,
504 0x9220, 0xffffffff, 0x00090008,
505 0x9224, 0xffffffff, 0x00070000,
506 0x9228, 0xffffffff, 0x00030002,
507 0x922c, 0xffffffff, 0x00050004,
508 0x9238, 0xffffffff, 0x00010006,
509 0x923c, 0xffffffff, 0x00090008,
510 0x9240, 0xffffffff, 0x00070000,
511 0x9244, 0xffffffff, 0x00030002,
512 0x9248, 0xffffffff, 0x00050004,
513 0x9254, 0xffffffff, 0x00010006,
514 0x9258, 0xffffffff, 0x00090008,
515 0x925c, 0xffffffff, 0x00070000,
516 0x9260, 0xffffffff, 0x00030002,
517 0x9264, 0xffffffff, 0x00050004,
518 0x9270, 0xffffffff, 0x00010006,
519 0x9274, 0xffffffff, 0x00090008,
520 0x9278, 0xffffffff, 0x00070000,
521 0x927c, 0xffffffff, 0x00030002,
522 0x9280, 0xffffffff, 0x00050004,
523 0x928c, 0xffffffff, 0x00010006,
524 0x9290, 0xffffffff, 0x00090008,
525 0x9294, 0xffffffff, 0x00000000,
526 0x929c, 0xffffffff, 0x00000001,
527 0x802c, 0xffffffff, 0xc0000000,
528 0x977c, 0xffffffff, 0x00000100,
529 0x3f80, 0xffffffff, 0x00000100,
530 0xa210, 0xffffffff, 0x00000100,
531 0xa214, 0xffffffff, 0x00000100,
532 0x4d8, 0xffffffff, 0x00000100,
533 0x9784, 0xffffffff, 0x00000100,
534 0x9698, 0xffffffff, 0x00000100,
535 0x4d4, 0xffffffff, 0x00000200,
536 0x30cc, 0xffffffff, 0x00000100,
537 0x802c, 0xffffffff, 0xc0000000
538};
539
540static const u32 supersumo_golden_registers[] =
541{
542 0x5eb4, 0xffffffff, 0x00000002,
543 0x5cc, 0xffffffff, 0x00000001,
544 0x7030, 0xffffffff, 0x00000011,
545 0x7c30, 0xffffffff, 0x00000011,
546 0x6104, 0x01000300, 0x00000000,
547 0x5bc0, 0x00300000, 0x00000000,
548 0x8c04, 0xffffffff, 0x40600060,
549 0x8c08, 0xffffffff, 0x001c001c,
550 0x8c20, 0xffffffff, 0x00800080,
551 0x8c24, 0xffffffff, 0x00800080,
552 0x8c18, 0xffffffff, 0x20202078,
553 0x8c1c, 0xffffffff, 0x00001010,
554 0x918c, 0xffffffff, 0x00010006,
555 0x91a8, 0xffffffff, 0x00010006,
556 0x91c4, 0xffffffff, 0x00010006,
557 0x91e0, 0xffffffff, 0x00010006,
558 0x9200, 0xffffffff, 0x00010006,
559 0x9150, 0xffffffff, 0x6e944040,
560 0x917c, 0xffffffff, 0x00030002,
561 0x9180, 0xffffffff, 0x00050004,
562 0x9198, 0xffffffff, 0x00030002,
563 0x919c, 0xffffffff, 0x00050004,
564 0x91b4, 0xffffffff, 0x00030002,
565 0x91b8, 0xffffffff, 0x00050004,
566 0x91d0, 0xffffffff, 0x00030002,
567 0x91d4, 0xffffffff, 0x00050004,
568 0x91f0, 0xffffffff, 0x00030002,
569 0x91f4, 0xffffffff, 0x00050004,
570 0x915c, 0xffffffff, 0x00010000,
571 0x9160, 0xffffffff, 0x00030002,
572 0x3f90, 0xffff0000, 0xff000000,
573 0x9178, 0xffffffff, 0x00070000,
574 0x9194, 0xffffffff, 0x00070000,
575 0x91b0, 0xffffffff, 0x00070000,
576 0x91cc, 0xffffffff, 0x00070000,
577 0x91ec, 0xffffffff, 0x00070000,
578 0x9148, 0xffff0000, 0xff000000,
579 0x9190, 0xffffffff, 0x00090008,
580 0x91ac, 0xffffffff, 0x00090008,
581 0x91c8, 0xffffffff, 0x00090008,
582 0x91e4, 0xffffffff, 0x00090008,
583 0x9204, 0xffffffff, 0x00090008,
584 0x3f94, 0xffff0000, 0xff000000,
585 0x914c, 0xffff0000, 0xff000000,
586 0x929c, 0xffffffff, 0x00000001,
587 0x8a18, 0xffffffff, 0x00000100,
588 0x8b28, 0xffffffff, 0x00000100,
589 0x9144, 0xffffffff, 0x00000100,
590 0x5644, 0xffffffff, 0x00000100,
591 0x9b7c, 0xffffffff, 0x00000000,
592 0x8030, 0xffffffff, 0x0000100a,
593 0x8a14, 0xffffffff, 0x00000007,
594 0x8b24, 0xffffffff, 0x00ff0fff,
595 0x8b10, 0xffffffff, 0x00000000,
596 0x28a4c, 0x06000000, 0x06000000,
597 0x4d8, 0xffffffff, 0x00000100,
598 0x913c, 0xffff000f, 0x0100000a,
599 0x960c, 0xffffffff, 0x54763210,
600 0x88c4, 0xffffffff, 0x000000c2,
601 0x88d4, 0xffffffff, 0x00000010,
602 0x8974, 0xffffffff, 0x00000000,
603 0xc78, 0x00000080, 0x00000080,
604 0x5e78, 0xffffffff, 0x001000f0,
605 0xd02c, 0xffffffff, 0x08421000,
606 0xa008, 0xffffffff, 0x00010000,
607 0x8d00, 0xffffffff, 0x100e4848,
608 0x8d04, 0xffffffff, 0x00164745,
609 0x8c00, 0xffffffff, 0xe4000003,
610 0x8cf0, 0x1fffffff, 0x08e00620,
611 0x28350, 0xffffffff, 0x00000000,
612 0x9508, 0xffffffff, 0x00000002
613};
614
615static const u32 sumo_golden_registers[] =
616{
617 0x900c, 0x00ffffff, 0x0017071f,
618 0x8c18, 0xffffffff, 0x10101060,
619 0x8c1c, 0xffffffff, 0x00001010,
620 0x8c30, 0x0000000f, 0x00000005,
621 0x9688, 0x0000000f, 0x00000007
622};
623
624static const u32 wrestler_golden_registers[] =
625{
626 0x5eb4, 0xffffffff, 0x00000002,
627 0x5cc, 0xffffffff, 0x00000001,
628 0x7030, 0xffffffff, 0x00000011,
629 0x7c30, 0xffffffff, 0x00000011,
630 0x6104, 0x01000300, 0x00000000,
631 0x5bc0, 0x00300000, 0x00000000,
632 0x918c, 0xffffffff, 0x00010006,
633 0x91a8, 0xffffffff, 0x00010006,
634 0x9150, 0xffffffff, 0x6e944040,
635 0x917c, 0xffffffff, 0x00030002,
636 0x9198, 0xffffffff, 0x00030002,
637 0x915c, 0xffffffff, 0x00010000,
638 0x3f90, 0xffff0000, 0xff000000,
639 0x9178, 0xffffffff, 0x00070000,
640 0x9194, 0xffffffff, 0x00070000,
641 0x9148, 0xffff0000, 0xff000000,
642 0x9190, 0xffffffff, 0x00090008,
643 0x91ac, 0xffffffff, 0x00090008,
644 0x3f94, 0xffff0000, 0xff000000,
645 0x914c, 0xffff0000, 0xff000000,
646 0x929c, 0xffffffff, 0x00000001,
647 0x8a18, 0xffffffff, 0x00000100,
648 0x8b28, 0xffffffff, 0x00000100,
649 0x9144, 0xffffffff, 0x00000100,
650 0x9b7c, 0xffffffff, 0x00000000,
651 0x8030, 0xffffffff, 0x0000100a,
652 0x8a14, 0xffffffff, 0x00000001,
653 0x8b24, 0xffffffff, 0x00ff0fff,
654 0x8b10, 0xffffffff, 0x00000000,
655 0x28a4c, 0x06000000, 0x06000000,
656 0x4d8, 0xffffffff, 0x00000100,
657 0x913c, 0xffff000f, 0x0100000a,
658 0x960c, 0xffffffff, 0x54763210,
659 0x88c4, 0xffffffff, 0x000000c2,
660 0x88d4, 0xffffffff, 0x00000010,
661 0x8974, 0xffffffff, 0x00000000,
662 0xc78, 0x00000080, 0x00000080,
663 0x5e78, 0xffffffff, 0x001000f0,
664 0xd02c, 0xffffffff, 0x08421000,
665 0xa008, 0xffffffff, 0x00010000,
666 0x8d00, 0xffffffff, 0x100e4848,
667 0x8d04, 0xffffffff, 0x00164745,
668 0x8c00, 0xffffffff, 0xe4000003,
669 0x8cf0, 0x1fffffff, 0x08e00410,
670 0x28350, 0xffffffff, 0x00000000,
671 0x9508, 0xffffffff, 0x00000002,
672 0x900c, 0xffffffff, 0x0017071f,
673 0x8c18, 0xffffffff, 0x10101060,
674 0x8c1c, 0xffffffff, 0x00001010
675};
676
677static const u32 barts_golden_registers[] =
678{
679 0x5eb4, 0xffffffff, 0x00000002,
680 0x5e78, 0x8f311ff1, 0x001000f0,
681 0x3f90, 0xffff0000, 0xff000000,
682 0x9148, 0xffff0000, 0xff000000,
683 0x3f94, 0xffff0000, 0xff000000,
684 0x914c, 0xffff0000, 0xff000000,
685 0xc78, 0x00000080, 0x00000080,
686 0xbd4, 0x70073777, 0x00010001,
687 0xd02c, 0xbfffff1f, 0x08421000,
688 0xd0b8, 0x03773777, 0x02011003,
689 0x5bc0, 0x00200000, 0x50100000,
690 0x98f8, 0x33773777, 0x02011003,
691 0x98fc, 0xffffffff, 0x76543210,
692 0x7030, 0x31000311, 0x00000011,
693 0x2f48, 0x00000007, 0x02011003,
694 0x6b28, 0x00000010, 0x00000012,
695 0x7728, 0x00000010, 0x00000012,
696 0x10328, 0x00000010, 0x00000012,
697 0x10f28, 0x00000010, 0x00000012,
698 0x11b28, 0x00000010, 0x00000012,
699 0x12728, 0x00000010, 0x00000012,
700 0x240c, 0x000007ff, 0x00000380,
701 0x8a14, 0xf000001f, 0x00000007,
702 0x8b24, 0x3fff3fff, 0x00ff0fff,
703 0x8b10, 0x0000ff0f, 0x00000000,
704 0x28a4c, 0x07ffffff, 0x06000000,
705 0x10c, 0x00000001, 0x00010003,
706 0xa02c, 0xffffffff, 0x0000009b,
707 0x913c, 0x0000000f, 0x0100000a,
708 0x8d00, 0xffff7f7f, 0x100e4848,
709 0x8d04, 0x00ffffff, 0x00164745,
710 0x8c00, 0xfffc0003, 0xe4000003,
711 0x8c04, 0xf8ff00ff, 0x40600060,
712 0x8c08, 0x00ff00ff, 0x001c001c,
713 0x8cf0, 0x1fff1fff, 0x08e00620,
714 0x8c20, 0x0fff0fff, 0x00800080,
715 0x8c24, 0x0fff0fff, 0x00800080,
716 0x8c18, 0xffffffff, 0x20202078,
717 0x8c1c, 0x0000ffff, 0x00001010,
718 0x28350, 0x00000f01, 0x00000000,
719 0x9508, 0x3700001f, 0x00000002,
720 0x960c, 0xffffffff, 0x54763210,
721 0x88c4, 0x001f3ae3, 0x000000c2,
722 0x88d4, 0x0000001f, 0x00000010,
723 0x8974, 0xffffffff, 0x00000000
724};
725
726static const u32 turks_golden_registers[] =
727{
728 0x5eb4, 0xffffffff, 0x00000002,
729 0x5e78, 0x8f311ff1, 0x001000f0,
730 0x8c8, 0x00003000, 0x00001070,
731 0x8cc, 0x000fffff, 0x00040035,
732 0x3f90, 0xffff0000, 0xfff00000,
733 0x9148, 0xffff0000, 0xfff00000,
734 0x3f94, 0xffff0000, 0xfff00000,
735 0x914c, 0xffff0000, 0xfff00000,
736 0xc78, 0x00000080, 0x00000080,
737 0xbd4, 0x00073007, 0x00010002,
738 0xd02c, 0xbfffff1f, 0x08421000,
739 0xd0b8, 0x03773777, 0x02010002,
740 0x5bc0, 0x00200000, 0x50100000,
741 0x98f8, 0x33773777, 0x00010002,
742 0x98fc, 0xffffffff, 0x33221100,
743 0x7030, 0x31000311, 0x00000011,
744 0x2f48, 0x33773777, 0x00010002,
745 0x6b28, 0x00000010, 0x00000012,
746 0x7728, 0x00000010, 0x00000012,
747 0x10328, 0x00000010, 0x00000012,
748 0x10f28, 0x00000010, 0x00000012,
749 0x11b28, 0x00000010, 0x00000012,
750 0x12728, 0x00000010, 0x00000012,
751 0x240c, 0x000007ff, 0x00000380,
752 0x8a14, 0xf000001f, 0x00000007,
753 0x8b24, 0x3fff3fff, 0x00ff0fff,
754 0x8b10, 0x0000ff0f, 0x00000000,
755 0x28a4c, 0x07ffffff, 0x06000000,
756 0x10c, 0x00000001, 0x00010003,
757 0xa02c, 0xffffffff, 0x0000009b,
758 0x913c, 0x0000000f, 0x0100000a,
759 0x8d00, 0xffff7f7f, 0x100e4848,
760 0x8d04, 0x00ffffff, 0x00164745,
761 0x8c00, 0xfffc0003, 0xe4000003,
762 0x8c04, 0xf8ff00ff, 0x40600060,
763 0x8c08, 0x00ff00ff, 0x001c001c,
764 0x8cf0, 0x1fff1fff, 0x08e00410,
765 0x8c20, 0x0fff0fff, 0x00800080,
766 0x8c24, 0x0fff0fff, 0x00800080,
767 0x8c18, 0xffffffff, 0x20202078,
768 0x8c1c, 0x0000ffff, 0x00001010,
769 0x28350, 0x00000f01, 0x00000000,
770 0x9508, 0x3700001f, 0x00000002,
771 0x960c, 0xffffffff, 0x54763210,
772 0x88c4, 0x001f3ae3, 0x000000c2,
773 0x88d4, 0x0000001f, 0x00000010,
774 0x8974, 0xffffffff, 0x00000000
775};
776
777static const u32 caicos_golden_registers[] =
778{
779 0x5eb4, 0xffffffff, 0x00000002,
780 0x5e78, 0x8f311ff1, 0x001000f0,
781 0x8c8, 0x00003420, 0x00001450,
782 0x8cc, 0x000fffff, 0x00040035,
783 0x3f90, 0xffff0000, 0xfffc0000,
784 0x9148, 0xffff0000, 0xfffc0000,
785 0x3f94, 0xffff0000, 0xfffc0000,
786 0x914c, 0xffff0000, 0xfffc0000,
787 0xc78, 0x00000080, 0x00000080,
788 0xbd4, 0x00073007, 0x00010001,
789 0xd02c, 0xbfffff1f, 0x08421000,
790 0xd0b8, 0x03773777, 0x02010001,
791 0x5bc0, 0x00200000, 0x50100000,
792 0x98f8, 0x33773777, 0x02010001,
793 0x98fc, 0xffffffff, 0x33221100,
794 0x7030, 0x31000311, 0x00000011,
795 0x2f48, 0x33773777, 0x02010001,
796 0x6b28, 0x00000010, 0x00000012,
797 0x7728, 0x00000010, 0x00000012,
798 0x10328, 0x00000010, 0x00000012,
799 0x10f28, 0x00000010, 0x00000012,
800 0x11b28, 0x00000010, 0x00000012,
801 0x12728, 0x00000010, 0x00000012,
802 0x240c, 0x000007ff, 0x00000380,
803 0x8a14, 0xf000001f, 0x00000001,
804 0x8b24, 0x3fff3fff, 0x00ff0fff,
805 0x8b10, 0x0000ff0f, 0x00000000,
806 0x28a4c, 0x07ffffff, 0x06000000,
807 0x10c, 0x00000001, 0x00010003,
808 0xa02c, 0xffffffff, 0x0000009b,
809 0x913c, 0x0000000f, 0x0100000a,
810 0x8d00, 0xffff7f7f, 0x100e4848,
811 0x8d04, 0x00ffffff, 0x00164745,
812 0x8c00, 0xfffc0003, 0xe4000003,
813 0x8c04, 0xf8ff00ff, 0x40600060,
814 0x8c08, 0x00ff00ff, 0x001c001c,
815 0x8cf0, 0x1fff1fff, 0x08e00410,
816 0x8c20, 0x0fff0fff, 0x00800080,
817 0x8c24, 0x0fff0fff, 0x00800080,
818 0x8c18, 0xffffffff, 0x20202078,
819 0x8c1c, 0x0000ffff, 0x00001010,
820 0x28350, 0x00000f01, 0x00000000,
821 0x9508, 0x3700001f, 0x00000002,
822 0x960c, 0xffffffff, 0x54763210,
823 0x88c4, 0x001f3ae3, 0x000000c2,
824 0x88d4, 0x0000001f, 0x00000010,
825 0x8974, 0xffffffff, 0x00000000
826};
827
828static void evergreen_init_golden_registers(struct radeon_device *rdev)
829{
830 switch (rdev->family) {
831 case CHIP_CYPRESS:
832 case CHIP_HEMLOCK:
833 radeon_program_register_sequence(rdev,
834 evergreen_golden_registers,
835 (const u32)ARRAY_SIZE(evergreen_golden_registers));
836 radeon_program_register_sequence(rdev,
837 evergreen_golden_registers2,
838 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
839 radeon_program_register_sequence(rdev,
840 cypress_mgcg_init,
841 (const u32)ARRAY_SIZE(cypress_mgcg_init));
842 break;
843 case CHIP_JUNIPER:
844 radeon_program_register_sequence(rdev,
845 evergreen_golden_registers,
846 (const u32)ARRAY_SIZE(evergreen_golden_registers));
847 radeon_program_register_sequence(rdev,
848 evergreen_golden_registers2,
849 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
850 radeon_program_register_sequence(rdev,
851 juniper_mgcg_init,
852 (const u32)ARRAY_SIZE(juniper_mgcg_init));
853 break;
854 case CHIP_REDWOOD:
855 radeon_program_register_sequence(rdev,
856 evergreen_golden_registers,
857 (const u32)ARRAY_SIZE(evergreen_golden_registers));
858 radeon_program_register_sequence(rdev,
859 evergreen_golden_registers2,
860 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
861 radeon_program_register_sequence(rdev,
862 redwood_mgcg_init,
863 (const u32)ARRAY_SIZE(redwood_mgcg_init));
864 break;
865 case CHIP_CEDAR:
866 radeon_program_register_sequence(rdev,
867 cedar_golden_registers,
868 (const u32)ARRAY_SIZE(cedar_golden_registers));
869 radeon_program_register_sequence(rdev,
870 evergreen_golden_registers2,
871 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
872 radeon_program_register_sequence(rdev,
873 cedar_mgcg_init,
874 (const u32)ARRAY_SIZE(cedar_mgcg_init));
875 break;
876 case CHIP_PALM:
877 radeon_program_register_sequence(rdev,
878 wrestler_golden_registers,
879 (const u32)ARRAY_SIZE(wrestler_golden_registers));
880 break;
881 case CHIP_SUMO:
882 radeon_program_register_sequence(rdev,
883 supersumo_golden_registers,
884 (const u32)ARRAY_SIZE(supersumo_golden_registers));
885 break;
886 case CHIP_SUMO2:
887 radeon_program_register_sequence(rdev,
888 supersumo_golden_registers,
889 (const u32)ARRAY_SIZE(supersumo_golden_registers));
890 radeon_program_register_sequence(rdev,
891 sumo_golden_registers,
892 (const u32)ARRAY_SIZE(sumo_golden_registers));
893 break;
894 case CHIP_BARTS:
895 radeon_program_register_sequence(rdev,
896 barts_golden_registers,
897 (const u32)ARRAY_SIZE(barts_golden_registers));
898 break;
899 case CHIP_TURKS:
900 radeon_program_register_sequence(rdev,
901 turks_golden_registers,
902 (const u32)ARRAY_SIZE(turks_golden_registers));
903 break;
904 case CHIP_CAICOS:
905 radeon_program_register_sequence(rdev,
906 caicos_golden_registers,
907 (const u32)ARRAY_SIZE(caicos_golden_registers));
908 break;
909 default:
910 break;
911 }
912}
913
56void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 914void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
57 unsigned *bankh, unsigned *mtaspect, 915 unsigned *bankh, unsigned *mtaspect,
58 unsigned *tile_split) 916 unsigned *tile_split)
@@ -84,6 +942,142 @@ void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
84 } 942 }
85} 943}
86 944
945static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,
946 u32 cntl_reg, u32 status_reg)
947{
948 int r, i;
949 struct atom_clock_dividers dividers;
950
951 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
952 clock, false, &dividers);
953 if (r)
954 return r;
955
956 WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));
957
958 for (i = 0; i < 100; i++) {
959 if (RREG32(status_reg) & DCLK_STATUS)
960 break;
961 mdelay(10);
962 }
963 if (i == 100)
964 return -ETIMEDOUT;
965
966 return 0;
967}
968
969int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
970{
971 int r = 0;
972 u32 cg_scratch = RREG32(CG_SCRATCH1);
973
974 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
975 if (r)
976 goto done;
977 cg_scratch &= 0xffff0000;
978 cg_scratch |= vclk / 100; /* Mhz */
979
980 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
981 if (r)
982 goto done;
983 cg_scratch &= 0x0000ffff;
984 cg_scratch |= (dclk / 100) << 16; /* Mhz */
985
986done:
987 WREG32(CG_SCRATCH1, cg_scratch);
988
989 return r;
990}
991
992int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
993{
994 /* start off with something large */
995 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
996 int r;
997
998 /* bypass vclk and dclk with bclk */
999 WREG32_P(CG_UPLL_FUNC_CNTL_2,
1000 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
1001 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
1002
1003 /* put PLL in bypass mode */
1004 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
1005
1006 if (!vclk || !dclk) {
1007 /* keep the Bypass mode, put PLL to sleep */
1008 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
1009 return 0;
1010 }
1011
1012 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
1013 16384, 0x03FFFFFF, 0, 128, 5,
1014 &fb_div, &vclk_div, &dclk_div);
1015 if (r)
1016 return r;
1017
1018 /* set VCO_MODE to 1 */
1019 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
1020
1021 /* toggle UPLL_SLEEP to 1 then back to 0 */
1022 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
1023 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
1024
1025 /* deassert UPLL_RESET */
1026 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
1027
1028 mdelay(1);
1029
1030 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
1031 if (r)
1032 return r;
1033
1034 /* assert UPLL_RESET again */
1035 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
1036
1037 /* disable spread spectrum. */
1038 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
1039
1040 /* set feedback divider */
1041 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
1042
1043 /* set ref divider to 0 */
1044 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
1045
1046 if (fb_div < 307200)
1047 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
1048 else
1049 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
1050
1051 /* set PDIV_A and PDIV_B */
1052 WREG32_P(CG_UPLL_FUNC_CNTL_2,
1053 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
1054 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
1055
1056 /* give the PLL some time to settle */
1057 mdelay(15);
1058
1059 /* deassert PLL_RESET */
1060 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
1061
1062 mdelay(15);
1063
1064 /* switch from bypass mode to normal mode */
1065 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
1066
1067 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
1068 if (r)
1069 return r;
1070
1071 /* switch VCLK and DCLK selection */
1072 WREG32_P(CG_UPLL_FUNC_CNTL_2,
1073 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
1074 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
1075
1076 mdelay(100);
1077
1078 return 0;
1079}
1080
87void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) 1081void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
88{ 1082{
89 u16 ctl, v; 1083 u16 ctl, v;
@@ -105,6 +1099,27 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
105 } 1099 }
106} 1100}
107 1101
1102static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
1103{
1104 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
1105 return true;
1106 else
1107 return false;
1108}
1109
1110static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
1111{
1112 u32 pos1, pos2;
1113
1114 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
1115 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
1116
1117 if (pos1 != pos2)
1118 return true;
1119 else
1120 return false;
1121}
1122
108/** 1123/**
109 * dce4_wait_for_vblank - vblank wait asic callback. 1124 * dce4_wait_for_vblank - vblank wait asic callback.
110 * 1125 *
@@ -115,21 +1130,28 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
115 */ 1130 */
116void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) 1131void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
117{ 1132{
118 int i; 1133 unsigned i = 0;
119 1134
120 if (crtc >= rdev->num_crtc) 1135 if (crtc >= rdev->num_crtc)
121 return; 1136 return;
122 1137
123 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) { 1138 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
124 for (i = 0; i < rdev->usec_timeout; i++) { 1139 return;
125 if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)) 1140
1141 /* depending on when we hit vblank, we may be close to active; if so,
1142 * wait for another frame.
1143 */
1144 while (dce4_is_in_vblank(rdev, crtc)) {
1145 if (i++ % 100 == 0) {
1146 if (!dce4_is_counter_moving(rdev, crtc))
126 break; 1147 break;
127 udelay(1);
128 } 1148 }
129 for (i = 0; i < rdev->usec_timeout; i++) { 1149 }
130 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) 1150
1151 while (!dce4_is_in_vblank(rdev, crtc)) {
1152 if (i++ % 100 == 0) {
1153 if (!dce4_is_counter_moving(rdev, crtc))
131 break; 1154 break;
132 udelay(1);
133 } 1155 }
134 } 1156 }
135} 1157}
@@ -608,6 +1630,16 @@ void evergreen_hpd_init(struct radeon_device *rdev)
608 1630
609 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1631 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
610 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1632 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1633
1634 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
1635 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
1636 /* don't try to enable hpd on eDP or LVDS avoid breaking the
1637 * aux dp channel on imac and help (but not completely fix)
1638 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
1639 * also avoid interrupt storms during dpms.
1640 */
1641 continue;
1642 }
611 switch (radeon_connector->hpd.hpd) { 1643 switch (radeon_connector->hpd.hpd) {
612 case RADEON_HPD_1: 1644 case RADEON_HPD_1:
613 WREG32(DC_HPD1_CONTROL, tmp); 1645 WREG32(DC_HPD1_CONTROL, tmp);
@@ -1325,17 +2357,16 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
1325 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); 2357 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1326 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { 2358 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1327 radeon_wait_for_vblank(rdev, i); 2359 radeon_wait_for_vblank(rdev, i);
1328 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1329 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 2360 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2361 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1330 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 2362 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1331 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1332 } 2363 }
1333 } else { 2364 } else {
1334 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); 2365 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1335 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) { 2366 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1336 radeon_wait_for_vblank(rdev, i); 2367 radeon_wait_for_vblank(rdev, i);
1337 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1338 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 2368 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2369 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1339 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); 2370 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1340 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 2371 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1341 } 2372 }
@@ -1347,6 +2378,15 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
1347 break; 2378 break;
1348 udelay(1); 2379 udelay(1);
1349 } 2380 }
2381
2382 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
2383 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2384 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2385 tmp &= ~EVERGREEN_CRTC_MASTER_EN;
2386 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
2387 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2388 save->crtc_enabled[i] = false;
2389 /* ***** */
1350 } else { 2390 } else {
1351 save->crtc_enabled[i] = false; 2391 save->crtc_enabled[i] = false;
1352 } 2392 }
@@ -1364,6 +2404,22 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
1364 } 2404 }
1365 /* wait for the MC to settle */ 2405 /* wait for the MC to settle */
1366 udelay(100); 2406 udelay(100);
2407
2408 /* lock double buffered regs */
2409 for (i = 0; i < rdev->num_crtc; i++) {
2410 if (save->crtc_enabled[i]) {
2411 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2412 if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
2413 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
2414 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
2415 }
2416 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
2417 if (!(tmp & 1)) {
2418 tmp |= 1;
2419 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
2420 }
2421 }
2422 }
1367} 2423}
1368 2424
1369void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 2425void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -1385,6 +2441,33 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1385 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); 2441 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1386 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 2442 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1387 2443
2444 /* unlock regs and wait for update */
2445 for (i = 0; i < rdev->num_crtc; i++) {
2446 if (save->crtc_enabled[i]) {
2447 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
2448 if ((tmp & 0x3) != 0) {
2449 tmp &= ~0x3;
2450 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
2451 }
2452 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2453 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
2454 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
2455 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
2456 }
2457 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
2458 if (tmp & 1) {
2459 tmp &= ~1;
2460 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
2461 }
2462 for (j = 0; j < rdev->usec_timeout; j++) {
2463 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2464 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
2465 break;
2466 udelay(1);
2467 }
2468 }
2469 }
2470
1388 /* unblackout the MC */ 2471 /* unblackout the MC */
1389 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); 2472 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1390 tmp &= ~BLACKOUT_MODE_MASK; 2473 tmp &= ~BLACKOUT_MODE_MASK;
@@ -2050,6 +3133,14 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2050 } 3133 }
2051 /* enabled rb are just the one not disabled :) */ 3134 /* enabled rb are just the one not disabled :) */
2052 disabled_rb_mask = tmp; 3135 disabled_rb_mask = tmp;
3136 tmp = 0;
3137 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
3138 tmp |= (1 << i);
3139 /* if all the backends are disabled, fix it up here */
3140 if ((disabled_rb_mask & tmp) == tmp) {
3141 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
3142 disabled_rb_mask &= ~(1 << i);
3143 }
2053 3144
2054 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 3145 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2055 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 3146 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
@@ -2058,6 +3149,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2058 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 3149 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2059 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 3150 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2060 WREG32(DMA_TILING_CONFIG, gb_addr_config); 3151 WREG32(DMA_TILING_CONFIG, gb_addr_config);
3152 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3153 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3154 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2061 3155
2062 if ((rdev->config.evergreen.max_backends == 1) && 3156 if ((rdev->config.evergreen.max_backends == 1) &&
2063 (rdev->flags & RADEON_IS_IGP)) { 3157 (rdev->flags & RADEON_IS_IGP)) {
@@ -3360,6 +4454,9 @@ restart_ih:
3360 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4454 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3361 break; 4455 break;
3362 } 4456 }
4457 case 124: /* UVD */
4458 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4459 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
3363 break; 4460 break;
3364 case 146: 4461 case 146:
3365 case 147: 4462 case 147:
@@ -3571,7 +4668,7 @@ int evergreen_copy_dma(struct radeon_device *rdev,
3571 4668
3572static int evergreen_startup(struct radeon_device *rdev) 4669static int evergreen_startup(struct radeon_device *rdev)
3573{ 4670{
3574 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4671 struct radeon_ring *ring;
3575 int r; 4672 int r;
3576 4673
3577 /* enable pcie gen2 link */ 4674 /* enable pcie gen2 link */
@@ -3638,6 +4735,17 @@ static int evergreen_startup(struct radeon_device *rdev)
3638 return r; 4735 return r;
3639 } 4736 }
3640 4737
4738 r = rv770_uvd_resume(rdev);
4739 if (!r) {
4740 r = radeon_fence_driver_start_ring(rdev,
4741 R600_RING_TYPE_UVD_INDEX);
4742 if (r)
4743 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
4744 }
4745
4746 if (r)
4747 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
4748
3641 /* Enable IRQ */ 4749 /* Enable IRQ */
3642 r = r600_irq_init(rdev); 4750 r = r600_irq_init(rdev);
3643 if (r) { 4751 if (r) {
@@ -3647,6 +4755,7 @@ static int evergreen_startup(struct radeon_device *rdev)
3647 } 4755 }
3648 evergreen_irq_set(rdev); 4756 evergreen_irq_set(rdev);
3649 4757
4758 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3650 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 4759 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3651 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 4760 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3652 0, 0xfffff, RADEON_CP_PACKET2); 4761 0, 0xfffff, RADEON_CP_PACKET2);
@@ -3670,6 +4779,19 @@ static int evergreen_startup(struct radeon_device *rdev)
3670 if (r) 4779 if (r)
3671 return r; 4780 return r;
3672 4781
4782 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4783 if (ring->ring_size) {
4784 r = radeon_ring_init(rdev, ring, ring->ring_size,
4785 R600_WB_UVD_RPTR_OFFSET,
4786 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
4787 0, 0xfffff, RADEON_CP_PACKET2);
4788 if (!r)
4789 r = r600_uvd_init(rdev);
4790
4791 if (r)
4792 DRM_ERROR("radeon: error initializing UVD (%d).\n", r);
4793 }
4794
3673 r = radeon_ib_pool_init(rdev); 4795 r = radeon_ib_pool_init(rdev);
3674 if (r) { 4796 if (r) {
3675 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 4797 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -3701,6 +4823,9 @@ int evergreen_resume(struct radeon_device *rdev)
3701 /* post card */ 4823 /* post card */
3702 atom_asic_init(rdev->mode_info.atom_context); 4824 atom_asic_init(rdev->mode_info.atom_context);
3703 4825
4826 /* init golden registers */
4827 evergreen_init_golden_registers(rdev);
4828
3704 rdev->accel_working = true; 4829 rdev->accel_working = true;
3705 r = evergreen_startup(rdev); 4830 r = evergreen_startup(rdev);
3706 if (r) { 4831 if (r) {
@@ -3716,8 +4841,10 @@ int evergreen_resume(struct radeon_device *rdev)
3716int evergreen_suspend(struct radeon_device *rdev) 4841int evergreen_suspend(struct radeon_device *rdev)
3717{ 4842{
3718 r600_audio_fini(rdev); 4843 r600_audio_fini(rdev);
4844 radeon_uvd_suspend(rdev);
3719 r700_cp_stop(rdev); 4845 r700_cp_stop(rdev);
3720 r600_dma_stop(rdev); 4846 r600_dma_stop(rdev);
4847 r600_uvd_rbc_stop(rdev);
3721 evergreen_irq_suspend(rdev); 4848 evergreen_irq_suspend(rdev);
3722 radeon_wb_disable(rdev); 4849 radeon_wb_disable(rdev);
3723 evergreen_pcie_gart_disable(rdev); 4850 evergreen_pcie_gart_disable(rdev);
@@ -3762,6 +4889,8 @@ int evergreen_init(struct radeon_device *rdev)
3762 DRM_INFO("GPU not posted. posting now...\n"); 4889 DRM_INFO("GPU not posted. posting now...\n");
3763 atom_asic_init(rdev->mode_info.atom_context); 4890 atom_asic_init(rdev->mode_info.atom_context);
3764 } 4891 }
4892 /* init golden registers */
4893 evergreen_init_golden_registers(rdev);
3765 /* Initialize scratch registers */ 4894 /* Initialize scratch registers */
3766 r600_scratch_init(rdev); 4895 r600_scratch_init(rdev);
3767 /* Initialize surface registers */ 4896 /* Initialize surface registers */
@@ -3797,6 +4926,13 @@ int evergreen_init(struct radeon_device *rdev)
3797 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 4926 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3798 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 4927 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3799 4928
4929 r = radeon_uvd_init(rdev);
4930 if (!r) {
4931 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
4932 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
4933 4096);
4934 }
4935
3800 rdev->ih.ring_obj = NULL; 4936 rdev->ih.ring_obj = NULL;
3801 r600_ih_ring_init(rdev, 64 * 1024); 4937 r600_ih_ring_init(rdev, 64 * 1024);
3802 4938
@@ -3843,6 +4979,7 @@ void evergreen_fini(struct radeon_device *rdev)
3843 radeon_ib_pool_fini(rdev); 4979 radeon_ib_pool_fini(rdev);
3844 radeon_irq_kms_fini(rdev); 4980 radeon_irq_kms_fini(rdev);
3845 evergreen_pcie_gart_fini(rdev); 4981 evergreen_pcie_gart_fini(rdev);
4982 radeon_uvd_fini(rdev);
3846 r600_vram_scratch_fini(rdev); 4983 r600_vram_scratch_fini(rdev);
3847 radeon_gem_fini(rdev); 4984 radeon_gem_fini(rdev);
3848 radeon_fence_driver_fini(rdev); 4985 radeon_fence_driver_fini(rdev);
@@ -3878,7 +5015,7 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3878 if (!(mask & DRM_PCIE_SPEED_50)) 5015 if (!(mask & DRM_PCIE_SPEED_50))
3879 return; 5016 return;
3880 5017
3881 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 5018 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3882 if (speed_cntl & LC_CURRENT_DATA_RATE) { 5019 if (speed_cntl & LC_CURRENT_DATA_RATE) {
3883 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 5020 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3884 return; 5021 return;
@@ -3889,33 +5026,33 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3889 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || 5026 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3890 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 5027 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3891 5028
3892 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 5029 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
3893 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 5030 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3894 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 5031 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3895 5032
3896 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 5033 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3897 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 5034 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3898 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 5035 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3899 5036
3900 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 5037 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3901 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 5038 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3902 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 5039 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3903 5040
3904 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 5041 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3905 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 5042 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3906 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 5043 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3907 5044
3908 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 5045 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3909 speed_cntl |= LC_GEN2_EN_STRAP; 5046 speed_cntl |= LC_GEN2_EN_STRAP;
3910 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 5047 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
3911 5048
3912 } else { 5049 } else {
3913 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 5050 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
3914 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 5051 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3915 if (1) 5052 if (1)
3916 link_width_cntl |= LC_UPCONFIGURE_DIS; 5053 link_width_cntl |= LC_UPCONFIGURE_DIS;
3917 else 5054 else
3918 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 5055 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3919 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 5056 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3920 } 5057 }
3921} 5058}
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 4fdecc2b4040..b4ab8ceb1654 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -54,6 +54,68 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t cloc
54 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); 54 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
55} 55}
56 56
57static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
58{
59 struct radeon_device *rdev = encoder->dev->dev_private;
60 struct drm_connector *connector;
61 struct radeon_connector *radeon_connector = NULL;
62 struct cea_sad *sads;
63 int i, sad_count;
64
65 static const u16 eld_reg_to_type[][2] = {
66 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
67 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
68 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
69 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
70 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
71 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
72 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
73 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
74 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
75 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
76 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
77 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
78 };
79
80 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
81 if (connector->encoder == encoder)
82 radeon_connector = to_radeon_connector(connector);
83 }
84
85 if (!radeon_connector) {
86 DRM_ERROR("Couldn't find encoder's connector\n");
87 return;
88 }
89
90 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
91 if (sad_count < 0) {
92 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
93 return;
94 }
95 BUG_ON(!sads);
96
97 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
98 u32 value = 0;
99 int j;
100
101 for (j = 0; j < sad_count; j++) {
102 struct cea_sad *sad = &sads[j];
103
104 if (sad->format == eld_reg_to_type[i][1]) {
105 value = MAX_CHANNELS(sad->channels) |
106 DESCRIPTOR_BYTE_2(sad->byte2) |
107 SUPPORTED_FREQUENCIES(sad->freq);
108 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
109 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
110 break;
111 }
112 }
113 WREG32(eld_reg_to_type[i][0], value);
114 }
115
116 kfree(sads);
117}
118
57/* 119/*
58 * build a HDMI Video Info Frame 120 * build a HDMI Video Info Frame
59 */ 121 */
@@ -85,6 +147,30 @@ static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
85 frame[0xC] | (frame[0xD] << 8)); 147 frame[0xC] | (frame[0xD] << 8));
86} 148}
87 149
150static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
151{
152 struct drm_device *dev = encoder->dev;
153 struct radeon_device *rdev = dev->dev_private;
154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
155 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
157 u32 base_rate = 48000;
158
159 if (!dig || !dig->afmt)
160 return;
161
162 /* XXX: properly calculate this */
163 /* XXX two dtos; generally use dto0 for hdmi */
164 /* Express [24MHz / target pixel clock] as an exact rational
165 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
166 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
167 */
168 WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);
169 WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);
170 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
171}
172
173
88/* 174/*
89 * update the info frames with the data from the current display mode 175 * update the info frames with the data from the current display mode
90 */ 176 */
@@ -104,33 +190,19 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
104 return; 190 return;
105 offset = dig->afmt->offset; 191 offset = dig->afmt->offset;
106 192
107 r600_audio_set_clock(encoder, mode->clock); 193 evergreen_audio_set_dto(encoder, mode->clock);
108 194
109 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 195 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
110 HDMI_NULL_SEND); /* send null packets when required */ 196 HDMI_NULL_SEND); /* send null packets when required */
111 197
112 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 198 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
113 199
114 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
115 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
116 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
117
118 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
119 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
120 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
121
122 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
123 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
124 HDMI_ACR_SOURCE); /* select SW CTS value */
125
126 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 200 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
127 HDMI_NULL_SEND | /* send null packets when required */ 201 HDMI_NULL_SEND | /* send null packets when required */
128 HDMI_GC_SEND | /* send general control packets */ 202 HDMI_GC_SEND | /* send general control packets */
129 HDMI_GC_CONT); /* send general control packets every frame */ 203 HDMI_GC_CONT); /* send general control packets every frame */
130 204
131 WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 205 WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
132 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
133 HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */
134 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 206 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
135 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ 207 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
136 208
@@ -138,11 +210,47 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
138 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 210 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
139 211
140 WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 212 WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
141 HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */
142 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 213 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
143 214
144 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 215 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
145 216
217 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
218 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
219 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
220
221 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
222 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
223
224 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
225
226 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
227 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
228 HDMI_ACR_SOURCE); /* select SW CTS value */
229
230 evergreen_hdmi_update_ACR(encoder, mode->clock);
231
232 WREG32(AFMT_60958_0 + offset,
233 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
234
235 WREG32(AFMT_60958_1 + offset,
236 AFMT_60958_CS_CHANNEL_NUMBER_R(2));
237
238 WREG32(AFMT_60958_2 + offset,
239 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
240 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
241 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
242 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
243 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
244 AFMT_60958_CS_CHANNEL_NUMBER_7(8));
245
246 /* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */
247
248 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
249 AFMT_AUDIO_CHANNEL_ENABLE(0xff));
250
251 /* fglrx sets 0x40 in 0x5f80 here */
252 evergreen_hdmi_write_sad_regs(encoder);
253
146 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 254 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
147 if (err < 0) { 255 if (err < 0) {
148 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 256 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
@@ -156,7 +264,17 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
156 } 264 }
157 265
158 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 266 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
159 evergreen_hdmi_update_ACR(encoder, mode->clock); 267
268 WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
269 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
270 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
271
272 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
273 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
274 ~HDMI_AVI_INFO_LINE_MASK);
275
276 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
277 AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
160 278
161 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 279 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
162 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 280 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
@@ -164,3 +282,20 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
164 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 282 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
165 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 283 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
166} 284}
285
286void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
287{
288 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
289 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
290
291 /* Silent, r600_hdmi_enable will raise WARN for us */
292 if (enable && dig->afmt->enabled)
293 return;
294 if (!enable && !dig->afmt->enabled)
295 return;
296
297 dig->afmt->enabled = enable;
298
299 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
300 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
301}
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index f585be16e2d5..881aba23c477 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -226,6 +226,8 @@
226#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x6ea0 226#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x6ea0
227#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8 227#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
228#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 228#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4
229#define EVERGREEN_MASTER_UPDATE_LOCK 0x6ef4
230#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
229 231
230#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 232#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0
231#define EVERGREEN_DC_GPIO_HPD_A 0x64b4 233#define EVERGREEN_DC_GPIO_HPD_A 0x64b4
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 982d25ad9af3..75c05631146d 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -53,6 +53,43 @@
53#define RCU_IND_INDEX 0x100 53#define RCU_IND_INDEX 0x100
54#define RCU_IND_DATA 0x104 54#define RCU_IND_DATA 0x104
55 55
56/* discrete uvd clocks */
57#define CG_UPLL_FUNC_CNTL 0x718
58# define UPLL_RESET_MASK 0x00000001
59# define UPLL_SLEEP_MASK 0x00000002
60# define UPLL_BYPASS_EN_MASK 0x00000004
61# define UPLL_CTLREQ_MASK 0x00000008
62# define UPLL_REF_DIV_MASK 0x003F0000
63# define UPLL_VCO_MODE_MASK 0x00000200
64# define UPLL_CTLACK_MASK 0x40000000
65# define UPLL_CTLACK2_MASK 0x80000000
66#define CG_UPLL_FUNC_CNTL_2 0x71c
67# define UPLL_PDIV_A(x) ((x) << 0)
68# define UPLL_PDIV_A_MASK 0x0000007F
69# define UPLL_PDIV_B(x) ((x) << 8)
70# define UPLL_PDIV_B_MASK 0x00007F00
71# define VCLK_SRC_SEL(x) ((x) << 20)
72# define VCLK_SRC_SEL_MASK 0x01F00000
73# define DCLK_SRC_SEL(x) ((x) << 25)
74# define DCLK_SRC_SEL_MASK 0x3E000000
75#define CG_UPLL_FUNC_CNTL_3 0x720
76# define UPLL_FB_DIV(x) ((x) << 0)
77# define UPLL_FB_DIV_MASK 0x01FFFFFF
78#define CG_UPLL_FUNC_CNTL_4 0x854
79# define UPLL_SPARE_ISPARE9 0x00020000
80#define CG_UPLL_SPREAD_SPECTRUM 0x79c
81# define SSEN_MASK 0x00000001
82
83/* fusion uvd clocks */
84#define CG_DCLK_CNTL 0x610
85# define DCLK_DIVIDER_MASK 0x7f
86# define DCLK_DIR_CNTL_EN (1 << 8)
87#define CG_DCLK_STATUS 0x614
88# define DCLK_STATUS (1 << 0)
89#define CG_VCLK_CNTL 0x618
90#define CG_VCLK_STATUS 0x61c
91#define CG_SCRATCH1 0x820
92
56#define GRBM_GFX_INDEX 0x802C 93#define GRBM_GFX_INDEX 0x802C
57#define INSTANCE_INDEX(x) ((x) << 0) 94#define INSTANCE_INDEX(x) ((x) << 0)
58#define SE_INDEX(x) ((x) << 16) 95#define SE_INDEX(x) ((x) << 16)
@@ -197,6 +234,7 @@
197# define HDMI_MPEG_INFO_CONT (1 << 9) 234# define HDMI_MPEG_INFO_CONT (1 << 9)
198#define HDMI_INFOFRAME_CONTROL1 0x7048 235#define HDMI_INFOFRAME_CONTROL1 0x7048
199# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 236# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
237# define HDMI_AVI_INFO_LINE_MASK (0x3f << 0)
200# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 238# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
201# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 239# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
202#define HDMI_GENERIC_PACKET_CONTROL 0x704c 240#define HDMI_GENERIC_PACKET_CONTROL 0x704c
@@ -992,6 +1030,16 @@
992# define TARGET_LINK_SPEED_MASK (0xf << 0) 1030# define TARGET_LINK_SPEED_MASK (0xf << 0)
993# define SELECTABLE_DEEMPHASIS (1 << 6) 1031# define SELECTABLE_DEEMPHASIS (1 << 6)
994 1032
1033
1034/*
1035 * UVD
1036 */
1037#define UVD_UDEC_ADDR_CONFIG 0xef4c
1038#define UVD_UDEC_DB_ADDR_CONFIG 0xef50
1039#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
1040#define UVD_RBC_RB_RPTR 0xf690
1041#define UVD_RBC_RB_WPTR 0xf694
1042
995/* 1043/*
996 * PM4 1044 * PM4
997 */ 1045 */
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 27769e724b6d..7969c0c8ec20 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -78,6 +78,282 @@ MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
78MODULE_FIRMWARE("radeon/ARUBA_me.bin"); 78MODULE_FIRMWARE("radeon/ARUBA_me.bin");
79MODULE_FIRMWARE("radeon/ARUBA_rlc.bin"); 79MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
80 80
81
82static const u32 cayman_golden_registers2[] =
83{
84 0x3e5c, 0xffffffff, 0x00000000,
85 0x3e48, 0xffffffff, 0x00000000,
86 0x3e4c, 0xffffffff, 0x00000000,
87 0x3e64, 0xffffffff, 0x00000000,
88 0x3e50, 0xffffffff, 0x00000000,
89 0x3e60, 0xffffffff, 0x00000000
90};
91
92static const u32 cayman_golden_registers[] =
93{
94 0x5eb4, 0xffffffff, 0x00000002,
95 0x5e78, 0x8f311ff1, 0x001000f0,
96 0x3f90, 0xffff0000, 0xff000000,
97 0x9148, 0xffff0000, 0xff000000,
98 0x3f94, 0xffff0000, 0xff000000,
99 0x914c, 0xffff0000, 0xff000000,
100 0xc78, 0x00000080, 0x00000080,
101 0xbd4, 0x70073777, 0x00011003,
102 0xd02c, 0xbfffff1f, 0x08421000,
103 0xd0b8, 0x73773777, 0x02011003,
104 0x5bc0, 0x00200000, 0x50100000,
105 0x98f8, 0x33773777, 0x02011003,
106 0x98fc, 0xffffffff, 0x76541032,
107 0x7030, 0x31000311, 0x00000011,
108 0x2f48, 0x33773777, 0x42010001,
109 0x6b28, 0x00000010, 0x00000012,
110 0x7728, 0x00000010, 0x00000012,
111 0x10328, 0x00000010, 0x00000012,
112 0x10f28, 0x00000010, 0x00000012,
113 0x11b28, 0x00000010, 0x00000012,
114 0x12728, 0x00000010, 0x00000012,
115 0x240c, 0x000007ff, 0x00000000,
116 0x8a14, 0xf000001f, 0x00000007,
117 0x8b24, 0x3fff3fff, 0x00ff0fff,
118 0x8b10, 0x0000ff0f, 0x00000000,
119 0x28a4c, 0x07ffffff, 0x06000000,
120 0x10c, 0x00000001, 0x00010003,
121 0xa02c, 0xffffffff, 0x0000009b,
122 0x913c, 0x0000010f, 0x01000100,
123 0x8c04, 0xf8ff00ff, 0x40600060,
124 0x28350, 0x00000f01, 0x00000000,
125 0x9508, 0x3700001f, 0x00000002,
126 0x960c, 0xffffffff, 0x54763210,
127 0x88c4, 0x001f3ae3, 0x00000082,
128 0x88d0, 0xffffffff, 0x0f40df40,
129 0x88d4, 0x0000001f, 0x00000010,
130 0x8974, 0xffffffff, 0x00000000
131};
132
133static const u32 dvst_golden_registers2[] =
134{
135 0x8f8, 0xffffffff, 0,
136 0x8fc, 0x00380000, 0,
137 0x8f8, 0xffffffff, 1,
138 0x8fc, 0x0e000000, 0
139};
140
141static const u32 dvst_golden_registers[] =
142{
143 0x690, 0x3fff3fff, 0x20c00033,
144 0x918c, 0x0fff0fff, 0x00010006,
145 0x91a8, 0x0fff0fff, 0x00010006,
146 0x9150, 0xffffdfff, 0x6e944040,
147 0x917c, 0x0fff0fff, 0x00030002,
148 0x9198, 0x0fff0fff, 0x00030002,
149 0x915c, 0x0fff0fff, 0x00010000,
150 0x3f90, 0xffff0001, 0xff000000,
151 0x9178, 0x0fff0fff, 0x00070000,
152 0x9194, 0x0fff0fff, 0x00070000,
153 0x9148, 0xffff0001, 0xff000000,
154 0x9190, 0x0fff0fff, 0x00090008,
155 0x91ac, 0x0fff0fff, 0x00090008,
156 0x3f94, 0xffff0000, 0xff000000,
157 0x914c, 0xffff0000, 0xff000000,
158 0x929c, 0x00000fff, 0x00000001,
159 0x55e4, 0xff607fff, 0xfc000100,
160 0x8a18, 0xff000fff, 0x00000100,
161 0x8b28, 0xff000fff, 0x00000100,
162 0x9144, 0xfffc0fff, 0x00000100,
163 0x6ed8, 0x00010101, 0x00010000,
164 0x9830, 0xffffffff, 0x00000000,
165 0x9834, 0xf00fffff, 0x00000400,
166 0x9838, 0xfffffffe, 0x00000000,
167 0xd0c0, 0xff000fff, 0x00000100,
168 0xd02c, 0xbfffff1f, 0x08421000,
169 0xd0b8, 0x73773777, 0x12010001,
170 0x5bb0, 0x000000f0, 0x00000070,
171 0x98f8, 0x73773777, 0x12010001,
172 0x98fc, 0xffffffff, 0x00000010,
173 0x9b7c, 0x00ff0000, 0x00fc0000,
174 0x8030, 0x00001f0f, 0x0000100a,
175 0x2f48, 0x73773777, 0x12010001,
176 0x2408, 0x00030000, 0x000c007f,
177 0x8a14, 0xf000003f, 0x00000007,
178 0x8b24, 0x3fff3fff, 0x00ff0fff,
179 0x8b10, 0x0000ff0f, 0x00000000,
180 0x28a4c, 0x07ffffff, 0x06000000,
181 0x4d8, 0x00000fff, 0x00000100,
182 0xa008, 0xffffffff, 0x00010000,
183 0x913c, 0xffff03ff, 0x01000100,
184 0x8c00, 0x000000ff, 0x00000003,
185 0x8c04, 0xf8ff00ff, 0x40600060,
186 0x8cf0, 0x1fff1fff, 0x08e00410,
187 0x28350, 0x00000f01, 0x00000000,
188 0x9508, 0xf700071f, 0x00000002,
189 0x960c, 0xffffffff, 0x54763210,
190 0x20ef8, 0x01ff01ff, 0x00000002,
191 0x20e98, 0xfffffbff, 0x00200000,
192 0x2015c, 0xffffffff, 0x00000f40,
193 0x88c4, 0x001f3ae3, 0x00000082,
194 0x8978, 0x3fffffff, 0x04050140,
195 0x88d4, 0x0000001f, 0x00000010,
196 0x8974, 0xffffffff, 0x00000000
197};
198
199static const u32 scrapper_golden_registers[] =
200{
201 0x690, 0x3fff3fff, 0x20c00033,
202 0x918c, 0x0fff0fff, 0x00010006,
203 0x918c, 0x0fff0fff, 0x00010006,
204 0x91a8, 0x0fff0fff, 0x00010006,
205 0x91a8, 0x0fff0fff, 0x00010006,
206 0x9150, 0xffffdfff, 0x6e944040,
207 0x9150, 0xffffdfff, 0x6e944040,
208 0x917c, 0x0fff0fff, 0x00030002,
209 0x917c, 0x0fff0fff, 0x00030002,
210 0x9198, 0x0fff0fff, 0x00030002,
211 0x9198, 0x0fff0fff, 0x00030002,
212 0x915c, 0x0fff0fff, 0x00010000,
213 0x915c, 0x0fff0fff, 0x00010000,
214 0x3f90, 0xffff0001, 0xff000000,
215 0x3f90, 0xffff0001, 0xff000000,
216 0x9178, 0x0fff0fff, 0x00070000,
217 0x9178, 0x0fff0fff, 0x00070000,
218 0x9194, 0x0fff0fff, 0x00070000,
219 0x9194, 0x0fff0fff, 0x00070000,
220 0x9148, 0xffff0001, 0xff000000,
221 0x9148, 0xffff0001, 0xff000000,
222 0x9190, 0x0fff0fff, 0x00090008,
223 0x9190, 0x0fff0fff, 0x00090008,
224 0x91ac, 0x0fff0fff, 0x00090008,
225 0x91ac, 0x0fff0fff, 0x00090008,
226 0x3f94, 0xffff0000, 0xff000000,
227 0x3f94, 0xffff0000, 0xff000000,
228 0x914c, 0xffff0000, 0xff000000,
229 0x914c, 0xffff0000, 0xff000000,
230 0x929c, 0x00000fff, 0x00000001,
231 0x929c, 0x00000fff, 0x00000001,
232 0x55e4, 0xff607fff, 0xfc000100,
233 0x8a18, 0xff000fff, 0x00000100,
234 0x8a18, 0xff000fff, 0x00000100,
235 0x8b28, 0xff000fff, 0x00000100,
236 0x8b28, 0xff000fff, 0x00000100,
237 0x9144, 0xfffc0fff, 0x00000100,
238 0x9144, 0xfffc0fff, 0x00000100,
239 0x6ed8, 0x00010101, 0x00010000,
240 0x9830, 0xffffffff, 0x00000000,
241 0x9830, 0xffffffff, 0x00000000,
242 0x9834, 0xf00fffff, 0x00000400,
243 0x9834, 0xf00fffff, 0x00000400,
244 0x9838, 0xfffffffe, 0x00000000,
245 0x9838, 0xfffffffe, 0x00000000,
246 0xd0c0, 0xff000fff, 0x00000100,
247 0xd02c, 0xbfffff1f, 0x08421000,
248 0xd02c, 0xbfffff1f, 0x08421000,
249 0xd0b8, 0x73773777, 0x12010001,
250 0xd0b8, 0x73773777, 0x12010001,
251 0x5bb0, 0x000000f0, 0x00000070,
252 0x98f8, 0x73773777, 0x12010001,
253 0x98f8, 0x73773777, 0x12010001,
254 0x98fc, 0xffffffff, 0x00000010,
255 0x98fc, 0xffffffff, 0x00000010,
256 0x9b7c, 0x00ff0000, 0x00fc0000,
257 0x9b7c, 0x00ff0000, 0x00fc0000,
258 0x8030, 0x00001f0f, 0x0000100a,
259 0x8030, 0x00001f0f, 0x0000100a,
260 0x2f48, 0x73773777, 0x12010001,
261 0x2f48, 0x73773777, 0x12010001,
262 0x2408, 0x00030000, 0x000c007f,
263 0x8a14, 0xf000003f, 0x00000007,
264 0x8a14, 0xf000003f, 0x00000007,
265 0x8b24, 0x3fff3fff, 0x00ff0fff,
266 0x8b24, 0x3fff3fff, 0x00ff0fff,
267 0x8b10, 0x0000ff0f, 0x00000000,
268 0x8b10, 0x0000ff0f, 0x00000000,
269 0x28a4c, 0x07ffffff, 0x06000000,
270 0x28a4c, 0x07ffffff, 0x06000000,
271 0x4d8, 0x00000fff, 0x00000100,
272 0x4d8, 0x00000fff, 0x00000100,
273 0xa008, 0xffffffff, 0x00010000,
274 0xa008, 0xffffffff, 0x00010000,
275 0x913c, 0xffff03ff, 0x01000100,
276 0x913c, 0xffff03ff, 0x01000100,
277 0x90e8, 0x001fffff, 0x010400c0,
278 0x8c00, 0x000000ff, 0x00000003,
279 0x8c00, 0x000000ff, 0x00000003,
280 0x8c04, 0xf8ff00ff, 0x40600060,
281 0x8c04, 0xf8ff00ff, 0x40600060,
282 0x8c30, 0x0000000f, 0x00040005,
283 0x8cf0, 0x1fff1fff, 0x08e00410,
284 0x8cf0, 0x1fff1fff, 0x08e00410,
285 0x900c, 0x00ffffff, 0x0017071f,
286 0x28350, 0x00000f01, 0x00000000,
287 0x28350, 0x00000f01, 0x00000000,
288 0x9508, 0xf700071f, 0x00000002,
289 0x9508, 0xf700071f, 0x00000002,
290 0x9688, 0x00300000, 0x0017000f,
291 0x960c, 0xffffffff, 0x54763210,
292 0x960c, 0xffffffff, 0x54763210,
293 0x20ef8, 0x01ff01ff, 0x00000002,
294 0x20e98, 0xfffffbff, 0x00200000,
295 0x2015c, 0xffffffff, 0x00000f40,
296 0x88c4, 0x001f3ae3, 0x00000082,
297 0x88c4, 0x001f3ae3, 0x00000082,
298 0x8978, 0x3fffffff, 0x04050140,
299 0x8978, 0x3fffffff, 0x04050140,
300 0x88d4, 0x0000001f, 0x00000010,
301 0x88d4, 0x0000001f, 0x00000010,
302 0x8974, 0xffffffff, 0x00000000,
303 0x8974, 0xffffffff, 0x00000000
304};
305
306static void ni_init_golden_registers(struct radeon_device *rdev)
307{
308 switch (rdev->family) {
309 case CHIP_CAYMAN:
310 radeon_program_register_sequence(rdev,
311 cayman_golden_registers,
312 (const u32)ARRAY_SIZE(cayman_golden_registers));
313 radeon_program_register_sequence(rdev,
314 cayman_golden_registers2,
315 (const u32)ARRAY_SIZE(cayman_golden_registers2));
316 break;
317 case CHIP_ARUBA:
318 if ((rdev->pdev->device == 0x9900) ||
319 (rdev->pdev->device == 0x9901) ||
320 (rdev->pdev->device == 0x9903) ||
321 (rdev->pdev->device == 0x9904) ||
322 (rdev->pdev->device == 0x9905) ||
323 (rdev->pdev->device == 0x9906) ||
324 (rdev->pdev->device == 0x9907) ||
325 (rdev->pdev->device == 0x9908) ||
326 (rdev->pdev->device == 0x9909) ||
327 (rdev->pdev->device == 0x990A) ||
328 (rdev->pdev->device == 0x990B) ||
329 (rdev->pdev->device == 0x990C) ||
330 (rdev->pdev->device == 0x990D) ||
331 (rdev->pdev->device == 0x990E) ||
332 (rdev->pdev->device == 0x990F) ||
333 (rdev->pdev->device == 0x9910) ||
334 (rdev->pdev->device == 0x9913) ||
335 (rdev->pdev->device == 0x9917) ||
336 (rdev->pdev->device == 0x9918)) {
337 radeon_program_register_sequence(rdev,
338 dvst_golden_registers,
339 (const u32)ARRAY_SIZE(dvst_golden_registers));
340 radeon_program_register_sequence(rdev,
341 dvst_golden_registers2,
342 (const u32)ARRAY_SIZE(dvst_golden_registers2));
343 } else {
344 radeon_program_register_sequence(rdev,
345 scrapper_golden_registers,
346 (const u32)ARRAY_SIZE(scrapper_golden_registers));
347 radeon_program_register_sequence(rdev,
348 dvst_golden_registers2,
349 (const u32)ARRAY_SIZE(dvst_golden_registers2));
350 }
351 break;
352 default:
353 break;
354 }
355}
356
81#define BTC_IO_MC_REGS_SIZE 29 357#define BTC_IO_MC_REGS_SIZE 29
82 358
83static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 359static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
@@ -473,7 +749,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
473 (rdev->pdev->device == 0x990F) || 749 (rdev->pdev->device == 0x990F) ||
474 (rdev->pdev->device == 0x9910) || 750 (rdev->pdev->device == 0x9910) ||
475 (rdev->pdev->device == 0x9917) || 751 (rdev->pdev->device == 0x9917) ||
476 (rdev->pdev->device == 0x9999)) { 752 (rdev->pdev->device == 0x9999) ||
753 (rdev->pdev->device == 0x999C)) {
477 rdev->config.cayman.max_simds_per_se = 6; 754 rdev->config.cayman.max_simds_per_se = 6;
478 rdev->config.cayman.max_backends_per_se = 2; 755 rdev->config.cayman.max_backends_per_se = 2;
479 } else if ((rdev->pdev->device == 0x9903) || 756 } else if ((rdev->pdev->device == 0x9903) ||
@@ -482,7 +759,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
482 (rdev->pdev->device == 0x990D) || 759 (rdev->pdev->device == 0x990D) ||
483 (rdev->pdev->device == 0x990E) || 760 (rdev->pdev->device == 0x990E) ||
484 (rdev->pdev->device == 0x9913) || 761 (rdev->pdev->device == 0x9913) ||
485 (rdev->pdev->device == 0x9918)) { 762 (rdev->pdev->device == 0x9918) ||
763 (rdev->pdev->device == 0x999D)) {
486 rdev->config.cayman.max_simds_per_se = 4; 764 rdev->config.cayman.max_simds_per_se = 4;
487 rdev->config.cayman.max_backends_per_se = 2; 765 rdev->config.cayman.max_backends_per_se = 2;
488 } else if ((rdev->pdev->device == 0x9919) || 766 } else if ((rdev->pdev->device == 0x9919) ||
@@ -615,15 +893,28 @@ static void cayman_gpu_init(struct radeon_device *rdev)
615 } 893 }
616 /* enabled rb are just the one not disabled :) */ 894 /* enabled rb are just the one not disabled :) */
617 disabled_rb_mask = tmp; 895 disabled_rb_mask = tmp;
896 tmp = 0;
897 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
898 tmp |= (1 << i);
899 /* if all the backends are disabled, fix it up here */
900 if ((disabled_rb_mask & tmp) == tmp) {
901 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
902 disabled_rb_mask &= ~(1 << i);
903 }
618 904
619 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 905 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
620 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 906 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
621 907
622 WREG32(GB_ADDR_CONFIG, gb_addr_config); 908 WREG32(GB_ADDR_CONFIG, gb_addr_config);
623 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 909 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
910 if (ASIC_IS_DCE6(rdev))
911 WREG32(DMIF_ADDR_CALC, gb_addr_config);
624 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 912 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
625 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 913 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
626 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 914 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
915 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
916 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
917 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
627 918
628 if ((rdev->config.cayman.max_backends_per_se == 1) && 919 if ((rdev->config.cayman.max_backends_per_se == 1) &&
629 (rdev->flags & RADEON_IS_IGP)) { 920 (rdev->flags & RADEON_IS_IGP)) {
@@ -931,6 +1222,23 @@ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
931 radeon_ring_write(ring, 10); /* poll interval */ 1222 radeon_ring_write(ring, 10); /* poll interval */
932} 1223}
933 1224
1225void cayman_uvd_semaphore_emit(struct radeon_device *rdev,
1226 struct radeon_ring *ring,
1227 struct radeon_semaphore *semaphore,
1228 bool emit_wait)
1229{
1230 uint64_t addr = semaphore->gpu_addr;
1231
1232 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
1233 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
1234
1235 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
1236 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
1237
1238 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
1239 radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));
1240}
1241
934static void cayman_cp_enable(struct radeon_device *rdev, bool enable) 1242static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
935{ 1243{
936 if (enable) 1244 if (enable)
@@ -1682,6 +1990,16 @@ static int cayman_startup(struct radeon_device *rdev)
1682 return r; 1990 return r;
1683 } 1991 }
1684 1992
1993 r = rv770_uvd_resume(rdev);
1994 if (!r) {
1995 r = radeon_fence_driver_start_ring(rdev,
1996 R600_RING_TYPE_UVD_INDEX);
1997 if (r)
1998 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1999 }
2000 if (r)
2001 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
2002
1685 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 2003 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1686 if (r) { 2004 if (r) {
1687 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2005 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
@@ -1748,6 +2066,18 @@ static int cayman_startup(struct radeon_device *rdev)
1748 if (r) 2066 if (r)
1749 return r; 2067 return r;
1750 2068
2069 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2070 if (ring->ring_size) {
2071 r = radeon_ring_init(rdev, ring, ring->ring_size,
2072 R600_WB_UVD_RPTR_OFFSET,
2073 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
2074 0, 0xfffff, RADEON_CP_PACKET2);
2075 if (!r)
2076 r = r600_uvd_init(rdev);
2077 if (r)
2078 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
2079 }
2080
1751 r = radeon_ib_pool_init(rdev); 2081 r = radeon_ib_pool_init(rdev);
1752 if (r) { 2082 if (r) {
1753 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2083 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -1778,6 +2108,9 @@ int cayman_resume(struct radeon_device *rdev)
1778 /* post card */ 2108 /* post card */
1779 atom_asic_init(rdev->mode_info.atom_context); 2109 atom_asic_init(rdev->mode_info.atom_context);
1780 2110
2111 /* init golden registers */
2112 ni_init_golden_registers(rdev);
2113
1781 rdev->accel_working = true; 2114 rdev->accel_working = true;
1782 r = cayman_startup(rdev); 2115 r = cayman_startup(rdev);
1783 if (r) { 2116 if (r) {
@@ -1794,6 +2127,8 @@ int cayman_suspend(struct radeon_device *rdev)
1794 radeon_vm_manager_fini(rdev); 2127 radeon_vm_manager_fini(rdev);
1795 cayman_cp_enable(rdev, false); 2128 cayman_cp_enable(rdev, false);
1796 cayman_dma_stop(rdev); 2129 cayman_dma_stop(rdev);
2130 r600_uvd_rbc_stop(rdev);
2131 radeon_uvd_suspend(rdev);
1797 evergreen_irq_suspend(rdev); 2132 evergreen_irq_suspend(rdev);
1798 radeon_wb_disable(rdev); 2133 radeon_wb_disable(rdev);
1799 cayman_pcie_gart_disable(rdev); 2134 cayman_pcie_gart_disable(rdev);
@@ -1834,6 +2169,8 @@ int cayman_init(struct radeon_device *rdev)
1834 DRM_INFO("GPU not posted. posting now...\n"); 2169 DRM_INFO("GPU not posted. posting now...\n");
1835 atom_asic_init(rdev->mode_info.atom_context); 2170 atom_asic_init(rdev->mode_info.atom_context);
1836 } 2171 }
2172 /* init golden registers */
2173 ni_init_golden_registers(rdev);
1837 /* Initialize scratch registers */ 2174 /* Initialize scratch registers */
1838 r600_scratch_init(rdev); 2175 r600_scratch_init(rdev);
1839 /* Initialize surface registers */ 2176 /* Initialize surface registers */
@@ -1868,6 +2205,13 @@ int cayman_init(struct radeon_device *rdev)
1868 ring->ring_obj = NULL; 2205 ring->ring_obj = NULL;
1869 r600_ring_init(rdev, ring, 64 * 1024); 2206 r600_ring_init(rdev, ring, 64 * 1024);
1870 2207
2208 r = radeon_uvd_init(rdev);
2209 if (!r) {
2210 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2211 ring->ring_obj = NULL;
2212 r600_ring_init(rdev, ring, 4096);
2213 }
2214
1871 rdev->ih.ring_obj = NULL; 2215 rdev->ih.ring_obj = NULL;
1872 r600_ih_ring_init(rdev, 64 * 1024); 2216 r600_ih_ring_init(rdev, 64 * 1024);
1873 2217
@@ -1919,6 +2263,7 @@ void cayman_fini(struct radeon_device *rdev)
1919 radeon_vm_manager_fini(rdev); 2263 radeon_vm_manager_fini(rdev);
1920 radeon_ib_pool_fini(rdev); 2264 radeon_ib_pool_fini(rdev);
1921 radeon_irq_kms_fini(rdev); 2265 radeon_irq_kms_fini(rdev);
2266 radeon_uvd_fini(rdev);
1922 cayman_pcie_gart_fini(rdev); 2267 cayman_pcie_gart_fini(rdev);
1923 r600_vram_scratch_fini(rdev); 2268 r600_vram_scratch_fini(rdev);
1924 radeon_gem_fini(rdev); 2269 radeon_gem_fini(rdev);
@@ -2017,28 +2362,57 @@ void cayman_vm_set_page(struct radeon_device *rdev,
2017 } 2362 }
2018 } 2363 }
2019 } else { 2364 } else {
2020 while (count) { 2365 if ((flags & RADEON_VM_PAGE_SYSTEM) ||
2021 ndw = count * 2; 2366 (count == 1)) {
2022 if (ndw > 0xFFFFE) 2367 while (count) {
2023 ndw = 0xFFFFE; 2368 ndw = count * 2;
2369 if (ndw > 0xFFFFE)
2370 ndw = 0xFFFFE;
2371
2372 /* for non-physically contiguous pages (system) */
2373 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
2374 ib->ptr[ib->length_dw++] = pe;
2375 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2376 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
2377 if (flags & RADEON_VM_PAGE_SYSTEM) {
2378 value = radeon_vm_map_gart(rdev, addr);
2379 value &= 0xFFFFFFFFFFFFF000ULL;
2380 } else if (flags & RADEON_VM_PAGE_VALID) {
2381 value = addr;
2382 } else {
2383 value = 0;
2384 }
2385 addr += incr;
2386 value |= r600_flags;
2387 ib->ptr[ib->length_dw++] = value;
2388 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2389 }
2390 }
2391 while (ib->length_dw & 0x7)
2392 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
2393 } else {
2394 while (count) {
2395 ndw = count * 2;
2396 if (ndw > 0xFFFFE)
2397 ndw = 0xFFFFE;
2024 2398
2025 /* for non-physically contiguous pages (system) */ 2399 if (flags & RADEON_VM_PAGE_VALID)
2026 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
2027 ib->ptr[ib->length_dw++] = pe;
2028 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2029 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
2030 if (flags & RADEON_VM_PAGE_SYSTEM) {
2031 value = radeon_vm_map_gart(rdev, addr);
2032 value &= 0xFFFFFFFFFFFFF000ULL;
2033 } else if (flags & RADEON_VM_PAGE_VALID) {
2034 value = addr; 2400 value = addr;
2035 } else { 2401 else
2036 value = 0; 2402 value = 0;
2037 } 2403 /* for physically contiguous pages (vram) */
2038 addr += incr; 2404 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
2039 value |= r600_flags; 2405 ib->ptr[ib->length_dw++] = pe; /* dst addr */
2040 ib->ptr[ib->length_dw++] = value; 2406 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2407 ib->ptr[ib->length_dw++] = r600_flags; /* mask */
2408 ib->ptr[ib->length_dw++] = 0;
2409 ib->ptr[ib->length_dw++] = value; /* value */
2041 ib->ptr[ib->length_dw++] = upper_32_bits(value); 2410 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2411 ib->ptr[ib->length_dw++] = incr; /* increment size */
2412 ib->ptr[ib->length_dw++] = 0;
2413 pe += ndw * 4;
2414 addr += (ndw / 2) * incr;
2415 count -= ndw / 2;
2042 } 2416 }
2043 } 2417 }
2044 while (ib->length_dw & 0x7) 2418 while (ib->length_dw & 0x7)
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 079dee202a9e..e226faf16fea 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -45,6 +45,10 @@
45#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 45#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
46 46
47#define DMIF_ADDR_CONFIG 0xBD4 47#define DMIF_ADDR_CONFIG 0xBD4
48
49/* DCE6 only */
50#define DMIF_ADDR_CALC 0xC00
51
48#define SRBM_GFX_CNTL 0x0E44 52#define SRBM_GFX_CNTL 0x0E44
49#define RINGID(x) (((x) & 0x3) << 0) 53#define RINGID(x) (((x) & 0x3) << 0)
50#define VMID(x) (((x) & 0x7) << 0) 54#define VMID(x) (((x) & 0x7) << 0)
@@ -486,6 +490,18 @@
486# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 490# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
487 491
488/* 492/*
493 * UVD
494 */
495#define UVD_SEMA_ADDR_LOW 0xEF00
496#define UVD_SEMA_ADDR_HIGH 0xEF04
497#define UVD_SEMA_CMD 0xEF08
498#define UVD_UDEC_ADDR_CONFIG 0xEF4C
499#define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
500#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
501#define UVD_RBC_RB_RPTR 0xF690
502#define UVD_RBC_RB_WPTR 0xF694
503
504/*
489 * PM4 505 * PM4
490 */ 506 */
491#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 507#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
@@ -668,6 +684,11 @@
668 (((vmid) & 0xF) << 20) | \ 684 (((vmid) & 0xF) << 20) | \
669 (((n) & 0xFFFFF) << 0)) 685 (((n) & 0xFFFFF) << 0))
670 686
687#define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
688 (1 << 26) | \
689 (1 << 21) | \
690 (((n) & 0xFFFFF) << 0))
691
671/* async DMA Packet types */ 692/* async DMA Packet types */
672#define DMA_PACKET_WRITE 0x2 693#define DMA_PACKET_WRITE 0x2
673#define DMA_PACKET_COPY 0x3 694#define DMA_PACKET_COPY 0x3
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 9db58530be37..4973bff37fec 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -69,6 +69,38 @@ MODULE_FIRMWARE(FIRMWARE_R520);
69 * and others in some cases. 69 * and others in some cases.
70 */ 70 */
71 71
72static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
73{
74 if (crtc == 0) {
75 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
76 return true;
77 else
78 return false;
79 } else {
80 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
81 return true;
82 else
83 return false;
84 }
85}
86
87static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
88{
89 u32 vline1, vline2;
90
91 if (crtc == 0) {
92 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
93 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
94 } else {
95 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
96 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
97 }
98 if (vline1 != vline2)
99 return true;
100 else
101 return false;
102}
103
72/** 104/**
73 * r100_wait_for_vblank - vblank wait asic callback. 105 * r100_wait_for_vblank - vblank wait asic callback.
74 * 106 *
@@ -79,36 +111,33 @@ MODULE_FIRMWARE(FIRMWARE_R520);
79 */ 111 */
80void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 112void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
81{ 113{
82 int i; 114 unsigned i = 0;
83 115
84 if (crtc >= rdev->num_crtc) 116 if (crtc >= rdev->num_crtc)
85 return; 117 return;
86 118
87 if (crtc == 0) { 119 if (crtc == 0) {
88 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) { 120 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
89 for (i = 0; i < rdev->usec_timeout; i++) { 121 return;
90 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
91 break;
92 udelay(1);
93 }
94 for (i = 0; i < rdev->usec_timeout; i++) {
95 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
96 break;
97 udelay(1);
98 }
99 }
100 } else { 122 } else {
101 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) { 123 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
102 for (i = 0; i < rdev->usec_timeout; i++) { 124 return;
103 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)) 125 }
104 break; 126
105 udelay(1); 127 /* depending on when we hit vblank, we may be close to active; if so,
106 } 128 * wait for another frame.
107 for (i = 0; i < rdev->usec_timeout; i++) { 129 */
108 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 130 while (r100_is_in_vblank(rdev, crtc)) {
109 break; 131 if (i++ % 100 == 0) {
110 udelay(1); 132 if (!r100_is_counter_moving(rdev, crtc))
111 } 133 break;
134 }
135 }
136
137 while (!r100_is_in_vblank(rdev, crtc)) {
138 if (i++ % 100 == 0) {
139 if (!r100_is_counter_moving(rdev, crtc))
140 break;
112 } 141 }
113 } 142 }
114} 143}
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index c0dc8d3ba0bb..1dd0d32993d5 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -358,7 +358,9 @@
358#define AVIVO_D1CRTC_STATUS_HV_COUNT 0x60ac 358#define AVIVO_D1CRTC_STATUS_HV_COUNT 0x60ac
359#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 359#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
360 360
361#define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0
361#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 362#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
363#define AVIVO_D1CRTC_UPDATE_LOCK 0x60e8
362 364
363/* master controls */ 365/* master controls */
364#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 366#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 0740db3fcd22..1a08008c978b 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1145,7 +1145,7 @@ static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc
1145 } 1145 }
1146 if (rdev->flags & RADEON_IS_AGP) { 1146 if (rdev->flags & RADEON_IS_AGP) {
1147 size_bf = mc->gtt_start; 1147 size_bf = mc->gtt_start;
1148 size_af = 0xFFFFFFFF - mc->gtt_end; 1148 size_af = mc->mc_mask - mc->gtt_end;
1149 if (size_bf > size_af) { 1149 if (size_bf > size_af) {
1150 if (mc->mc_vram_size > size_bf) { 1150 if (mc->mc_vram_size > size_bf) {
1151 dev_warn(rdev->dev, "limiting VRAM\n"); 1151 dev_warn(rdev->dev, "limiting VRAM\n");
@@ -2552,6 +2552,193 @@ void r600_dma_fini(struct radeon_device *rdev)
2552} 2552}
2553 2553
2554/* 2554/*
2555 * UVD
2556 */
2557int r600_uvd_rbc_start(struct radeon_device *rdev)
2558{
2559 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2560 uint64_t rptr_addr;
2561 uint32_t rb_bufsz, tmp;
2562 int r;
2563
2564 rptr_addr = rdev->wb.gpu_addr + R600_WB_UVD_RPTR_OFFSET;
2565
2566 if (upper_32_bits(rptr_addr) != upper_32_bits(ring->gpu_addr)) {
2567 DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n");
2568 return -EINVAL;
2569 }
2570
2571 /* force RBC into idle state */
2572 WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2573
2574 /* Set the write pointer delay */
2575 WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
2576
2577 /* set the wb address */
2578 WREG32(UVD_RBC_RB_RPTR_ADDR, rptr_addr >> 2);
2579
2580 /* programm the 4GB memory segment for rptr and ring buffer */
2581 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(rptr_addr) |
2582 (0x7 << 16) | (0x1 << 31));
2583
2584 /* Initialize the ring buffer's read and write pointers */
2585 WREG32(UVD_RBC_RB_RPTR, 0x0);
2586
2587 ring->wptr = ring->rptr = RREG32(UVD_RBC_RB_RPTR);
2588 WREG32(UVD_RBC_RB_WPTR, ring->wptr);
2589
2590 /* set the ring address */
2591 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
2592
2593 /* Set ring buffer size */
2594 rb_bufsz = drm_order(ring->ring_size);
2595 rb_bufsz = (0x1 << 8) | rb_bufsz;
2596 WREG32(UVD_RBC_RB_CNTL, rb_bufsz);
2597
2598 ring->ready = true;
2599 r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);
2600 if (r) {
2601 ring->ready = false;
2602 return r;
2603 }
2604
2605 r = radeon_ring_lock(rdev, ring, 10);
2606 if (r) {
2607 DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);
2608 return r;
2609 }
2610
2611 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
2612 radeon_ring_write(ring, tmp);
2613 radeon_ring_write(ring, 0xFFFFF);
2614
2615 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
2616 radeon_ring_write(ring, tmp);
2617 radeon_ring_write(ring, 0xFFFFF);
2618
2619 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
2620 radeon_ring_write(ring, tmp);
2621 radeon_ring_write(ring, 0xFFFFF);
2622
2623 /* Clear timeout status bits */
2624 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));
2625 radeon_ring_write(ring, 0x8);
2626
2627 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
2628 radeon_ring_write(ring, 3);
2629
2630 radeon_ring_unlock_commit(rdev, ring);
2631
2632 return 0;
2633}
2634
2635void r600_uvd_rbc_stop(struct radeon_device *rdev)
2636{
2637 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2638
2639 /* force RBC into idle state */
2640 WREG32(UVD_RBC_RB_CNTL, 0x11010101);
2641 ring->ready = false;
2642}
2643
2644int r600_uvd_init(struct radeon_device *rdev)
2645{
2646 int i, j, r;
2647
2648 /* raise clocks while booting up the VCPU */
2649 radeon_set_uvd_clocks(rdev, 53300, 40000);
2650
2651 /* disable clock gating */
2652 WREG32(UVD_CGC_GATE, 0);
2653
2654 /* disable interupt */
2655 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));
2656
2657 /* put LMI, VCPU, RBC etc... into reset */
2658 WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
2659 LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET |
2660 CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET);
2661 mdelay(5);
2662
2663 /* take UVD block out of reset */
2664 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
2665 mdelay(5);
2666
2667 /* initialize UVD memory controller */
2668 WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
2669 (1 << 21) | (1 << 9) | (1 << 20));
2670
2671 /* disable byte swapping */
2672 WREG32(UVD_LMI_SWAP_CNTL, 0);
2673 WREG32(UVD_MP_SWAP_CNTL, 0);
2674
2675 WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
2676 WREG32(UVD_MPC_SET_MUXA1, 0x0);
2677 WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);
2678 WREG32(UVD_MPC_SET_MUXB1, 0x0);
2679 WREG32(UVD_MPC_SET_ALU, 0);
2680 WREG32(UVD_MPC_SET_MUX, 0x88);
2681
2682 /* Stall UMC */
2683 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
2684 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
2685
2686 /* take all subblocks out of reset, except VCPU */
2687 WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
2688 mdelay(5);
2689
2690 /* enable VCPU clock */
2691 WREG32(UVD_VCPU_CNTL, 1 << 9);
2692
2693 /* enable UMC */
2694 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
2695
2696 /* boot up the VCPU */
2697 WREG32(UVD_SOFT_RESET, 0);
2698 mdelay(10);
2699
2700 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
2701
2702 for (i = 0; i < 10; ++i) {
2703 uint32_t status;
2704 for (j = 0; j < 100; ++j) {
2705 status = RREG32(UVD_STATUS);
2706 if (status & 2)
2707 break;
2708 mdelay(10);
2709 }
2710 r = 0;
2711 if (status & 2)
2712 break;
2713
2714 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
2715 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
2716 mdelay(10);
2717 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
2718 mdelay(10);
2719 r = -1;
2720 }
2721
2722 if (r) {
2723 DRM_ERROR("UVD not responding, giving up!!!\n");
2724 radeon_set_uvd_clocks(rdev, 0, 0);
2725 return r;
2726 }
2727
2728 /* enable interupt */
2729 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
2730
2731 r = r600_uvd_rbc_start(rdev);
2732 if (!r)
2733 DRM_INFO("UVD initialized successfully.\n");
2734
2735 /* lower clocks again */
2736 radeon_set_uvd_clocks(rdev, 0, 0);
2737
2738 return r;
2739}
2740
2741/*
2555 * GPU scratch registers helpers function. 2742 * GPU scratch registers helpers function.
2556 */ 2743 */
2557void r600_scratch_init(struct radeon_device *rdev) 2744void r600_scratch_init(struct radeon_device *rdev)
@@ -2660,6 +2847,40 @@ int r600_dma_ring_test(struct radeon_device *rdev,
2660 return r; 2847 return r;
2661} 2848}
2662 2849
2850int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2851{
2852 uint32_t tmp = 0;
2853 unsigned i;
2854 int r;
2855
2856 WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);
2857 r = radeon_ring_lock(rdev, ring, 3);
2858 if (r) {
2859 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
2860 ring->idx, r);
2861 return r;
2862 }
2863 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
2864 radeon_ring_write(ring, 0xDEADBEEF);
2865 radeon_ring_unlock_commit(rdev, ring);
2866 for (i = 0; i < rdev->usec_timeout; i++) {
2867 tmp = RREG32(UVD_CONTEXT_ID);
2868 if (tmp == 0xDEADBEEF)
2869 break;
2870 DRM_UDELAY(1);
2871 }
2872
2873 if (i < rdev->usec_timeout) {
2874 DRM_INFO("ring test on %d succeeded in %d usecs\n",
2875 ring->idx, i);
2876 } else {
2877 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2878 ring->idx, tmp);
2879 r = -EINVAL;
2880 }
2881 return r;
2882}
2883
2663/* 2884/*
2664 * CP fences/semaphores 2885 * CP fences/semaphores
2665 */ 2886 */
@@ -2711,6 +2932,30 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
2711 } 2932 }
2712} 2933}
2713 2934
2935void r600_uvd_fence_emit(struct radeon_device *rdev,
2936 struct radeon_fence *fence)
2937{
2938 struct radeon_ring *ring = &rdev->ring[fence->ring];
2939 uint32_t addr = rdev->fence_drv[fence->ring].gpu_addr;
2940
2941 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
2942 radeon_ring_write(ring, fence->seq);
2943 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
2944 radeon_ring_write(ring, addr & 0xffffffff);
2945 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
2946 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2947 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
2948 radeon_ring_write(ring, 0);
2949
2950 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
2951 radeon_ring_write(ring, 0);
2952 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
2953 radeon_ring_write(ring, 0);
2954 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
2955 radeon_ring_write(ring, 2);
2956 return;
2957}
2958
2714void r600_semaphore_ring_emit(struct radeon_device *rdev, 2959void r600_semaphore_ring_emit(struct radeon_device *rdev,
2715 struct radeon_ring *ring, 2960 struct radeon_ring *ring,
2716 struct radeon_semaphore *semaphore, 2961 struct radeon_semaphore *semaphore,
@@ -2780,6 +3025,23 @@ void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2780 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 3025 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2781} 3026}
2782 3027
3028void r600_uvd_semaphore_emit(struct radeon_device *rdev,
3029 struct radeon_ring *ring,
3030 struct radeon_semaphore *semaphore,
3031 bool emit_wait)
3032{
3033 uint64_t addr = semaphore->gpu_addr;
3034
3035 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
3036 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
3037
3038 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
3039 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
3040
3041 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
3042 radeon_ring_write(ring, emit_wait ? 1 : 0);
3043}
3044
2783int r600_copy_blit(struct radeon_device *rdev, 3045int r600_copy_blit(struct radeon_device *rdev,
2784 uint64_t src_offset, 3046 uint64_t src_offset,
2785 uint64_t dst_offset, 3047 uint64_t dst_offset,
@@ -3183,6 +3445,16 @@ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3183 radeon_ring_write(ring, ib->length_dw); 3445 radeon_ring_write(ring, ib->length_dw);
3184} 3446}
3185 3447
3448void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3449{
3450 struct radeon_ring *ring = &rdev->ring[ib->ring];
3451
3452 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));
3453 radeon_ring_write(ring, ib->gpu_addr);
3454 radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));
3455 radeon_ring_write(ring, ib->length_dw);
3456}
3457
3186int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3458int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3187{ 3459{
3188 struct radeon_ib ib; 3460 struct radeon_ib ib;
@@ -3300,6 +3572,41 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3300 return r; 3572 return r;
3301} 3573}
3302 3574
3575int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3576{
3577 struct radeon_fence *fence = NULL;
3578 int r;
3579
3580 r = radeon_set_uvd_clocks(rdev, 53300, 40000);
3581 if (r) {
3582 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
3583 return r;
3584 }
3585
3586 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
3587 if (r) {
3588 DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
3589 goto error;
3590 }
3591
3592 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);
3593 if (r) {
3594 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
3595 goto error;
3596 }
3597
3598 r = radeon_fence_wait(fence, false);
3599 if (r) {
3600 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3601 goto error;
3602 }
3603 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
3604error:
3605 radeon_fence_unref(&fence);
3606 radeon_set_uvd_clocks(rdev, 0, 0);
3607 return r;
3608}
3609
3303/** 3610/**
3304 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine 3611 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3305 * 3612 *
@@ -4232,7 +4539,7 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4232 4539
4233void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4540void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4234{ 4541{
4235 u32 link_width_cntl, mask, target_reg; 4542 u32 link_width_cntl, mask;
4236 4543
4237 if (rdev->flags & RADEON_IS_IGP) 4544 if (rdev->flags & RADEON_IS_IGP)
4238 return; 4545 return;
@@ -4244,7 +4551,7 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4244 if (ASIC_IS_X2(rdev)) 4551 if (ASIC_IS_X2(rdev))
4245 return; 4552 return;
4246 4553
4247 /* FIXME wait for idle */ 4554 radeon_gui_idle(rdev);
4248 4555
4249 switch (lanes) { 4556 switch (lanes) {
4250 case 0: 4557 case 0:
@@ -4263,53 +4570,24 @@ void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4263 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4570 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4264 break; 4571 break;
4265 case 12: 4572 case 12:
4573 /* not actually supported */
4266 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4574 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4267 break; 4575 break;
4268 case 16: 4576 case 16:
4269 default:
4270 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4577 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4271 break; 4578 break;
4272 } 4579 default:
4273 4580 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4274 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4275
4276 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4277 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4278 return;
4279
4280 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4281 return; 4581 return;
4582 }
4282 4583
4283 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 4584 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4284 RADEON_PCIE_LC_RECONFIG_NOW | 4585 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4285 R600_PCIE_LC_RENEGOTIATE_EN | 4586 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4286 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4587 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4287 link_width_cntl |= mask; 4588 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4288
4289 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4290
4291 /* some northbridges can renegotiate the link rather than requiring
4292 * a complete re-config.
4293 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4294 */
4295 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4296 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4297 else
4298 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4299
4300 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4301 RADEON_PCIE_LC_RECONFIG_NOW));
4302
4303 if (rdev->family >= CHIP_RV770)
4304 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4305 else
4306 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4307
4308 /* wait for lane set to complete */
4309 link_width_cntl = RREG32(target_reg);
4310 while (link_width_cntl == 0xffffffff)
4311 link_width_cntl = RREG32(target_reg);
4312 4589
4590 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4313} 4591}
4314 4592
4315int r600_get_pcie_lanes(struct radeon_device *rdev) 4593int r600_get_pcie_lanes(struct radeon_device *rdev)
@@ -4326,13 +4604,11 @@ int r600_get_pcie_lanes(struct radeon_device *rdev)
4326 if (ASIC_IS_X2(rdev)) 4604 if (ASIC_IS_X2(rdev))
4327 return 0; 4605 return 0;
4328 4606
4329 /* FIXME wait for idle */ 4607 radeon_gui_idle(rdev);
4330 4608
4331 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4609 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4332 4610
4333 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4611 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4334 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4335 return 0;
4336 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4612 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4337 return 1; 4613 return 1;
4338 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4614 case RADEON_PCIE_LC_LINK_WIDTH_X2:
@@ -4341,6 +4617,10 @@ int r600_get_pcie_lanes(struct radeon_device *rdev)
4341 return 4; 4617 return 4;
4342 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4618 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4343 return 8; 4619 return 8;
4620 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4621 /* not actually supported */
4622 return 12;
4623 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4344 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4624 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4345 default: 4625 default:
4346 return 16; 4626 return 16;
@@ -4378,7 +4658,7 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4378 if (!(mask & DRM_PCIE_SPEED_50)) 4658 if (!(mask & DRM_PCIE_SPEED_50))
4379 return; 4659 return;
4380 4660
4381 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4661 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4382 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4662 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4383 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4663 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4384 return; 4664 return;
@@ -4391,23 +4671,23 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4391 (rdev->family == CHIP_RV620) || 4671 (rdev->family == CHIP_RV620) ||
4392 (rdev->family == CHIP_RV635)) { 4672 (rdev->family == CHIP_RV635)) {
4393 /* advertise upconfig capability */ 4673 /* advertise upconfig capability */
4394 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4674 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4395 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4675 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4396 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4676 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4397 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4677 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4398 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4678 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4399 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4679 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4400 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4680 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4401 LC_RECONFIG_ARC_MISSING_ESCAPE); 4681 LC_RECONFIG_ARC_MISSING_ESCAPE);
4402 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4682 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4403 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4683 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4404 } else { 4684 } else {
4405 link_width_cntl |= LC_UPCONFIGURE_DIS; 4685 link_width_cntl |= LC_UPCONFIGURE_DIS;
4406 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4686 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4407 } 4687 }
4408 } 4688 }
4409 4689
4410 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4690 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4411 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4691 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4412 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4692 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4413 4693
@@ -4428,7 +4708,7 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4428 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4708 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4429 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4709 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4430 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4710 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4431 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4711 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4432 4712
4433 tmp = RREG32(0x541c); 4713 tmp = RREG32(0x541c);
4434 WREG32(0x541c, tmp | 0x8); 4714 WREG32(0x541c, tmp | 0x8);
@@ -4442,27 +4722,27 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4442 if ((rdev->family == CHIP_RV670) || 4722 if ((rdev->family == CHIP_RV670) ||
4443 (rdev->family == CHIP_RV620) || 4723 (rdev->family == CHIP_RV620) ||
4444 (rdev->family == CHIP_RV635)) { 4724 (rdev->family == CHIP_RV635)) {
4445 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); 4725 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4446 training_cntl &= ~LC_POINT_7_PLUS_EN; 4726 training_cntl &= ~LC_POINT_7_PLUS_EN;
4447 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); 4727 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4448 } else { 4728 } else {
4449 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4729 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4450 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4730 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4451 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4731 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4452 } 4732 }
4453 4733
4454 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4734 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4455 speed_cntl |= LC_GEN2_EN_STRAP; 4735 speed_cntl |= LC_GEN2_EN_STRAP;
4456 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4736 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4457 4737
4458 } else { 4738 } else {
4459 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4739 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4460 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4740 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4461 if (1) 4741 if (1)
4462 link_width_cntl |= LC_UPCONFIGURE_DIS; 4742 link_width_cntl |= LC_UPCONFIGURE_DIS;
4463 else 4743 else
4464 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4744 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4465 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4745 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4466 } 4746 }
4467} 4747}
4468 4748
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index cb03fe22b0ab..c92eb86a8e55 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -57,10 +57,7 @@ static bool radeon_dig_encoder(struct drm_encoder *encoder)
57 */ 57 */
58static int r600_audio_chipset_supported(struct radeon_device *rdev) 58static int r600_audio_chipset_supported(struct radeon_device *rdev)
59{ 59{
60 return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE6(rdev)) 60 return ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE6(rdev);
61 || rdev->family == CHIP_RS600
62 || rdev->family == CHIP_RS690
63 || rdev->family == CHIP_RS740;
64} 61}
65 62
66struct r600_audio r600_audio_status(struct radeon_device *rdev) 63struct r600_audio r600_audio_status(struct radeon_device *rdev)
@@ -184,65 +181,6 @@ int r600_audio_init(struct radeon_device *rdev)
184} 181}
185 182
186/* 183/*
187 * atach the audio codec to the clock source of the encoder
188 */
189void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
190{
191 struct drm_device *dev = encoder->dev;
192 struct radeon_device *rdev = dev->dev_private;
193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
194 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
195 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
196 int base_rate = 48000;
197
198 switch (radeon_encoder->encoder_id) {
199 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
200 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
201 WREG32_P(R600_AUDIO_TIMING, 0, ~0x301);
202 break;
203 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
204 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
205 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
206 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
207 WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);
208 break;
209 default:
210 dev_err(rdev->dev, "Unsupported encoder type 0x%02X\n",
211 radeon_encoder->encoder_id);
212 return;
213 }
214
215 if (ASIC_IS_DCE4(rdev)) {
216 /* TODO: other PLLs? */
217 WREG32(EVERGREEN_AUDIO_PLL1_MUL, base_rate * 10);
218 WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);
219 WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071);
220
221 /* Select DTO source */
222 WREG32(0x5ac, radeon_crtc->crtc_id);
223 } else {
224 switch (dig->dig_encoder) {
225 case 0:
226 WREG32(R600_AUDIO_PLL1_MUL, base_rate * 50);
227 WREG32(R600_AUDIO_PLL1_DIV, clock * 100);
228 WREG32(R600_AUDIO_CLK_SRCSEL, 0);
229 break;
230
231 case 1:
232 WREG32(R600_AUDIO_PLL2_MUL, base_rate * 50);
233 WREG32(R600_AUDIO_PLL2_DIV, clock * 100);
234 WREG32(R600_AUDIO_CLK_SRCSEL, 1);
235 break;
236 default:
237 dev_err(rdev->dev,
238 "Unsupported DIG on encoder 0x%02X\n",
239 radeon_encoder->encoder_id);
240 return;
241 }
242 }
243}
244
245/*
246 * release the audio timer 184 * release the audio timer
247 * TODO: How to do this correctly on SMP systems? 185 * TODO: How to do this correctly on SMP systems?
248 */ 186 */
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 21ecc0e12dc4..47f180a79352 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -226,6 +226,39 @@ static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
226 value, ~HDMI0_AUDIO_TEST_EN); 226 value, ~HDMI0_AUDIO_TEST_EN);
227} 227}
228 228
229void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
230{
231 struct drm_device *dev = encoder->dev;
232 struct radeon_device *rdev = dev->dev_private;
233 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
234 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
235 u32 base_rate = 48000;
236
237 if (!dig || !dig->afmt)
238 return;
239
240 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
241 * doesn't matter which one you use. Just use the first one.
242 */
243 /* XXX: properly calculate this */
244 /* XXX two dtos; generally use dto0 for hdmi */
245 /* Express [24MHz / target pixel clock] as an exact rational
246 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
247 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
248 */
249 if (ASIC_IS_DCE3(rdev)) {
250 /* according to the reg specs, this should DCE3.2 only, but in
251 * practice it seems to cover DCE3.0 as well.
252 */
253 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50);
254 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
255 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
256 } else {
257 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
258 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) |
259 AUDIO_DTO_MODULE(clock * 100));
260 }
261}
229 262
230/* 263/*
231 * update the info frames with the data from the current display mode 264 * update the info frames with the data from the current display mode
@@ -246,7 +279,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
246 return; 279 return;
247 offset = dig->afmt->offset; 280 offset = dig->afmt->offset;
248 281
249 r600_audio_set_clock(encoder, mode->clock); 282 r600_audio_set_dto(encoder, mode->clock);
250 283
251 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 284 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
252 HDMI0_NULL_SEND); /* send null packets when required */ 285 HDMI0_NULL_SEND); /* send null packets when required */
@@ -415,114 +448,73 @@ void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
415/* 448/*
416 * enable the HDMI engine 449 * enable the HDMI engine
417 */ 450 */
418void r600_hdmi_enable(struct drm_encoder *encoder) 451void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
419{ 452{
420 struct drm_device *dev = encoder->dev; 453 struct drm_device *dev = encoder->dev;
421 struct radeon_device *rdev = dev->dev_private; 454 struct radeon_device *rdev = dev->dev_private;
422 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 455 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
423 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 456 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
424 uint32_t offset; 457 u32 hdmi = HDMI0_ERROR_ACK;
425 u32 hdmi;
426
427 if (ASIC_IS_DCE6(rdev))
428 return;
429 458
430 /* Silent, r600_hdmi_enable will raise WARN for us */ 459 /* Silent, r600_hdmi_enable will raise WARN for us */
431 if (dig->afmt->enabled) 460 if (enable && dig->afmt->enabled)
461 return;
462 if (!enable && !dig->afmt->enabled)
432 return; 463 return;
433 offset = dig->afmt->offset;
434 464
435 /* Older chipsets require setting HDMI and routing manually */ 465 /* Older chipsets require setting HDMI and routing manually */
436 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 466 if (!ASIC_IS_DCE3(rdev)) {
437 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE; 467 if (enable)
468 hdmi |= HDMI0_ENABLE;
438 switch (radeon_encoder->encoder_id) { 469 switch (radeon_encoder->encoder_id) {
439 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 470 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
440 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, 471 if (enable) {
441 ~AVIVO_TMDSA_CNTL_HDMI_EN); 472 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
442 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 473 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
474 } else {
475 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
476 }
443 break; 477 break;
444 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 478 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
445 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, 479 if (enable) {
446 ~AVIVO_LVTMA_CNTL_HDMI_EN); 480 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
447 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 481 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
482 } else {
483 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
484 }
448 break; 485 break;
449 case ENCODER_OBJECT_ID_INTERNAL_DDI: 486 case ENCODER_OBJECT_ID_INTERNAL_DDI:
450 WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN); 487 if (enable) {
451 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 488 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
489 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
490 } else {
491 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
492 }
452 break; 493 break;
453 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 494 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
454 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 495 if (enable)
496 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
455 break; 497 break;
456 default: 498 default:
457 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 499 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
458 radeon_encoder->encoder_id); 500 radeon_encoder->encoder_id);
459 break; 501 break;
460 } 502 }
461 WREG32(HDMI0_CONTROL + offset, hdmi); 503 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
462 } 504 }
463 505
464 if (rdev->irq.installed) { 506 if (rdev->irq.installed) {
465 /* if irq is available use it */ 507 /* if irq is available use it */
466 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 508 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
509 if (enable)
510 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
511 else
512 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
467 } 513 }
468 514
469 dig->afmt->enabled = true; 515 dig->afmt->enabled = enable;
470 516
471 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", 517 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
472 offset, radeon_encoder->encoder_id); 518 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
473} 519}
474 520
475/*
476 * disable the HDMI engine
477 */
478void r600_hdmi_disable(struct drm_encoder *encoder)
479{
480 struct drm_device *dev = encoder->dev;
481 struct radeon_device *rdev = dev->dev_private;
482 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
483 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
484 uint32_t offset;
485
486 if (ASIC_IS_DCE6(rdev))
487 return;
488
489 /* Called for ATOM_ENCODER_MODE_HDMI only */
490 if (!dig || !dig->afmt) {
491 return;
492 }
493 if (!dig->afmt->enabled)
494 return;
495 offset = dig->afmt->offset;
496
497 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
498 offset, radeon_encoder->encoder_id);
499
500 /* disable irq */
501 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
502
503 /* Older chipsets not handled by AtomBIOS */
504 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
505 switch (radeon_encoder->encoder_id) {
506 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
507 WREG32_P(AVIVO_TMDSA_CNTL, 0,
508 ~AVIVO_TMDSA_CNTL_HDMI_EN);
509 break;
510 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
511 WREG32_P(AVIVO_LVTMA_CNTL, 0,
512 ~AVIVO_LVTMA_CNTL_HDMI_EN);
513 break;
514 case ENCODER_OBJECT_ID_INTERNAL_DDI:
515 WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);
516 break;
517 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
518 break;
519 default:
520 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
521 radeon_encoder->encoder_id);
522 break;
523 }
524 WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK);
525 }
526
527 dig->afmt->enabled = false;
528}
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index a42ba11a3bed..acb146c06973 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -691,6 +691,7 @@
691#define SRBM_SOFT_RESET 0xe60 691#define SRBM_SOFT_RESET 0xe60
692# define SOFT_RESET_DMA (1 << 12) 692# define SOFT_RESET_DMA (1 << 12)
693# define SOFT_RESET_RLC (1 << 13) 693# define SOFT_RESET_RLC (1 << 13)
694# define SOFT_RESET_UVD (1 << 18)
694# define RV770_SOFT_RESET_DMA (1 << 20) 695# define RV770_SOFT_RESET_DMA (1 << 20)
695 696
696#define CP_INT_CNTL 0xc124 697#define CP_INT_CNTL 0xc124
@@ -909,7 +910,12 @@
909# define TARGET_LINK_SPEED_MASK (0xf << 0) 910# define TARGET_LINK_SPEED_MASK (0xf << 0)
910# define SELECTABLE_DEEMPHASIS (1 << 6) 911# define SELECTABLE_DEEMPHASIS (1 << 6)
911 912
912/* Audio clocks */ 913/* Audio clocks DCE 2.0/3.0 */
914#define AUDIO_DTO 0x7340
915# define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0)
916# define AUDIO_DTO_MODULE(x) (((x) & 0xffff) << 16)
917
918/* Audio clocks DCE 3.2 */
913#define DCCG_AUDIO_DTO0_PHASE 0x0514 919#define DCCG_AUDIO_DTO0_PHASE 0x0514
914#define DCCG_AUDIO_DTO0_MODULE 0x0518 920#define DCCG_AUDIO_DTO0_MODULE 0x0518
915#define DCCG_AUDIO_DTO0_LOAD 0x051c 921#define DCCG_AUDIO_DTO0_LOAD 0x051c
@@ -1143,6 +1149,70 @@
1143# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 1149# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
1144 1150
1145/* 1151/*
1152 * UVD
1153 */
1154#define UVD_SEMA_ADDR_LOW 0xef00
1155#define UVD_SEMA_ADDR_HIGH 0xef04
1156#define UVD_SEMA_CMD 0xef08
1157
1158#define UVD_GPCOM_VCPU_CMD 0xef0c
1159#define UVD_GPCOM_VCPU_DATA0 0xef10
1160#define UVD_GPCOM_VCPU_DATA1 0xef14
1161#define UVD_ENGINE_CNTL 0xef18
1162
1163#define UVD_SEMA_CNTL 0xf400
1164#define UVD_RB_ARB_CTRL 0xf480
1165
1166#define UVD_LMI_EXT40_ADDR 0xf498
1167#define UVD_CGC_GATE 0xf4a8
1168#define UVD_LMI_CTRL2 0xf4f4
1169#define UVD_MASTINT_EN 0xf500
1170#define UVD_LMI_ADDR_EXT 0xf594
1171#define UVD_LMI_CTRL 0xf598
1172#define UVD_LMI_SWAP_CNTL 0xf5b4
1173#define UVD_MP_SWAP_CNTL 0xf5bC
1174#define UVD_MPC_CNTL 0xf5dC
1175#define UVD_MPC_SET_MUXA0 0xf5e4
1176#define UVD_MPC_SET_MUXA1 0xf5e8
1177#define UVD_MPC_SET_MUXB0 0xf5eC
1178#define UVD_MPC_SET_MUXB1 0xf5f0
1179#define UVD_MPC_SET_MUX 0xf5f4
1180#define UVD_MPC_SET_ALU 0xf5f8
1181
1182#define UVD_VCPU_CNTL 0xf660
1183#define UVD_SOFT_RESET 0xf680
1184#define RBC_SOFT_RESET (1<<0)
1185#define LBSI_SOFT_RESET (1<<1)
1186#define LMI_SOFT_RESET (1<<2)
1187#define VCPU_SOFT_RESET (1<<3)
1188#define CSM_SOFT_RESET (1<<5)
1189#define CXW_SOFT_RESET (1<<6)
1190#define TAP_SOFT_RESET (1<<7)
1191#define LMI_UMC_SOFT_RESET (1<<13)
1192#define UVD_RBC_IB_BASE 0xf684
1193#define UVD_RBC_IB_SIZE 0xf688
1194#define UVD_RBC_RB_BASE 0xf68c
1195#define UVD_RBC_RB_RPTR 0xf690
1196#define UVD_RBC_RB_WPTR 0xf694
1197#define UVD_RBC_RB_WPTR_CNTL 0xf698
1198
1199#define UVD_STATUS 0xf6bc
1200
1201#define UVD_SEMA_TIMEOUT_STATUS 0xf6c0
1202#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0xf6c4
1203#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0xf6c8
1204#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0xf6cc
1205
1206#define UVD_RBC_RB_CNTL 0xf6a4
1207#define UVD_RBC_RB_RPTR_ADDR 0xf6a8
1208
1209#define UVD_CONTEXT_ID 0xf6f4
1210
1211# define UPLL_CTLREQ_MASK 0x00000008
1212# define UPLL_CTLACK_MASK 0x40000000
1213# define UPLL_CTLACK2_MASK 0x80000000
1214
1215/*
1146 * PM4 1216 * PM4
1147 */ 1217 */
1148#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1218#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 8263af3fd832..1442ce765d48 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -95,6 +95,7 @@ extern int radeon_hw_i2c;
95extern int radeon_pcie_gen2; 95extern int radeon_pcie_gen2;
96extern int radeon_msi; 96extern int radeon_msi;
97extern int radeon_lockup_timeout; 97extern int radeon_lockup_timeout;
98extern int radeon_fastfb;
98 99
99/* 100/*
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting 101 * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -109,24 +110,27 @@ extern int radeon_lockup_timeout;
109#define RADEON_BIOS_NUM_SCRATCH 8 110#define RADEON_BIOS_NUM_SCRATCH 8
110 111
111/* max number of rings */ 112/* max number of rings */
112#define RADEON_NUM_RINGS 5 113#define RADEON_NUM_RINGS 6
113 114
114/* fence seq are set to this number when signaled */ 115/* fence seq are set to this number when signaled */
115#define RADEON_FENCE_SIGNALED_SEQ 0LL 116#define RADEON_FENCE_SIGNALED_SEQ 0LL
116 117
117/* internal ring indices */ 118/* internal ring indices */
118/* r1xx+ has gfx CP ring */ 119/* r1xx+ has gfx CP ring */
119#define RADEON_RING_TYPE_GFX_INDEX 0 120#define RADEON_RING_TYPE_GFX_INDEX 0
120 121
121/* cayman has 2 compute CP rings */ 122/* cayman has 2 compute CP rings */
122#define CAYMAN_RING_TYPE_CP1_INDEX 1 123#define CAYMAN_RING_TYPE_CP1_INDEX 1
123#define CAYMAN_RING_TYPE_CP2_INDEX 2 124#define CAYMAN_RING_TYPE_CP2_INDEX 2
124 125
125/* R600+ has an async dma ring */ 126/* R600+ has an async dma ring */
126#define R600_RING_TYPE_DMA_INDEX 3 127#define R600_RING_TYPE_DMA_INDEX 3
127/* cayman add a second async dma ring */ 128/* cayman add a second async dma ring */
128#define CAYMAN_RING_TYPE_DMA1_INDEX 4 129#define CAYMAN_RING_TYPE_DMA1_INDEX 4
129 130
131/* R600+ */
132#define R600_RING_TYPE_UVD_INDEX 5
133
130/* hardcode those limit for now */ 134/* hardcode those limit for now */
131#define RADEON_VA_IB_OFFSET (1 << 20) 135#define RADEON_VA_IB_OFFSET (1 << 20)
132#define RADEON_VA_RESERVED_SIZE (8 << 20) 136#define RADEON_VA_RESERVED_SIZE (8 << 20)
@@ -202,6 +206,11 @@ void radeon_pm_suspend(struct radeon_device *rdev);
202void radeon_pm_resume(struct radeon_device *rdev); 206void radeon_pm_resume(struct radeon_device *rdev);
203void radeon_combios_get_power_modes(struct radeon_device *rdev); 207void radeon_combios_get_power_modes(struct radeon_device *rdev);
204void radeon_atombios_get_power_modes(struct radeon_device *rdev); 208void radeon_atombios_get_power_modes(struct radeon_device *rdev);
209int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
210 u8 clock_type,
211 u32 clock,
212 bool strobe_mode,
213 struct atom_clock_dividers *dividers);
205void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 214void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
206void rs690_pm_info(struct radeon_device *rdev); 215void rs690_pm_info(struct radeon_device *rdev);
207extern int rv6xx_get_temp(struct radeon_device *rdev); 216extern int rv6xx_get_temp(struct radeon_device *rdev);
@@ -349,7 +358,8 @@ struct radeon_bo {
349 struct radeon_device *rdev; 358 struct radeon_device *rdev;
350 struct drm_gem_object gem_base; 359 struct drm_gem_object gem_base;
351 360
352 struct ttm_bo_kmap_obj dma_buf_vmap; 361 struct ttm_bo_kmap_obj dma_buf_vmap;
362 pid_t pid;
353}; 363};
354#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 364#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
355 365
@@ -357,11 +367,14 @@ struct radeon_bo_list {
357 struct ttm_validate_buffer tv; 367 struct ttm_validate_buffer tv;
358 struct radeon_bo *bo; 368 struct radeon_bo *bo;
359 uint64_t gpu_offset; 369 uint64_t gpu_offset;
360 unsigned rdomain; 370 bool written;
361 unsigned wdomain; 371 unsigned domain;
372 unsigned alt_domain;
362 u32 tiling_flags; 373 u32 tiling_flags;
363}; 374};
364 375
376int radeon_gem_debugfs_init(struct radeon_device *rdev);
377
365/* sub-allocation manager, it has to be protected by another lock. 378/* sub-allocation manager, it has to be protected by another lock.
366 * By conception this is an helper for other part of the driver 379 * By conception this is an helper for other part of the driver
367 * like the indirect buffer or semaphore, which both have their 380 * like the indirect buffer or semaphore, which both have their
@@ -517,6 +530,7 @@ struct radeon_mc {
517 bool vram_is_ddr; 530 bool vram_is_ddr;
518 bool igp_sideport_enabled; 531 bool igp_sideport_enabled;
519 u64 gtt_base_align; 532 u64 gtt_base_align;
533 u64 mc_mask;
520}; 534};
521 535
522bool radeon_combios_sideport_present(struct radeon_device *rdev); 536bool radeon_combios_sideport_present(struct radeon_device *rdev);
@@ -918,6 +932,7 @@ struct radeon_wb {
918#define R600_WB_DMA_RPTR_OFFSET 1792 932#define R600_WB_DMA_RPTR_OFFSET 1792
919#define R600_WB_IH_WPTR_OFFSET 2048 933#define R600_WB_IH_WPTR_OFFSET 2048
920#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 934#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
935#define R600_WB_UVD_RPTR_OFFSET 2560
921#define R600_WB_EVENT_OFFSET 3072 936#define R600_WB_EVENT_OFFSET 3072
922 937
923/** 938/**
@@ -1118,6 +1133,46 @@ struct radeon_pm {
1118int radeon_pm_get_type_index(struct radeon_device *rdev, 1133int radeon_pm_get_type_index(struct radeon_device *rdev,
1119 enum radeon_pm_state_type ps_type, 1134 enum radeon_pm_state_type ps_type,
1120 int instance); 1135 int instance);
1136/*
1137 * UVD
1138 */
1139#define RADEON_MAX_UVD_HANDLES 10
1140#define RADEON_UVD_STACK_SIZE (1024*1024)
1141#define RADEON_UVD_HEAP_SIZE (1024*1024)
1142
1143struct radeon_uvd {
1144 struct radeon_bo *vcpu_bo;
1145 void *cpu_addr;
1146 uint64_t gpu_addr;
1147 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1148 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1149 struct delayed_work idle_work;
1150};
1151
1152int radeon_uvd_init(struct radeon_device *rdev);
1153void radeon_uvd_fini(struct radeon_device *rdev);
1154int radeon_uvd_suspend(struct radeon_device *rdev);
1155int radeon_uvd_resume(struct radeon_device *rdev);
1156int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1157 uint32_t handle, struct radeon_fence **fence);
1158int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1159 uint32_t handle, struct radeon_fence **fence);
1160void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1161void radeon_uvd_free_handles(struct radeon_device *rdev,
1162 struct drm_file *filp);
1163int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1164void radeon_uvd_note_usage(struct radeon_device *rdev);
1165int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1166 unsigned vclk, unsigned dclk,
1167 unsigned vco_min, unsigned vco_max,
1168 unsigned fb_factor, unsigned fb_mask,
1169 unsigned pd_min, unsigned pd_max,
1170 unsigned pd_even,
1171 unsigned *optimal_fb_div,
1172 unsigned *optimal_vclk_div,
1173 unsigned *optimal_dclk_div);
1174int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1175 unsigned cg_upll_func_cntl);
1121 1176
1122struct r600_audio { 1177struct r600_audio {
1123 int channels; 1178 int channels;
@@ -1229,6 +1284,9 @@ struct radeon_asic {
1229 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1284 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1230 /* get backlight level */ 1285 /* get backlight level */
1231 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1286 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1287 /* audio callbacks */
1288 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1289 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1232 } display; 1290 } display;
1233 /* copy functions for bo handling */ 1291 /* copy functions for bo handling */
1234 struct { 1292 struct {
@@ -1281,6 +1339,7 @@ struct radeon_asic {
1281 int (*get_pcie_lanes)(struct radeon_device *rdev); 1339 int (*get_pcie_lanes)(struct radeon_device *rdev);
1282 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1340 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1283 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1341 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1342 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1284 } pm; 1343 } pm;
1285 /* pageflipping */ 1344 /* pageflipping */
1286 struct { 1345 struct {
@@ -1443,6 +1502,7 @@ struct si_asic {
1443 unsigned multi_gpu_tile_size; 1502 unsigned multi_gpu_tile_size;
1444 1503
1445 unsigned tile_config; 1504 unsigned tile_config;
1505 uint32_t tile_mode_array[32];
1446}; 1506};
1447 1507
1448union radeon_asic_config { 1508union radeon_asic_config {
@@ -1608,6 +1668,7 @@ struct radeon_device {
1608 struct radeon_asic *asic; 1668 struct radeon_asic *asic;
1609 struct radeon_gem gem; 1669 struct radeon_gem gem;
1610 struct radeon_pm pm; 1670 struct radeon_pm pm;
1671 struct radeon_uvd uvd;
1611 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1672 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1612 struct radeon_wb wb; 1673 struct radeon_wb wb;
1613 struct radeon_dummy_page dummy_page; 1674 struct radeon_dummy_page dummy_page;
@@ -1615,12 +1676,14 @@ struct radeon_device {
1615 bool suspend; 1676 bool suspend;
1616 bool need_dma32; 1677 bool need_dma32;
1617 bool accel_working; 1678 bool accel_working;
1679 bool fastfb_working; /* IGP feature*/
1618 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1680 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1619 const struct firmware *me_fw; /* all family ME firmware */ 1681 const struct firmware *me_fw; /* all family ME firmware */
1620 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1682 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1621 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1683 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1622 const struct firmware *mc_fw; /* NI MC firmware */ 1684 const struct firmware *mc_fw; /* NI MC firmware */
1623 const struct firmware *ce_fw; /* SI CE firmware */ 1685 const struct firmware *ce_fw; /* SI CE firmware */
1686 const struct firmware *uvd_fw; /* UVD firmware */
1624 struct r600_blit r600_blit; 1687 struct r600_blit r600_blit;
1625 struct r600_vram_scratch vram_scratch; 1688 struct r600_vram_scratch vram_scratch;
1626 int msi_enabled; /* msi enabled */ 1689 int msi_enabled; /* msi enabled */
@@ -1688,8 +1751,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1688#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1751#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1689#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1752#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1690#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1753#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1691#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1754#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
1692#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1755#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1693#define WREG32_P(reg, val, mask) \ 1756#define WREG32_P(reg, val, mask) \
1694 do { \ 1757 do { \
1695 uint32_t tmp_ = RREG32(reg); \ 1758 uint32_t tmp_ = RREG32(reg); \
@@ -1697,6 +1760,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1697 tmp_ |= ((val) & ~(mask)); \ 1760 tmp_ |= ((val) & ~(mask)); \
1698 WREG32(reg, tmp_); \ 1761 WREG32(reg, tmp_); \
1699 } while (0) 1762 } while (0)
1763#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1764#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
1700#define WREG32_PLL_P(reg, val, mask) \ 1765#define WREG32_PLL_P(reg, val, mask) \
1701 do { \ 1766 do { \
1702 uint32_t tmp_ = RREG32_PLL(reg); \ 1767 uint32_t tmp_ = RREG32_PLL(reg); \
@@ -1830,6 +1895,8 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1830#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1895#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1831#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 1896#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1832#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 1897#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1898#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
1899#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
1833#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1900#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1834#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1901#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1835#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1902#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
@@ -1845,6 +1912,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1845#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1912#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1846#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1913#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1847#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1914#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1915#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
1848#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1916#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1849#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1917#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1850#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1918#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
@@ -1892,6 +1960,9 @@ extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc
1892extern int radeon_resume_kms(struct drm_device *dev); 1960extern int radeon_resume_kms(struct drm_device *dev);
1893extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 1961extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1894extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1962extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1963extern void radeon_program_register_sequence(struct radeon_device *rdev,
1964 const u32 *registers,
1965 const u32 array_size);
1895 1966
1896/* 1967/*
1897 * vm 1968 * vm
@@ -1964,9 +2035,6 @@ struct radeon_hdmi_acr {
1964 2035
1965extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2036extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1966 2037
1967extern void r600_hdmi_enable(struct drm_encoder *encoder);
1968extern void r600_hdmi_disable(struct drm_encoder *encoder);
1969extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1970extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2038extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1971 u32 tiling_pipe_num, 2039 u32 tiling_pipe_num,
1972 u32 max_rb_num, 2040 u32 max_rb_num,
@@ -1977,8 +2045,6 @@ extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1977 * evergreen functions used by radeon_encoder.c 2045 * evergreen functions used by radeon_encoder.c
1978 */ 2046 */
1979 2047
1980extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1981
1982extern int ni_init_microcode(struct radeon_device *rdev); 2048extern int ni_init_microcode(struct radeon_device *rdev);
1983extern int ni_mc_load_microcode(struct radeon_device *rdev); 2049extern int ni_mc_load_microcode(struct radeon_device *rdev);
1984 2050
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index aba0a893ea98..6417132c50cf 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -656,6 +656,8 @@ static struct radeon_asic rs600_asic = {
656 .wait_for_vblank = &avivo_wait_for_vblank, 656 .wait_for_vblank = &avivo_wait_for_vblank,
657 .set_backlight_level = &atombios_set_backlight_level, 657 .set_backlight_level = &atombios_set_backlight_level,
658 .get_backlight_level = &atombios_get_backlight_level, 658 .get_backlight_level = &atombios_get_backlight_level,
659 .hdmi_enable = &r600_hdmi_enable,
660 .hdmi_setmode = &r600_hdmi_setmode,
659 }, 661 },
660 .copy = { 662 .copy = {
661 .blit = &r100_copy_blit, 663 .blit = &r100_copy_blit,
@@ -732,6 +734,8 @@ static struct radeon_asic rs690_asic = {
732 .wait_for_vblank = &avivo_wait_for_vblank, 734 .wait_for_vblank = &avivo_wait_for_vblank,
733 .set_backlight_level = &atombios_set_backlight_level, 735 .set_backlight_level = &atombios_set_backlight_level,
734 .get_backlight_level = &atombios_get_backlight_level, 736 .get_backlight_level = &atombios_get_backlight_level,
737 .hdmi_enable = &r600_hdmi_enable,
738 .hdmi_setmode = &r600_hdmi_setmode,
735 }, 739 },
736 .copy = { 740 .copy = {
737 .blit = &r100_copy_blit, 741 .blit = &r100_copy_blit,
@@ -970,6 +974,8 @@ static struct radeon_asic r600_asic = {
970 .wait_for_vblank = &avivo_wait_for_vblank, 974 .wait_for_vblank = &avivo_wait_for_vblank,
971 .set_backlight_level = &atombios_set_backlight_level, 975 .set_backlight_level = &atombios_set_backlight_level,
972 .get_backlight_level = &atombios_get_backlight_level, 976 .get_backlight_level = &atombios_get_backlight_level,
977 .hdmi_enable = &r600_hdmi_enable,
978 .hdmi_setmode = &r600_hdmi_setmode,
973 }, 979 },
974 .copy = { 980 .copy = {
975 .blit = &r600_copy_blit, 981 .blit = &r600_copy_blit,
@@ -1056,6 +1062,8 @@ static struct radeon_asic rs780_asic = {
1056 .wait_for_vblank = &avivo_wait_for_vblank, 1062 .wait_for_vblank = &avivo_wait_for_vblank,
1057 .set_backlight_level = &atombios_set_backlight_level, 1063 .set_backlight_level = &atombios_set_backlight_level,
1058 .get_backlight_level = &atombios_get_backlight_level, 1064 .get_backlight_level = &atombios_get_backlight_level,
1065 .hdmi_enable = &r600_hdmi_enable,
1066 .hdmi_setmode = &r600_hdmi_setmode,
1059 }, 1067 },
1060 .copy = { 1068 .copy = {
1061 .blit = &r600_copy_blit, 1069 .blit = &r600_copy_blit,
@@ -1130,6 +1138,15 @@ static struct radeon_asic rv770_asic = {
1130 .ring_test = &r600_dma_ring_test, 1138 .ring_test = &r600_dma_ring_test,
1131 .ib_test = &r600_dma_ib_test, 1139 .ib_test = &r600_dma_ib_test,
1132 .is_lockup = &r600_dma_is_lockup, 1140 .is_lockup = &r600_dma_is_lockup,
1141 },
1142 [R600_RING_TYPE_UVD_INDEX] = {
1143 .ib_execute = &r600_uvd_ib_execute,
1144 .emit_fence = &r600_uvd_fence_emit,
1145 .emit_semaphore = &r600_uvd_semaphore_emit,
1146 .cs_parse = &radeon_uvd_cs_parse,
1147 .ring_test = &r600_uvd_ring_test,
1148 .ib_test = &r600_uvd_ib_test,
1149 .is_lockup = &radeon_ring_test_lockup,
1133 } 1150 }
1134 }, 1151 },
1135 .irq = { 1152 .irq = {
@@ -1142,6 +1159,8 @@ static struct radeon_asic rv770_asic = {
1142 .wait_for_vblank = &avivo_wait_for_vblank, 1159 .wait_for_vblank = &avivo_wait_for_vblank,
1143 .set_backlight_level = &atombios_set_backlight_level, 1160 .set_backlight_level = &atombios_set_backlight_level,
1144 .get_backlight_level = &atombios_get_backlight_level, 1161 .get_backlight_level = &atombios_get_backlight_level,
1162 .hdmi_enable = &r600_hdmi_enable,
1163 .hdmi_setmode = &r600_hdmi_setmode,
1145 }, 1164 },
1146 .copy = { 1165 .copy = {
1147 .blit = &r600_copy_blit, 1166 .blit = &r600_copy_blit,
@@ -1174,6 +1193,7 @@ static struct radeon_asic rv770_asic = {
1174 .get_pcie_lanes = &r600_get_pcie_lanes, 1193 .get_pcie_lanes = &r600_get_pcie_lanes,
1175 .set_pcie_lanes = &r600_set_pcie_lanes, 1194 .set_pcie_lanes = &r600_set_pcie_lanes,
1176 .set_clock_gating = &radeon_atom_set_clock_gating, 1195 .set_clock_gating = &radeon_atom_set_clock_gating,
1196 .set_uvd_clocks = &rv770_set_uvd_clocks,
1177 }, 1197 },
1178 .pflip = { 1198 .pflip = {
1179 .pre_page_flip = &rs600_pre_page_flip, 1199 .pre_page_flip = &rs600_pre_page_flip,
@@ -1216,6 +1236,15 @@ static struct radeon_asic evergreen_asic = {
1216 .ring_test = &r600_dma_ring_test, 1236 .ring_test = &r600_dma_ring_test,
1217 .ib_test = &r600_dma_ib_test, 1237 .ib_test = &r600_dma_ib_test,
1218 .is_lockup = &evergreen_dma_is_lockup, 1238 .is_lockup = &evergreen_dma_is_lockup,
1239 },
1240 [R600_RING_TYPE_UVD_INDEX] = {
1241 .ib_execute = &r600_uvd_ib_execute,
1242 .emit_fence = &r600_uvd_fence_emit,
1243 .emit_semaphore = &r600_uvd_semaphore_emit,
1244 .cs_parse = &radeon_uvd_cs_parse,
1245 .ring_test = &r600_uvd_ring_test,
1246 .ib_test = &r600_uvd_ib_test,
1247 .is_lockup = &radeon_ring_test_lockup,
1219 } 1248 }
1220 }, 1249 },
1221 .irq = { 1250 .irq = {
@@ -1228,6 +1257,8 @@ static struct radeon_asic evergreen_asic = {
1228 .wait_for_vblank = &dce4_wait_for_vblank, 1257 .wait_for_vblank = &dce4_wait_for_vblank,
1229 .set_backlight_level = &atombios_set_backlight_level, 1258 .set_backlight_level = &atombios_set_backlight_level,
1230 .get_backlight_level = &atombios_get_backlight_level, 1259 .get_backlight_level = &atombios_get_backlight_level,
1260 .hdmi_enable = &evergreen_hdmi_enable,
1261 .hdmi_setmode = &evergreen_hdmi_setmode,
1231 }, 1262 },
1232 .copy = { 1263 .copy = {
1233 .blit = &r600_copy_blit, 1264 .blit = &r600_copy_blit,
@@ -1260,6 +1291,7 @@ static struct radeon_asic evergreen_asic = {
1260 .get_pcie_lanes = &r600_get_pcie_lanes, 1291 .get_pcie_lanes = &r600_get_pcie_lanes,
1261 .set_pcie_lanes = &r600_set_pcie_lanes, 1292 .set_pcie_lanes = &r600_set_pcie_lanes,
1262 .set_clock_gating = NULL, 1293 .set_clock_gating = NULL,
1294 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1263 }, 1295 },
1264 .pflip = { 1296 .pflip = {
1265 .pre_page_flip = &evergreen_pre_page_flip, 1297 .pre_page_flip = &evergreen_pre_page_flip,
@@ -1302,6 +1334,15 @@ static struct radeon_asic sumo_asic = {
1302 .ring_test = &r600_dma_ring_test, 1334 .ring_test = &r600_dma_ring_test,
1303 .ib_test = &r600_dma_ib_test, 1335 .ib_test = &r600_dma_ib_test,
1304 .is_lockup = &evergreen_dma_is_lockup, 1336 .is_lockup = &evergreen_dma_is_lockup,
1337 },
1338 [R600_RING_TYPE_UVD_INDEX] = {
1339 .ib_execute = &r600_uvd_ib_execute,
1340 .emit_fence = &r600_uvd_fence_emit,
1341 .emit_semaphore = &r600_uvd_semaphore_emit,
1342 .cs_parse = &radeon_uvd_cs_parse,
1343 .ring_test = &r600_uvd_ring_test,
1344 .ib_test = &r600_uvd_ib_test,
1345 .is_lockup = &radeon_ring_test_lockup,
1305 } 1346 }
1306 }, 1347 },
1307 .irq = { 1348 .irq = {
@@ -1314,6 +1355,8 @@ static struct radeon_asic sumo_asic = {
1314 .wait_for_vblank = &dce4_wait_for_vblank, 1355 .wait_for_vblank = &dce4_wait_for_vblank,
1315 .set_backlight_level = &atombios_set_backlight_level, 1356 .set_backlight_level = &atombios_set_backlight_level,
1316 .get_backlight_level = &atombios_get_backlight_level, 1357 .get_backlight_level = &atombios_get_backlight_level,
1358 .hdmi_enable = &evergreen_hdmi_enable,
1359 .hdmi_setmode = &evergreen_hdmi_setmode,
1317 }, 1360 },
1318 .copy = { 1361 .copy = {
1319 .blit = &r600_copy_blit, 1362 .blit = &r600_copy_blit,
@@ -1346,6 +1389,7 @@ static struct radeon_asic sumo_asic = {
1346 .get_pcie_lanes = NULL, 1389 .get_pcie_lanes = NULL,
1347 .set_pcie_lanes = NULL, 1390 .set_pcie_lanes = NULL,
1348 .set_clock_gating = NULL, 1391 .set_clock_gating = NULL,
1392 .set_uvd_clocks = &sumo_set_uvd_clocks,
1349 }, 1393 },
1350 .pflip = { 1394 .pflip = {
1351 .pre_page_flip = &evergreen_pre_page_flip, 1395 .pre_page_flip = &evergreen_pre_page_flip,
@@ -1388,6 +1432,15 @@ static struct radeon_asic btc_asic = {
1388 .ring_test = &r600_dma_ring_test, 1432 .ring_test = &r600_dma_ring_test,
1389 .ib_test = &r600_dma_ib_test, 1433 .ib_test = &r600_dma_ib_test,
1390 .is_lockup = &evergreen_dma_is_lockup, 1434 .is_lockup = &evergreen_dma_is_lockup,
1435 },
1436 [R600_RING_TYPE_UVD_INDEX] = {
1437 .ib_execute = &r600_uvd_ib_execute,
1438 .emit_fence = &r600_uvd_fence_emit,
1439 .emit_semaphore = &r600_uvd_semaphore_emit,
1440 .cs_parse = &radeon_uvd_cs_parse,
1441 .ring_test = &r600_uvd_ring_test,
1442 .ib_test = &r600_uvd_ib_test,
1443 .is_lockup = &radeon_ring_test_lockup,
1391 } 1444 }
1392 }, 1445 },
1393 .irq = { 1446 .irq = {
@@ -1400,6 +1453,8 @@ static struct radeon_asic btc_asic = {
1400 .wait_for_vblank = &dce4_wait_for_vblank, 1453 .wait_for_vblank = &dce4_wait_for_vblank,
1401 .set_backlight_level = &atombios_set_backlight_level, 1454 .set_backlight_level = &atombios_set_backlight_level,
1402 .get_backlight_level = &atombios_get_backlight_level, 1455 .get_backlight_level = &atombios_get_backlight_level,
1456 .hdmi_enable = &evergreen_hdmi_enable,
1457 .hdmi_setmode = &evergreen_hdmi_setmode,
1403 }, 1458 },
1404 .copy = { 1459 .copy = {
1405 .blit = &r600_copy_blit, 1460 .blit = &r600_copy_blit,
@@ -1429,9 +1484,10 @@ static struct radeon_asic btc_asic = {
1429 .set_engine_clock = &radeon_atom_set_engine_clock, 1484 .set_engine_clock = &radeon_atom_set_engine_clock,
1430 .get_memory_clock = &radeon_atom_get_memory_clock, 1485 .get_memory_clock = &radeon_atom_get_memory_clock,
1431 .set_memory_clock = &radeon_atom_set_memory_clock, 1486 .set_memory_clock = &radeon_atom_set_memory_clock,
1432 .get_pcie_lanes = NULL, 1487 .get_pcie_lanes = &r600_get_pcie_lanes,
1433 .set_pcie_lanes = NULL, 1488 .set_pcie_lanes = &r600_set_pcie_lanes,
1434 .set_clock_gating = NULL, 1489 .set_clock_gating = NULL,
1490 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1435 }, 1491 },
1436 .pflip = { 1492 .pflip = {
1437 .pre_page_flip = &evergreen_pre_page_flip, 1493 .pre_page_flip = &evergreen_pre_page_flip,
@@ -1517,6 +1573,15 @@ static struct radeon_asic cayman_asic = {
1517 .ib_test = &r600_dma_ib_test, 1573 .ib_test = &r600_dma_ib_test,
1518 .is_lockup = &cayman_dma_is_lockup, 1574 .is_lockup = &cayman_dma_is_lockup,
1519 .vm_flush = &cayman_dma_vm_flush, 1575 .vm_flush = &cayman_dma_vm_flush,
1576 },
1577 [R600_RING_TYPE_UVD_INDEX] = {
1578 .ib_execute = &r600_uvd_ib_execute,
1579 .emit_fence = &r600_uvd_fence_emit,
1580 .emit_semaphore = &cayman_uvd_semaphore_emit,
1581 .cs_parse = &radeon_uvd_cs_parse,
1582 .ring_test = &r600_uvd_ring_test,
1583 .ib_test = &r600_uvd_ib_test,
1584 .is_lockup = &radeon_ring_test_lockup,
1520 } 1585 }
1521 }, 1586 },
1522 .irq = { 1587 .irq = {
@@ -1529,6 +1594,8 @@ static struct radeon_asic cayman_asic = {
1529 .wait_for_vblank = &dce4_wait_for_vblank, 1594 .wait_for_vblank = &dce4_wait_for_vblank,
1530 .set_backlight_level = &atombios_set_backlight_level, 1595 .set_backlight_level = &atombios_set_backlight_level,
1531 .get_backlight_level = &atombios_get_backlight_level, 1596 .get_backlight_level = &atombios_get_backlight_level,
1597 .hdmi_enable = &evergreen_hdmi_enable,
1598 .hdmi_setmode = &evergreen_hdmi_setmode,
1532 }, 1599 },
1533 .copy = { 1600 .copy = {
1534 .blit = &r600_copy_blit, 1601 .blit = &r600_copy_blit,
@@ -1558,9 +1625,10 @@ static struct radeon_asic cayman_asic = {
1558 .set_engine_clock = &radeon_atom_set_engine_clock, 1625 .set_engine_clock = &radeon_atom_set_engine_clock,
1559 .get_memory_clock = &radeon_atom_get_memory_clock, 1626 .get_memory_clock = &radeon_atom_get_memory_clock,
1560 .set_memory_clock = &radeon_atom_set_memory_clock, 1627 .set_memory_clock = &radeon_atom_set_memory_clock,
1561 .get_pcie_lanes = NULL, 1628 .get_pcie_lanes = &r600_get_pcie_lanes,
1562 .set_pcie_lanes = NULL, 1629 .set_pcie_lanes = &r600_set_pcie_lanes,
1563 .set_clock_gating = NULL, 1630 .set_clock_gating = NULL,
1631 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1564 }, 1632 },
1565 .pflip = { 1633 .pflip = {
1566 .pre_page_flip = &evergreen_pre_page_flip, 1634 .pre_page_flip = &evergreen_pre_page_flip,
@@ -1646,6 +1714,15 @@ static struct radeon_asic trinity_asic = {
1646 .ib_test = &r600_dma_ib_test, 1714 .ib_test = &r600_dma_ib_test,
1647 .is_lockup = &cayman_dma_is_lockup, 1715 .is_lockup = &cayman_dma_is_lockup,
1648 .vm_flush = &cayman_dma_vm_flush, 1716 .vm_flush = &cayman_dma_vm_flush,
1717 },
1718 [R600_RING_TYPE_UVD_INDEX] = {
1719 .ib_execute = &r600_uvd_ib_execute,
1720 .emit_fence = &r600_uvd_fence_emit,
1721 .emit_semaphore = &cayman_uvd_semaphore_emit,
1722 .cs_parse = &radeon_uvd_cs_parse,
1723 .ring_test = &r600_uvd_ring_test,
1724 .ib_test = &r600_uvd_ib_test,
1725 .is_lockup = &radeon_ring_test_lockup,
1649 } 1726 }
1650 }, 1727 },
1651 .irq = { 1728 .irq = {
@@ -1690,6 +1767,7 @@ static struct radeon_asic trinity_asic = {
1690 .get_pcie_lanes = NULL, 1767 .get_pcie_lanes = NULL,
1691 .set_pcie_lanes = NULL, 1768 .set_pcie_lanes = NULL,
1692 .set_clock_gating = NULL, 1769 .set_clock_gating = NULL,
1770 .set_uvd_clocks = &sumo_set_uvd_clocks,
1693 }, 1771 },
1694 .pflip = { 1772 .pflip = {
1695 .pre_page_flip = &evergreen_pre_page_flip, 1773 .pre_page_flip = &evergreen_pre_page_flip,
@@ -1775,6 +1853,15 @@ static struct radeon_asic si_asic = {
1775 .ib_test = &r600_dma_ib_test, 1853 .ib_test = &r600_dma_ib_test,
1776 .is_lockup = &si_dma_is_lockup, 1854 .is_lockup = &si_dma_is_lockup,
1777 .vm_flush = &si_dma_vm_flush, 1855 .vm_flush = &si_dma_vm_flush,
1856 },
1857 [R600_RING_TYPE_UVD_INDEX] = {
1858 .ib_execute = &r600_uvd_ib_execute,
1859 .emit_fence = &r600_uvd_fence_emit,
1860 .emit_semaphore = &cayman_uvd_semaphore_emit,
1861 .cs_parse = &radeon_uvd_cs_parse,
1862 .ring_test = &r600_uvd_ring_test,
1863 .ib_test = &r600_uvd_ib_test,
1864 .is_lockup = &radeon_ring_test_lockup,
1778 } 1865 }
1779 }, 1866 },
1780 .irq = { 1867 .irq = {
@@ -1816,9 +1903,10 @@ static struct radeon_asic si_asic = {
1816 .set_engine_clock = &radeon_atom_set_engine_clock, 1903 .set_engine_clock = &radeon_atom_set_engine_clock,
1817 .get_memory_clock = &radeon_atom_get_memory_clock, 1904 .get_memory_clock = &radeon_atom_get_memory_clock,
1818 .set_memory_clock = &radeon_atom_set_memory_clock, 1905 .set_memory_clock = &radeon_atom_set_memory_clock,
1819 .get_pcie_lanes = NULL, 1906 .get_pcie_lanes = &r600_get_pcie_lanes,
1820 .set_pcie_lanes = NULL, 1907 .set_pcie_lanes = &r600_set_pcie_lanes,
1821 .set_clock_gating = NULL, 1908 .set_clock_gating = NULL,
1909 .set_uvd_clocks = &si_set_uvd_clocks,
1822 }, 1910 },
1823 .pflip = { 1911 .pflip = {
1824 .pre_page_flip = &evergreen_pre_page_flip, 1912 .pre_page_flip = &evergreen_pre_page_flip,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 3535f73ad3e2..2c87365d345f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -330,6 +330,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
330void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 330void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
331int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 331int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
332int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 332int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
333int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
333int r600_copy_blit(struct radeon_device *rdev, 334int r600_copy_blit(struct radeon_device *rdev,
334 uint64_t src_offset, uint64_t dst_offset, 335 uint64_t src_offset, uint64_t dst_offset,
335 unsigned num_gpu_pages, struct radeon_fence **fence); 336 unsigned num_gpu_pages, struct radeon_fence **fence);
@@ -373,11 +374,12 @@ void r600_disable_interrupts(struct radeon_device *rdev);
373void r600_rlc_stop(struct radeon_device *rdev); 374void r600_rlc_stop(struct radeon_device *rdev);
374/* r600 audio */ 375/* r600 audio */
375int r600_audio_init(struct radeon_device *rdev); 376int r600_audio_init(struct radeon_device *rdev);
376void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
377struct r600_audio r600_audio_status(struct radeon_device *rdev); 377struct r600_audio r600_audio_status(struct radeon_device *rdev);
378void r600_audio_fini(struct radeon_device *rdev); 378void r600_audio_fini(struct radeon_device *rdev);
379int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 379int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
380void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 380void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
381void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
382void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
381/* r600 blit */ 383/* r600 blit */
382int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, 384int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
383 struct radeon_fence **fence, struct radeon_sa_bo **vb, 385 struct radeon_fence **fence, struct radeon_sa_bo **vb,
@@ -392,6 +394,19 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
392u32 r600_get_xclk(struct radeon_device *rdev); 394u32 r600_get_xclk(struct radeon_device *rdev);
393uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 395uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
394 396
397/* uvd */
398int r600_uvd_init(struct radeon_device *rdev);
399int r600_uvd_rbc_start(struct radeon_device *rdev);
400void r600_uvd_rbc_stop(struct radeon_device *rdev);
401int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
402void r600_uvd_fence_emit(struct radeon_device *rdev,
403 struct radeon_fence *fence);
404void r600_uvd_semaphore_emit(struct radeon_device *rdev,
405 struct radeon_ring *ring,
406 struct radeon_semaphore *semaphore,
407 bool emit_wait);
408void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
409
395/* 410/*
396 * rv770,rv730,rv710,rv740 411 * rv770,rv730,rv710,rv740
397 */ 412 */
@@ -409,6 +424,8 @@ int rv770_copy_dma(struct radeon_device *rdev,
409 unsigned num_gpu_pages, 424 unsigned num_gpu_pages,
410 struct radeon_fence **fence); 425 struct radeon_fence **fence);
411u32 rv770_get_xclk(struct radeon_device *rdev); 426u32 rv770_get_xclk(struct radeon_device *rdev);
427int rv770_uvd_resume(struct radeon_device *rdev);
428int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
412 429
413/* 430/*
414 * evergreen 431 * evergreen
@@ -444,6 +461,8 @@ extern void evergreen_pm_prepare(struct radeon_device *rdev);
444extern void evergreen_pm_finish(struct radeon_device *rdev); 461extern void evergreen_pm_finish(struct radeon_device *rdev);
445extern void sumo_pm_init_profile(struct radeon_device *rdev); 462extern void sumo_pm_init_profile(struct radeon_device *rdev);
446extern void btc_pm_init_profile(struct radeon_device *rdev); 463extern void btc_pm_init_profile(struct radeon_device *rdev);
464int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
465int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
447extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 466extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
448extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 467extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
449extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 468extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
@@ -459,12 +478,18 @@ int evergreen_copy_dma(struct radeon_device *rdev,
459 uint64_t src_offset, uint64_t dst_offset, 478 uint64_t src_offset, uint64_t dst_offset,
460 unsigned num_gpu_pages, 479 unsigned num_gpu_pages,
461 struct radeon_fence **fence); 480 struct radeon_fence **fence);
481void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
482void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
462 483
463/* 484/*
464 * cayman 485 * cayman
465 */ 486 */
466void cayman_fence_ring_emit(struct radeon_device *rdev, 487void cayman_fence_ring_emit(struct radeon_device *rdev,
467 struct radeon_fence *fence); 488 struct radeon_fence *fence);
489void cayman_uvd_semaphore_emit(struct radeon_device *rdev,
490 struct radeon_ring *ring,
491 struct radeon_semaphore *semaphore,
492 bool emit_wait);
468void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 493void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
469int cayman_init(struct radeon_device *rdev); 494int cayman_init(struct radeon_device *rdev);
470void cayman_fini(struct radeon_device *rdev); 495void cayman_fini(struct radeon_device *rdev);
@@ -524,5 +549,6 @@ int si_copy_dma(struct radeon_device *rdev,
524void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 549void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
525u32 si_get_xclk(struct radeon_device *rdev); 550u32 si_get_xclk(struct radeon_device *rdev);
526uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 551uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
552int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
527 553
528#endif 554#endif
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index f22eb5713528..dea6f63c9724 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2028,6 +2028,8 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2028 num_modes = power_info->info.ucNumOfPowerModeEntries; 2028 num_modes = power_info->info.ucNumOfPowerModeEntries;
2029 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2029 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2030 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2030 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2031 if (num_modes == 0)
2032 return state_index;
2031 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); 2033 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2032 if (!rdev->pm.power_state) 2034 if (!rdev->pm.power_state)
2033 return state_index; 2035 return state_index;
@@ -2307,7 +2309,7 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde
2307 rdev->pm.default_power_state_index = state_index; 2309 rdev->pm.default_power_state_index = state_index;
2308 rdev->pm.power_state[state_index].default_clock_mode = 2310 rdev->pm.power_state[state_index].default_clock_mode =
2309 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2311 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2310 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2312 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2311 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2313 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2312 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2314 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2313 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2315 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
@@ -2345,7 +2347,7 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2345 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2347 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2346 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2348 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2347 } 2349 }
2348 } else if (ASIC_IS_DCE6(rdev)) { 2350 } else if (rdev->family >= CHIP_TAHITI) {
2349 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2351 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2350 sclk |= clock_info->si.ucEngineClockHigh << 16; 2352 sclk |= clock_info->si.ucEngineClockHigh << 16;
2351 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2353 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
@@ -2358,7 +2360,7 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2358 le16_to_cpu(clock_info->si.usVDDC); 2360 le16_to_cpu(clock_info->si.usVDDC);
2359 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2361 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2360 le16_to_cpu(clock_info->si.usVDDCI); 2362 le16_to_cpu(clock_info->si.usVDDCI);
2361 } else if (ASIC_IS_DCE4(rdev)) { 2363 } else if (rdev->family >= CHIP_CEDAR) {
2362 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2364 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2363 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2365 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2364 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2366 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
@@ -2432,6 +2434,8 @@ static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2432 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2434 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2433 2435
2434 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2436 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2437 if (power_info->pplib.ucNumStates == 0)
2438 return state_index;
2435 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2439 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2436 power_info->pplib.ucNumStates, GFP_KERNEL); 2440 power_info->pplib.ucNumStates, GFP_KERNEL);
2437 if (!rdev->pm.power_state) 2441 if (!rdev->pm.power_state)
@@ -2514,6 +2518,7 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2514 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2518 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2515 u16 data_offset; 2519 u16 data_offset;
2516 u8 frev, crev; 2520 u8 frev, crev;
2521 u8 *power_state_offset;
2517 2522
2518 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2523 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2519 &frev, &crev, &data_offset)) 2524 &frev, &crev, &data_offset))
@@ -2530,15 +2535,17 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2530 non_clock_info_array = (struct _NonClockInfoArray *) 2535 non_clock_info_array = (struct _NonClockInfoArray *)
2531 (mode_info->atom_context->bios + data_offset + 2536 (mode_info->atom_context->bios + data_offset +
2532 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2537 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2538 if (state_array->ucNumEntries == 0)
2539 return state_index;
2533 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2540 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2534 state_array->ucNumEntries, GFP_KERNEL); 2541 state_array->ucNumEntries, GFP_KERNEL);
2535 if (!rdev->pm.power_state) 2542 if (!rdev->pm.power_state)
2536 return state_index; 2543 return state_index;
2544 power_state_offset = (u8 *)state_array->states;
2537 for (i = 0; i < state_array->ucNumEntries; i++) { 2545 for (i = 0; i < state_array->ucNumEntries; i++) {
2538 mode_index = 0; 2546 mode_index = 0;
2539 power_state = (union pplib_power_state *)&state_array->states[i]; 2547 power_state = (union pplib_power_state *)power_state_offset;
2540 /* XXX this might be an inagua bug... */ 2548 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2541 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2542 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2549 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2543 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2550 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2544 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2551 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
@@ -2550,9 +2557,6 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2550 if (power_state->v2.ucNumDPMLevels) { 2557 if (power_state->v2.ucNumDPMLevels) {
2551 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2558 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2552 clock_array_index = power_state->v2.clockInfoIndex[j]; 2559 clock_array_index = power_state->v2.clockInfoIndex[j];
2553 /* XXX this might be an inagua bug... */
2554 if (clock_array_index >= clock_info_array->ucNumEntries)
2555 continue;
2556 clock_info = (union pplib_clock_info *) 2560 clock_info = (union pplib_clock_info *)
2557 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2561 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2558 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2562 valid = radeon_atombios_parse_pplib_clock_info(rdev,
@@ -2574,6 +2578,7 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2574 non_clock_info); 2578 non_clock_info);
2575 state_index++; 2579 state_index++;
2576 } 2580 }
2581 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2577 } 2582 }
2578 /* if multiple clock modes, mark the lowest as no display */ 2583 /* if multiple clock modes, mark the lowest as no display */
2579 for (i = 0; i < state_index; i++) { 2584 for (i = 0; i < state_index; i++) {
@@ -2620,7 +2625,9 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2620 default: 2625 default:
2621 break; 2626 break;
2622 } 2627 }
2623 } else { 2628 }
2629
2630 if (state_index == 0) {
2624 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2631 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2625 if (rdev->pm.power_state) { 2632 if (rdev->pm.power_state) {
2626 rdev->pm.power_state[0].clock_info = 2633 rdev->pm.power_state[0].clock_info =
@@ -2654,6 +2661,111 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2654 rdev->pm.current_vddc = 0; 2661 rdev->pm.current_vddc = 0;
2655} 2662}
2656 2663
2664union get_clock_dividers {
2665 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2666 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2667 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2668 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2669 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2670};
2671
2672int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2673 u8 clock_type,
2674 u32 clock,
2675 bool strobe_mode,
2676 struct atom_clock_dividers *dividers)
2677{
2678 union get_clock_dividers args;
2679 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2680 u8 frev, crev;
2681
2682 memset(&args, 0, sizeof(args));
2683 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2684
2685 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2686 return -EINVAL;
2687
2688 switch (crev) {
2689 case 1:
2690 /* r4xx, r5xx */
2691 args.v1.ucAction = clock_type;
2692 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2693
2694 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2695
2696 dividers->post_div = args.v1.ucPostDiv;
2697 dividers->fb_div = args.v1.ucFbDiv;
2698 dividers->enable_post_div = true;
2699 break;
2700 case 2:
2701 case 3:
2702 /* r6xx, r7xx, evergreen, ni */
2703 if (rdev->family <= CHIP_RV770) {
2704 args.v2.ucAction = clock_type;
2705 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2706
2707 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2708
2709 dividers->post_div = args.v2.ucPostDiv;
2710 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2711 dividers->ref_div = args.v2.ucAction;
2712 if (rdev->family == CHIP_RV770) {
2713 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2714 true : false;
2715 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2716 } else
2717 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2718 } else {
2719 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2720 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2721
2722 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2723
2724 dividers->post_div = args.v3.ucPostDiv;
2725 dividers->enable_post_div = (args.v3.ucCntlFlag &
2726 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2727 dividers->enable_dithen = (args.v3.ucCntlFlag &
2728 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2729 dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2730 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2731 dividers->ref_div = args.v3.ucRefDiv;
2732 dividers->vco_mode = (args.v3.ucCntlFlag &
2733 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2734 } else {
2735 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2736 if (strobe_mode)
2737 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2738
2739 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2740
2741 dividers->post_div = args.v5.ucPostDiv;
2742 dividers->enable_post_div = (args.v5.ucCntlFlag &
2743 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2744 dividers->enable_dithen = (args.v5.ucCntlFlag &
2745 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2746 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2747 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2748 dividers->ref_div = args.v5.ucRefDiv;
2749 dividers->vco_mode = (args.v5.ucCntlFlag &
2750 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2751 }
2752 }
2753 break;
2754 case 4:
2755 /* fusion */
2756 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2757
2758 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2759
2760 dividers->post_div = args.v4.ucPostDiv;
2761 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2762 break;
2763 default:
2764 return -EINVAL;
2765 }
2766 return 0;
2767}
2768
2657void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 2769void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2658{ 2770{
2659 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 2771 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 70d38241b083..7e265a58141f 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -63,30 +63,50 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
63 break; 63 break;
64 } 64 }
65 } 65 }
66 if (!duplicate) { 66 if (duplicate) {
67 p->relocs[i].gobj = drm_gem_object_lookup(ddev,
68 p->filp,
69 r->handle);
70 if (p->relocs[i].gobj == NULL) {
71 DRM_ERROR("gem object lookup failed 0x%x\n",
72 r->handle);
73 return -ENOENT;
74 }
75 p->relocs_ptr[i] = &p->relocs[i];
76 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
77 p->relocs[i].lobj.bo = p->relocs[i].robj;
78 p->relocs[i].lobj.wdomain = r->write_domain;
79 p->relocs[i].lobj.rdomain = r->read_domains;
80 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
81 p->relocs[i].handle = r->handle;
82 p->relocs[i].flags = r->flags;
83 radeon_bo_list_add_object(&p->relocs[i].lobj,
84 &p->validated);
85
86 } else
87 p->relocs[i].handle = 0; 67 p->relocs[i].handle = 0;
68 continue;
69 }
70
71 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
72 r->handle);
73 if (p->relocs[i].gobj == NULL) {
74 DRM_ERROR("gem object lookup failed 0x%x\n",
75 r->handle);
76 return -ENOENT;
77 }
78 p->relocs_ptr[i] = &p->relocs[i];
79 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
80 p->relocs[i].lobj.bo = p->relocs[i].robj;
81 p->relocs[i].lobj.written = !!r->write_domain;
82
83 /* the first reloc of an UVD job is the
84 msg and that must be in VRAM */
85 if (p->ring == R600_RING_TYPE_UVD_INDEX && i == 0) {
86 /* TODO: is this still needed for NI+ ? */
87 p->relocs[i].lobj.domain =
88 RADEON_GEM_DOMAIN_VRAM;
89
90 p->relocs[i].lobj.alt_domain =
91 RADEON_GEM_DOMAIN_VRAM;
92
93 } else {
94 uint32_t domain = r->write_domain ?
95 r->write_domain : r->read_domains;
96
97 p->relocs[i].lobj.domain = domain;
98 if (domain == RADEON_GEM_DOMAIN_VRAM)
99 domain |= RADEON_GEM_DOMAIN_GTT;
100 p->relocs[i].lobj.alt_domain = domain;
101 }
102
103 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
104 p->relocs[i].handle = r->handle;
105
106 radeon_bo_list_add_object(&p->relocs[i].lobj,
107 &p->validated);
88 } 108 }
89 return radeon_bo_list_validate(&p->validated); 109 return radeon_bo_list_validate(&p->validated, p->ring);
90} 110}
91 111
92static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) 112static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
@@ -121,6 +141,9 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
121 return -EINVAL; 141 return -EINVAL;
122 } 142 }
123 break; 143 break;
144 case RADEON_CS_RING_UVD:
145 p->ring = R600_RING_TYPE_UVD_INDEX;
146 break;
124 } 147 }
125 return 0; 148 return 0;
126} 149}
@@ -241,15 +264,15 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
241 return -EINVAL; 264 return -EINVAL;
242 } 265 }
243 266
244 /* we only support VM on SI+ */ 267 if (radeon_cs_get_ring(p, ring, priority))
245 if ((p->rdev->family >= CHIP_TAHITI) &&
246 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
247 DRM_ERROR("VM required on SI+!\n");
248 return -EINVAL; 268 return -EINVAL;
249 }
250 269
251 if (radeon_cs_get_ring(p, ring, priority)) 270 /* we only support VM on some SI+ rings */
271 if ((p->rdev->asic->ring[p->ring].cs_parse == NULL) &&
272 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
273 DRM_ERROR("Ring %d requires VM!\n", p->ring);
252 return -EINVAL; 274 return -EINVAL;
275 }
253 } 276 }
254 277
255 /* deal with non-vm */ 278 /* deal with non-vm */
@@ -526,6 +549,10 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
526 r = radeon_cs_handle_lockup(rdev, r); 549 r = radeon_cs_handle_lockup(rdev, r);
527 return r; 550 return r;
528 } 551 }
552
553 if (parser.ring == R600_RING_TYPE_UVD_INDEX)
554 radeon_uvd_note_usage(rdev);
555
529 r = radeon_cs_ib_chunk(rdev, &parser); 556 r = radeon_cs_ib_chunk(rdev, &parser);
530 if (r) { 557 if (r) {
531 goto out; 558 goto out;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 44b8034a400d..a8f608903989 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -98,6 +98,42 @@ static const char radeon_family_name[][16] = {
98}; 98};
99 99
100/** 100/**
101 * radeon_program_register_sequence - program an array of registers.
102 *
103 * @rdev: radeon_device pointer
104 * @registers: pointer to the register array
105 * @array_size: size of the register array
106 *
107 * Programs an array or registers with and and or masks.
108 * This is a helper for setting golden registers.
109 */
110void radeon_program_register_sequence(struct radeon_device *rdev,
111 const u32 *registers,
112 const u32 array_size)
113{
114 u32 tmp, reg, and_mask, or_mask;
115 int i;
116
117 if (array_size % 3)
118 return;
119
120 for (i = 0; i < array_size; i +=3) {
121 reg = registers[i + 0];
122 and_mask = registers[i + 1];
123 or_mask = registers[i + 2];
124
125 if (and_mask == 0xffffffff) {
126 tmp = or_mask;
127 } else {
128 tmp = RREG32(reg);
129 tmp &= ~and_mask;
130 tmp |= or_mask;
131 }
132 WREG32(reg, tmp);
133 }
134}
135
136/**
101 * radeon_surface_init - Clear GPU surface registers. 137 * radeon_surface_init - Clear GPU surface registers.
102 * 138 *
103 * @rdev: radeon_device pointer 139 * @rdev: radeon_device pointer
@@ -359,7 +395,7 @@ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64
359 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 395 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
360 396
361 mc->vram_start = base; 397 mc->vram_start = base;
362 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { 398 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
363 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 399 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
364 mc->real_vram_size = mc->aper_size; 400 mc->real_vram_size = mc->aper_size;
365 mc->mc_vram_size = mc->aper_size; 401 mc->mc_vram_size = mc->aper_size;
@@ -394,7 +430,7 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
394{ 430{
395 u64 size_af, size_bf; 431 u64 size_af, size_bf;
396 432
397 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 433 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
398 size_bf = mc->vram_start & ~mc->gtt_base_align; 434 size_bf = mc->vram_start & ~mc->gtt_base_align;
399 if (size_bf > size_af) { 435 if (size_bf > size_af) {
400 if (mc->gtt_size > size_bf) { 436 if (mc->gtt_size > size_bf) {
@@ -1068,6 +1104,17 @@ int radeon_device_init(struct radeon_device *rdev,
1068 radeon_agp_disable(rdev); 1104 radeon_agp_disable(rdev);
1069 } 1105 }
1070 1106
1107 /* Set the internal MC address mask
1108 * This is the max address of the GPU's
1109 * internal address space.
1110 */
1111 if (rdev->family >= CHIP_CAYMAN)
1112 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1113 else if (rdev->family >= CHIP_CEDAR)
1114 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1115 else
1116 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1117
1071 /* set DMA mask + need_dma32 flags. 1118 /* set DMA mask + need_dma32 flags.
1072 * PCIE - can handle 40-bits. 1119 * PCIE - can handle 40-bits.
1073 * IGP - can handle 40-bits 1120 * IGP - can handle 40-bits
@@ -1131,6 +1178,11 @@ int radeon_device_init(struct radeon_device *rdev,
1131 if (r) 1178 if (r)
1132 DRM_ERROR("ib ring test failed (%d).\n", r); 1179 DRM_ERROR("ib ring test failed (%d).\n", r);
1133 1180
1181 r = radeon_gem_debugfs_init(rdev);
1182 if (r) {
1183 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1184 }
1185
1134 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1186 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1135 /* Acceleration not working on AGP card try again 1187 /* Acceleration not working on AGP card try again
1136 * with fallback to PCI or PCIE GART 1188 * with fallback to PCI or PCIE GART
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 66a7f0fd9620..d33f484ace48 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -71,9 +71,12 @@
71 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 71 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
72 * 2.29.0 - R500 FP16 color clear registers 72 * 2.29.0 - R500 FP16 color clear registers
73 * 2.30.0 - fix for FMASK texturing 73 * 2.30.0 - fix for FMASK texturing
74 * 2.31.0 - Add fastfb support for rs690
75 * 2.32.0 - new info request for rings working
76 * 2.33.0 - Add SI tiling mode array query
74 */ 77 */
75#define KMS_DRIVER_MAJOR 2 78#define KMS_DRIVER_MAJOR 2
76#define KMS_DRIVER_MINOR 30 79#define KMS_DRIVER_MINOR 33
77#define KMS_DRIVER_PATCHLEVEL 0 80#define KMS_DRIVER_PATCHLEVEL 0
78int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 81int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
79int radeon_driver_unload_kms(struct drm_device *dev); 82int radeon_driver_unload_kms(struct drm_device *dev);
@@ -160,6 +163,7 @@ int radeon_hw_i2c = 0;
160int radeon_pcie_gen2 = -1; 163int radeon_pcie_gen2 = -1;
161int radeon_msi = -1; 164int radeon_msi = -1;
162int radeon_lockup_timeout = 10000; 165int radeon_lockup_timeout = 10000;
166int radeon_fastfb = 0;
163 167
164MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 168MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
165module_param_named(no_wb, radeon_no_wb, int, 0444); 169module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -212,6 +216,9 @@ module_param_named(msi, radeon_msi, int, 0444);
212MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 216MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
213module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 217module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
214 218
219MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
220module_param_named(fastfb, radeon_fastfb, int, 0444);
221
215static struct pci_device_id pciidlist[] = { 222static struct pci_device_id pciidlist[] = {
216 radeon_PCI_IDS 223 radeon_PCI_IDS
217}; 224};
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 34356252567a..5b937dfe6f65 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -31,9 +31,9 @@
31#include <linux/seq_file.h> 31#include <linux/seq_file.h>
32#include <linux/atomic.h> 32#include <linux/atomic.h>
33#include <linux/wait.h> 33#include <linux/wait.h>
34#include <linux/list.h>
35#include <linux/kref.h> 34#include <linux/kref.h>
36#include <linux/slab.h> 35#include <linux/slab.h>
36#include <linux/firmware.h>
37#include <drm/drmP.h> 37#include <drm/drmP.h>
38#include "radeon_reg.h" 38#include "radeon_reg.h"
39#include "radeon.h" 39#include "radeon.h"
@@ -768,7 +768,19 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
768 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg); 768 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
769 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) { 769 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
770 rdev->fence_drv[ring].scratch_reg = 0; 770 rdev->fence_drv[ring].scratch_reg = 0;
771 index = R600_WB_EVENT_OFFSET + ring * 4; 771 if (ring != R600_RING_TYPE_UVD_INDEX) {
772 index = R600_WB_EVENT_OFFSET + ring * 4;
773 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
774 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
775 index;
776
777 } else {
778 /* put fence directly behind firmware */
779 index = ALIGN(rdev->uvd_fw->size, 8);
780 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
781 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
782 }
783
772 } else { 784 } else {
773 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg); 785 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
774 if (r) { 786 if (r) {
@@ -778,9 +790,9 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
778 index = RADEON_WB_SCRATCH_OFFSET + 790 index = RADEON_WB_SCRATCH_OFFSET +
779 rdev->fence_drv[ring].scratch_reg - 791 rdev->fence_drv[ring].scratch_reg -
780 rdev->scratch.reg_base; 792 rdev->scratch.reg_base;
793 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
794 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
781 } 795 }
782 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
783 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
784 radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring); 796 radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
785 rdev->fence_drv[ring].initialized = true; 797 rdev->fence_drv[ring].initialized = true;
786 dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n", 798 dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index fe5c1f6b7957..aa796031ab65 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -84,6 +84,7 @@ retry:
84 return r; 84 return r;
85 } 85 }
86 *obj = &robj->gem_base; 86 *obj = &robj->gem_base;
87 robj->pid = task_pid_nr(current);
87 88
88 mutex_lock(&rdev->gem.mutex); 89 mutex_lock(&rdev->gem.mutex);
89 list_add_tail(&robj->list, &rdev->gem.objects); 90 list_add_tail(&robj->list, &rdev->gem.objects);
@@ -575,3 +576,52 @@ int radeon_mode_dumb_destroy(struct drm_file *file_priv,
575{ 576{
576 return drm_gem_handle_delete(file_priv, handle); 577 return drm_gem_handle_delete(file_priv, handle);
577} 578}
579
580#if defined(CONFIG_DEBUG_FS)
581static int radeon_debugfs_gem_info(struct seq_file *m, void *data)
582{
583 struct drm_info_node *node = (struct drm_info_node *)m->private;
584 struct drm_device *dev = node->minor->dev;
585 struct radeon_device *rdev = dev->dev_private;
586 struct radeon_bo *rbo;
587 unsigned i = 0;
588
589 mutex_lock(&rdev->gem.mutex);
590 list_for_each_entry(rbo, &rdev->gem.objects, list) {
591 unsigned domain;
592 const char *placement;
593
594 domain = radeon_mem_type_to_domain(rbo->tbo.mem.mem_type);
595 switch (domain) {
596 case RADEON_GEM_DOMAIN_VRAM:
597 placement = "VRAM";
598 break;
599 case RADEON_GEM_DOMAIN_GTT:
600 placement = " GTT";
601 break;
602 case RADEON_GEM_DOMAIN_CPU:
603 default:
604 placement = " CPU";
605 break;
606 }
607 seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
608 i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20,
609 placement, (unsigned long)rbo->pid);
610 i++;
611 }
612 mutex_unlock(&rdev->gem.mutex);
613 return 0;
614}
615
616static struct drm_info_list radeon_debugfs_gem_list[] = {
617 {"radeon_gem_info", &radeon_debugfs_gem_info, 0, NULL},
618};
619#endif
620
621int radeon_gem_debugfs_init(struct radeon_device *rdev)
622{
623#if defined(CONFIG_DEBUG_FS)
624 return radeon_debugfs_add_files(rdev, radeon_debugfs_gem_list, 1);
625#endif
626 return 0;
627}
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index c75cb2c6ba71..4f2d4f4c1dab 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -50,9 +50,13 @@ int radeon_driver_unload_kms(struct drm_device *dev)
50 50
51 if (rdev == NULL) 51 if (rdev == NULL)
52 return 0; 52 return 0;
53 if (rdev->rmmio == NULL)
54 goto done_free;
53 radeon_acpi_fini(rdev); 55 radeon_acpi_fini(rdev);
54 radeon_modeset_fini(rdev); 56 radeon_modeset_fini(rdev);
55 radeon_device_fini(rdev); 57 radeon_device_fini(rdev);
58
59done_free:
56 kfree(rdev); 60 kfree(rdev);
57 dev->dev_private = NULL; 61 dev->dev_private = NULL;
58 return 0; 62 return 0;
@@ -176,80 +180,65 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
176 struct radeon_device *rdev = dev->dev_private; 180 struct radeon_device *rdev = dev->dev_private;
177 struct drm_radeon_info *info = data; 181 struct drm_radeon_info *info = data;
178 struct radeon_mode_info *minfo = &rdev->mode_info; 182 struct radeon_mode_info *minfo = &rdev->mode_info;
179 uint32_t value, *value_ptr; 183 uint32_t *value, value_tmp, *value_ptr, value_size;
180 uint64_t value64, *value_ptr64; 184 uint64_t value64;
181 struct drm_crtc *crtc; 185 struct drm_crtc *crtc;
182 int i, found; 186 int i, found;
183 187
184 /* TIMESTAMP is a 64-bit value, needs special handling. */
185 if (info->request == RADEON_INFO_TIMESTAMP) {
186 if (rdev->family >= CHIP_R600) {
187 value_ptr64 = (uint64_t*)((unsigned long)info->value);
188 value64 = radeon_get_gpu_clock_counter(rdev);
189
190 if (DRM_COPY_TO_USER(value_ptr64, &value64, sizeof(value64))) {
191 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
192 return -EFAULT;
193 }
194 return 0;
195 } else {
196 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
197 return -EINVAL;
198 }
199 }
200
201 value_ptr = (uint32_t *)((unsigned long)info->value); 188 value_ptr = (uint32_t *)((unsigned long)info->value);
202 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) { 189 value = &value_tmp;
203 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 190 value_size = sizeof(uint32_t);
204 return -EFAULT;
205 }
206 191
207 switch (info->request) { 192 switch (info->request) {
208 case RADEON_INFO_DEVICE_ID: 193 case RADEON_INFO_DEVICE_ID:
209 value = dev->pci_device; 194 *value = dev->pci_device;
210 break; 195 break;
211 case RADEON_INFO_NUM_GB_PIPES: 196 case RADEON_INFO_NUM_GB_PIPES:
212 value = rdev->num_gb_pipes; 197 *value = rdev->num_gb_pipes;
213 break; 198 break;
214 case RADEON_INFO_NUM_Z_PIPES: 199 case RADEON_INFO_NUM_Z_PIPES:
215 value = rdev->num_z_pipes; 200 *value = rdev->num_z_pipes;
216 break; 201 break;
217 case RADEON_INFO_ACCEL_WORKING: 202 case RADEON_INFO_ACCEL_WORKING:
218 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 203 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
219 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 204 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
220 value = false; 205 *value = false;
221 else 206 else
222 value = rdev->accel_working; 207 *value = rdev->accel_working;
223 break; 208 break;
224 case RADEON_INFO_CRTC_FROM_ID: 209 case RADEON_INFO_CRTC_FROM_ID:
210 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
211 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
212 return -EFAULT;
213 }
225 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 214 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
226 crtc = (struct drm_crtc *)minfo->crtcs[i]; 215 crtc = (struct drm_crtc *)minfo->crtcs[i];
227 if (crtc && crtc->base.id == value) { 216 if (crtc && crtc->base.id == *value) {
228 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 217 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
229 value = radeon_crtc->crtc_id; 218 *value = radeon_crtc->crtc_id;
230 found = 1; 219 found = 1;
231 break; 220 break;
232 } 221 }
233 } 222 }
234 if (!found) { 223 if (!found) {
235 DRM_DEBUG_KMS("unknown crtc id %d\n", value); 224 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
236 return -EINVAL; 225 return -EINVAL;
237 } 226 }
238 break; 227 break;
239 case RADEON_INFO_ACCEL_WORKING2: 228 case RADEON_INFO_ACCEL_WORKING2:
240 value = rdev->accel_working; 229 *value = rdev->accel_working;
241 break; 230 break;
242 case RADEON_INFO_TILING_CONFIG: 231 case RADEON_INFO_TILING_CONFIG:
243 if (rdev->family >= CHIP_TAHITI) 232 if (rdev->family >= CHIP_TAHITI)
244 value = rdev->config.si.tile_config; 233 *value = rdev->config.si.tile_config;
245 else if (rdev->family >= CHIP_CAYMAN) 234 else if (rdev->family >= CHIP_CAYMAN)
246 value = rdev->config.cayman.tile_config; 235 *value = rdev->config.cayman.tile_config;
247 else if (rdev->family >= CHIP_CEDAR) 236 else if (rdev->family >= CHIP_CEDAR)
248 value = rdev->config.evergreen.tile_config; 237 *value = rdev->config.evergreen.tile_config;
249 else if (rdev->family >= CHIP_RV770) 238 else if (rdev->family >= CHIP_RV770)
250 value = rdev->config.rv770.tile_config; 239 *value = rdev->config.rv770.tile_config;
251 else if (rdev->family >= CHIP_R600) 240 else if (rdev->family >= CHIP_R600)
252 value = rdev->config.r600.tile_config; 241 *value = rdev->config.r600.tile_config;
253 else { 242 else {
254 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 243 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
255 return -EINVAL; 244 return -EINVAL;
@@ -262,73 +251,81 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
262 * 251 *
263 * When returning, the value is 1 if filp owns hyper-z access, 252 * When returning, the value is 1 if filp owns hyper-z access,
264 * 0 otherwise. */ 253 * 0 otherwise. */
265 if (value >= 2) { 254 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
266 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value); 255 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
256 return -EFAULT;
257 }
258 if (*value >= 2) {
259 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
267 return -EINVAL; 260 return -EINVAL;
268 } 261 }
269 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value); 262 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
270 break; 263 break;
271 case RADEON_INFO_WANT_CMASK: 264 case RADEON_INFO_WANT_CMASK:
272 /* The same logic as Hyper-Z. */ 265 /* The same logic as Hyper-Z. */
273 if (value >= 2) { 266 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
274 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value); 267 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
268 return -EFAULT;
269 }
270 if (*value >= 2) {
271 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
275 return -EINVAL; 272 return -EINVAL;
276 } 273 }
277 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value); 274 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
278 break; 275 break;
279 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 276 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
280 /* return clock value in KHz */ 277 /* return clock value in KHz */
281 if (rdev->asic->get_xclk) 278 if (rdev->asic->get_xclk)
282 value = radeon_get_xclk(rdev) * 10; 279 *value = radeon_get_xclk(rdev) * 10;
283 else 280 else
284 value = rdev->clock.spll.reference_freq * 10; 281 *value = rdev->clock.spll.reference_freq * 10;
285 break; 282 break;
286 case RADEON_INFO_NUM_BACKENDS: 283 case RADEON_INFO_NUM_BACKENDS:
287 if (rdev->family >= CHIP_TAHITI) 284 if (rdev->family >= CHIP_TAHITI)
288 value = rdev->config.si.max_backends_per_se * 285 *value = rdev->config.si.max_backends_per_se *
289 rdev->config.si.max_shader_engines; 286 rdev->config.si.max_shader_engines;
290 else if (rdev->family >= CHIP_CAYMAN) 287 else if (rdev->family >= CHIP_CAYMAN)
291 value = rdev->config.cayman.max_backends_per_se * 288 *value = rdev->config.cayman.max_backends_per_se *
292 rdev->config.cayman.max_shader_engines; 289 rdev->config.cayman.max_shader_engines;
293 else if (rdev->family >= CHIP_CEDAR) 290 else if (rdev->family >= CHIP_CEDAR)
294 value = rdev->config.evergreen.max_backends; 291 *value = rdev->config.evergreen.max_backends;
295 else if (rdev->family >= CHIP_RV770) 292 else if (rdev->family >= CHIP_RV770)
296 value = rdev->config.rv770.max_backends; 293 *value = rdev->config.rv770.max_backends;
297 else if (rdev->family >= CHIP_R600) 294 else if (rdev->family >= CHIP_R600)
298 value = rdev->config.r600.max_backends; 295 *value = rdev->config.r600.max_backends;
299 else { 296 else {
300 return -EINVAL; 297 return -EINVAL;
301 } 298 }
302 break; 299 break;
303 case RADEON_INFO_NUM_TILE_PIPES: 300 case RADEON_INFO_NUM_TILE_PIPES:
304 if (rdev->family >= CHIP_TAHITI) 301 if (rdev->family >= CHIP_TAHITI)
305 value = rdev->config.si.max_tile_pipes; 302 *value = rdev->config.si.max_tile_pipes;
306 else if (rdev->family >= CHIP_CAYMAN) 303 else if (rdev->family >= CHIP_CAYMAN)
307 value = rdev->config.cayman.max_tile_pipes; 304 *value = rdev->config.cayman.max_tile_pipes;
308 else if (rdev->family >= CHIP_CEDAR) 305 else if (rdev->family >= CHIP_CEDAR)
309 value = rdev->config.evergreen.max_tile_pipes; 306 *value = rdev->config.evergreen.max_tile_pipes;
310 else if (rdev->family >= CHIP_RV770) 307 else if (rdev->family >= CHIP_RV770)
311 value = rdev->config.rv770.max_tile_pipes; 308 *value = rdev->config.rv770.max_tile_pipes;
312 else if (rdev->family >= CHIP_R600) 309 else if (rdev->family >= CHIP_R600)
313 value = rdev->config.r600.max_tile_pipes; 310 *value = rdev->config.r600.max_tile_pipes;
314 else { 311 else {
315 return -EINVAL; 312 return -EINVAL;
316 } 313 }
317 break; 314 break;
318 case RADEON_INFO_FUSION_GART_WORKING: 315 case RADEON_INFO_FUSION_GART_WORKING:
319 value = 1; 316 *value = 1;
320 break; 317 break;
321 case RADEON_INFO_BACKEND_MAP: 318 case RADEON_INFO_BACKEND_MAP:
322 if (rdev->family >= CHIP_TAHITI) 319 if (rdev->family >= CHIP_TAHITI)
323 value = rdev->config.si.backend_map; 320 *value = rdev->config.si.backend_map;
324 else if (rdev->family >= CHIP_CAYMAN) 321 else if (rdev->family >= CHIP_CAYMAN)
325 value = rdev->config.cayman.backend_map; 322 *value = rdev->config.cayman.backend_map;
326 else if (rdev->family >= CHIP_CEDAR) 323 else if (rdev->family >= CHIP_CEDAR)
327 value = rdev->config.evergreen.backend_map; 324 *value = rdev->config.evergreen.backend_map;
328 else if (rdev->family >= CHIP_RV770) 325 else if (rdev->family >= CHIP_RV770)
329 value = rdev->config.rv770.backend_map; 326 *value = rdev->config.rv770.backend_map;
330 else if (rdev->family >= CHIP_R600) 327 else if (rdev->family >= CHIP_R600)
331 value = rdev->config.r600.backend_map; 328 *value = rdev->config.r600.backend_map;
332 else { 329 else {
333 return -EINVAL; 330 return -EINVAL;
334 } 331 }
@@ -337,50 +334,91 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
337 /* this is where we report if vm is supported or not */ 334 /* this is where we report if vm is supported or not */
338 if (rdev->family < CHIP_CAYMAN) 335 if (rdev->family < CHIP_CAYMAN)
339 return -EINVAL; 336 return -EINVAL;
340 value = RADEON_VA_RESERVED_SIZE; 337 *value = RADEON_VA_RESERVED_SIZE;
341 break; 338 break;
342 case RADEON_INFO_IB_VM_MAX_SIZE: 339 case RADEON_INFO_IB_VM_MAX_SIZE:
343 /* this is where we report if vm is supported or not */ 340 /* this is where we report if vm is supported or not */
344 if (rdev->family < CHIP_CAYMAN) 341 if (rdev->family < CHIP_CAYMAN)
345 return -EINVAL; 342 return -EINVAL;
346 value = RADEON_IB_VM_MAX_SIZE; 343 *value = RADEON_IB_VM_MAX_SIZE;
347 break; 344 break;
348 case RADEON_INFO_MAX_PIPES: 345 case RADEON_INFO_MAX_PIPES:
349 if (rdev->family >= CHIP_TAHITI) 346 if (rdev->family >= CHIP_TAHITI)
350 value = rdev->config.si.max_cu_per_sh; 347 *value = rdev->config.si.max_cu_per_sh;
351 else if (rdev->family >= CHIP_CAYMAN) 348 else if (rdev->family >= CHIP_CAYMAN)
352 value = rdev->config.cayman.max_pipes_per_simd; 349 *value = rdev->config.cayman.max_pipes_per_simd;
353 else if (rdev->family >= CHIP_CEDAR) 350 else if (rdev->family >= CHIP_CEDAR)
354 value = rdev->config.evergreen.max_pipes; 351 *value = rdev->config.evergreen.max_pipes;
355 else if (rdev->family >= CHIP_RV770) 352 else if (rdev->family >= CHIP_RV770)
356 value = rdev->config.rv770.max_pipes; 353 *value = rdev->config.rv770.max_pipes;
357 else if (rdev->family >= CHIP_R600) 354 else if (rdev->family >= CHIP_R600)
358 value = rdev->config.r600.max_pipes; 355 *value = rdev->config.r600.max_pipes;
359 else { 356 else {
360 return -EINVAL; 357 return -EINVAL;
361 } 358 }
362 break; 359 break;
360 case RADEON_INFO_TIMESTAMP:
361 if (rdev->family < CHIP_R600) {
362 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
363 return -EINVAL;
364 }
365 value = (uint32_t*)&value64;
366 value_size = sizeof(uint64_t);
367 value64 = radeon_get_gpu_clock_counter(rdev);
368 break;
363 case RADEON_INFO_MAX_SE: 369 case RADEON_INFO_MAX_SE:
364 if (rdev->family >= CHIP_TAHITI) 370 if (rdev->family >= CHIP_TAHITI)
365 value = rdev->config.si.max_shader_engines; 371 *value = rdev->config.si.max_shader_engines;
366 else if (rdev->family >= CHIP_CAYMAN) 372 else if (rdev->family >= CHIP_CAYMAN)
367 value = rdev->config.cayman.max_shader_engines; 373 *value = rdev->config.cayman.max_shader_engines;
368 else if (rdev->family >= CHIP_CEDAR) 374 else if (rdev->family >= CHIP_CEDAR)
369 value = rdev->config.evergreen.num_ses; 375 *value = rdev->config.evergreen.num_ses;
370 else 376 else
371 value = 1; 377 *value = 1;
372 break; 378 break;
373 case RADEON_INFO_MAX_SH_PER_SE: 379 case RADEON_INFO_MAX_SH_PER_SE:
374 if (rdev->family >= CHIP_TAHITI) 380 if (rdev->family >= CHIP_TAHITI)
375 value = rdev->config.si.max_sh_per_se; 381 *value = rdev->config.si.max_sh_per_se;
376 else 382 else
377 return -EINVAL; 383 return -EINVAL;
378 break; 384 break;
385 case RADEON_INFO_FASTFB_WORKING:
386 *value = rdev->fastfb_working;
387 break;
388 case RADEON_INFO_RING_WORKING:
389 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
390 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
391 return -EFAULT;
392 }
393 switch (*value) {
394 case RADEON_CS_RING_GFX:
395 case RADEON_CS_RING_COMPUTE:
396 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
397 break;
398 case RADEON_CS_RING_DMA:
399 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
400 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
401 break;
402 case RADEON_CS_RING_UVD:
403 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
404 break;
405 default:
406 return -EINVAL;
407 }
408 break;
409 case RADEON_INFO_SI_TILE_MODE_ARRAY:
410 if (rdev->family < CHIP_TAHITI) {
411 DRM_DEBUG_KMS("tile mode array is si only!\n");
412 return -EINVAL;
413 }
414 value = rdev->config.si.tile_mode_array;
415 value_size = sizeof(uint32_t)*32;
416 break;
379 default: 417 default:
380 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 418 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
381 return -EINVAL; 419 return -EINVAL;
382 } 420 }
383 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { 421 if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) {
384 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 422 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
385 return -EFAULT; 423 return -EFAULT;
386 } 424 }
@@ -513,6 +551,7 @@ void radeon_driver_preclose_kms(struct drm_device *dev,
513 rdev->hyperz_filp = NULL; 551 rdev->hyperz_filp = NULL;
514 if (rdev->cmask_filp == file_priv) 552 if (rdev->cmask_filp == file_priv)
515 rdev->cmask_filp = NULL; 553 rdev->cmask_filp = NULL;
554 radeon_uvd_free_handles(rdev, file_priv);
516} 555}
517 556
518/* 557/*
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 4003f5a68c09..44e579e75fd0 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -492,6 +492,29 @@ struct radeon_framebuffer {
492#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 492#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
493 ((em) == ATOM_ENCODER_MODE_DP_MST)) 493 ((em) == ATOM_ENCODER_MODE_DP_MST))
494 494
495struct atom_clock_dividers {
496 u32 post_div;
497 union {
498 struct {
499#ifdef __BIG_ENDIAN
500 u32 reserved : 6;
501 u32 whole_fb_div : 12;
502 u32 frac_fb_div : 14;
503#else
504 u32 frac_fb_div : 14;
505 u32 whole_fb_div : 12;
506 u32 reserved : 6;
507#endif
508 };
509 u32 fb_div;
510 };
511 u32 ref_div;
512 bool enable_post_div;
513 bool enable_dithen;
514 u32 vco_mode;
515 u32 real_clock;
516};
517
495extern enum radeon_tv_std 518extern enum radeon_tv_std
496radeon_combios_get_tv_info(struct radeon_device *rdev); 519radeon_combios_get_tv_info(struct radeon_device *rdev);
497extern enum radeon_tv_std 520extern enum radeon_tv_std
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index d3aface2d12d..1424ccde2377 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -321,8 +321,10 @@ void radeon_bo_force_delete(struct radeon_device *rdev)
321int radeon_bo_init(struct radeon_device *rdev) 321int radeon_bo_init(struct radeon_device *rdev)
322{ 322{
323 /* Add an MTRR for the VRAM */ 323 /* Add an MTRR for the VRAM */
324 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 324 if (!rdev->fastfb_working) {
325 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
325 MTRR_TYPE_WRCOMB, 1); 326 MTRR_TYPE_WRCOMB, 1);
327 }
326 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 328 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
327 rdev->mc.mc_vram_size >> 20, 329 rdev->mc.mc_vram_size >> 20,
328 (unsigned long long)rdev->mc.aper_size >> 20); 330 (unsigned long long)rdev->mc.aper_size >> 20);
@@ -339,14 +341,14 @@ void radeon_bo_fini(struct radeon_device *rdev)
339void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 341void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
340 struct list_head *head) 342 struct list_head *head)
341{ 343{
342 if (lobj->wdomain) { 344 if (lobj->written) {
343 list_add(&lobj->tv.head, head); 345 list_add(&lobj->tv.head, head);
344 } else { 346 } else {
345 list_add_tail(&lobj->tv.head, head); 347 list_add_tail(&lobj->tv.head, head);
346 } 348 }
347} 349}
348 350
349int radeon_bo_list_validate(struct list_head *head) 351int radeon_bo_list_validate(struct list_head *head, int ring)
350{ 352{
351 struct radeon_bo_list *lobj; 353 struct radeon_bo_list *lobj;
352 struct radeon_bo *bo; 354 struct radeon_bo *bo;
@@ -360,15 +362,17 @@ int radeon_bo_list_validate(struct list_head *head)
360 list_for_each_entry(lobj, head, tv.head) { 362 list_for_each_entry(lobj, head, tv.head) {
361 bo = lobj->bo; 363 bo = lobj->bo;
362 if (!bo->pin_count) { 364 if (!bo->pin_count) {
363 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; 365 domain = lobj->domain;
364 366
365 retry: 367 retry:
366 radeon_ttm_placement_from_domain(bo, domain); 368 radeon_ttm_placement_from_domain(bo, domain);
369 if (ring == R600_RING_TYPE_UVD_INDEX)
370 radeon_uvd_force_into_uvd_segment(bo);
367 r = ttm_bo_validate(&bo->tbo, &bo->placement, 371 r = ttm_bo_validate(&bo->tbo, &bo->placement,
368 true, false); 372 true, false);
369 if (unlikely(r)) { 373 if (unlikely(r)) {
370 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { 374 if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
371 domain |= RADEON_GEM_DOMAIN_GTT; 375 domain = lobj->alt_domain;
372 goto retry; 376 goto retry;
373 } 377 }
374 return r; 378 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 5fc86b03043b..e2cb80a96b51 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -128,7 +128,7 @@ extern int radeon_bo_init(struct radeon_device *rdev);
128extern void radeon_bo_fini(struct radeon_device *rdev); 128extern void radeon_bo_fini(struct radeon_device *rdev);
129extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 129extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
130 struct list_head *head); 130 struct list_head *head);
131extern int radeon_bo_list_validate(struct list_head *head); 131extern int radeon_bo_list_validate(struct list_head *head, int ring);
132extern int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 132extern int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
133 struct vm_area_struct *vma); 133 struct vm_area_struct *vma);
134extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 134extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 338fd6a74e87..788c64cb4b47 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -843,7 +843,11 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
843 struct radeon_device *rdev = dev->dev_private; 843 struct radeon_device *rdev = dev->dev_private;
844 844
845 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 845 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
846 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 846 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
847 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
848 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
849 else
850 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
847 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 851 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
848 if (rdev->asic->pm.get_memory_clock) 852 if (rdev->asic->pm.get_memory_clock)
849 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 853 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 8d58e268ff6d..e17faa7cf732 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -180,7 +180,8 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
180 radeon_semaphore_free(rdev, &ib->semaphore, NULL); 180 radeon_semaphore_free(rdev, &ib->semaphore, NULL);
181 } 181 }
182 /* if we can't remember our last VM flush then flush now! */ 182 /* if we can't remember our last VM flush then flush now! */
183 if (ib->vm && !ib->vm->last_flush) { 183 /* XXX figure out why we have to flush for every IB */
184 if (ib->vm /*&& !ib->vm->last_flush*/) {
184 radeon_ring_vm_flush(rdev, ib->ring, ib->vm); 185 radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
185 } 186 }
186 if (const_ib) { 187 if (const_ib) {
@@ -368,7 +369,7 @@ void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
368{ 369{
369 u32 rptr; 370 u32 rptr;
370 371
371 if (rdev->wb.enabled) 372 if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX])
372 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 373 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
373 else 374 else
374 rptr = RREG32(ring->rptr_reg); 375 rptr = RREG32(ring->rptr_reg);
@@ -821,18 +822,20 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
821 return 0; 822 return 0;
822} 823}
823 824
824static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; 825static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
825static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; 826static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
826static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; 827static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
827static int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX; 828static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
828static int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; 829static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
830static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
829 831
830static struct drm_info_list radeon_debugfs_ring_info_list[] = { 832static struct drm_info_list radeon_debugfs_ring_info_list[] = {
831 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, 833 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
832 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, 834 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
833 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, 835 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
834 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index}, 836 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
835 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index}, 837 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
838 {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
836}; 839};
837 840
838static int radeon_debugfs_sa_info(struct seq_file *m, void *data) 841static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c
index cb800995d4f9..0abe5a9431bb 100644
--- a/drivers/gpu/drm/radeon/radeon_sa.c
+++ b/drivers/gpu/drm/radeon/radeon_sa.c
@@ -64,7 +64,7 @@ int radeon_sa_bo_manager_init(struct radeon_device *rdev,
64 } 64 }
65 65
66 r = radeon_bo_create(rdev, size, RADEON_GPU_PAGE_SIZE, true, 66 r = radeon_bo_create(rdev, size, RADEON_GPU_PAGE_SIZE, true,
67 RADEON_GEM_DOMAIN_CPU, NULL, &sa_manager->bo); 67 domain, NULL, &sa_manager->bo);
68 if (r) { 68 if (r) {
69 dev_err(rdev->dev, "(%d) failed to allocate bo for manager\n", r); 69 dev_err(rdev->dev, "(%d) failed to allocate bo for manager\n", r);
70 return r; 70 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index fda09c9ea689..bbed4af8d0bc 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -252,6 +252,36 @@ void radeon_test_moves(struct radeon_device *rdev)
252 radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT); 252 radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT);
253} 253}
254 254
255static int radeon_test_create_and_emit_fence(struct radeon_device *rdev,
256 struct radeon_ring *ring,
257 struct radeon_fence **fence)
258{
259 int r;
260
261 if (ring->idx == R600_RING_TYPE_UVD_INDEX) {
262 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
263 if (r) {
264 DRM_ERROR("Failed to get dummy create msg\n");
265 return r;
266 }
267
268 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, fence);
269 if (r) {
270 DRM_ERROR("Failed to get dummy destroy msg\n");
271 return r;
272 }
273 } else {
274 r = radeon_ring_lock(rdev, ring, 64);
275 if (r) {
276 DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
277 return r;
278 }
279 radeon_fence_emit(rdev, fence, ring->idx);
280 radeon_ring_unlock_commit(rdev, ring);
281 }
282 return 0;
283}
284
255void radeon_test_ring_sync(struct radeon_device *rdev, 285void radeon_test_ring_sync(struct radeon_device *rdev,
256 struct radeon_ring *ringA, 286 struct radeon_ring *ringA,
257 struct radeon_ring *ringB) 287 struct radeon_ring *ringB)
@@ -272,21 +302,24 @@ void radeon_test_ring_sync(struct radeon_device *rdev,
272 goto out_cleanup; 302 goto out_cleanup;
273 } 303 }
274 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); 304 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
275 r = radeon_fence_emit(rdev, &fence1, ringA->idx); 305 radeon_ring_unlock_commit(rdev, ringA);
276 if (r) { 306
277 DRM_ERROR("Failed to emit fence 1\n"); 307 r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1);
278 radeon_ring_unlock_undo(rdev, ringA); 308 if (r)
279 goto out_cleanup; 309 goto out_cleanup;
280 } 310
281 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); 311 r = radeon_ring_lock(rdev, ringA, 64);
282 r = radeon_fence_emit(rdev, &fence2, ringA->idx);
283 if (r) { 312 if (r) {
284 DRM_ERROR("Failed to emit fence 2\n"); 313 DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
285 radeon_ring_unlock_undo(rdev, ringA);
286 goto out_cleanup; 314 goto out_cleanup;
287 } 315 }
316 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
288 radeon_ring_unlock_commit(rdev, ringA); 317 radeon_ring_unlock_commit(rdev, ringA);
289 318
319 r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2);
320 if (r)
321 goto out_cleanup;
322
290 mdelay(1000); 323 mdelay(1000);
291 324
292 if (radeon_fence_signaled(fence1)) { 325 if (radeon_fence_signaled(fence1)) {
@@ -364,27 +397,22 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev,
364 goto out_cleanup; 397 goto out_cleanup;
365 } 398 }
366 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore); 399 radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
367 r = radeon_fence_emit(rdev, &fenceA, ringA->idx);
368 if (r) {
369 DRM_ERROR("Failed to emit sync fence 1\n");
370 radeon_ring_unlock_undo(rdev, ringA);
371 goto out_cleanup;
372 }
373 radeon_ring_unlock_commit(rdev, ringA); 400 radeon_ring_unlock_commit(rdev, ringA);
374 401
402 r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA);
403 if (r)
404 goto out_cleanup;
405
375 r = radeon_ring_lock(rdev, ringB, 64); 406 r = radeon_ring_lock(rdev, ringB, 64);
376 if (r) { 407 if (r) {
377 DRM_ERROR("Failed to lock ring B %d\n", ringB->idx); 408 DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
378 goto out_cleanup; 409 goto out_cleanup;
379 } 410 }
380 radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore); 411 radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore);
381 r = radeon_fence_emit(rdev, &fenceB, ringB->idx);
382 if (r) {
383 DRM_ERROR("Failed to create sync fence 2\n");
384 radeon_ring_unlock_undo(rdev, ringB);
385 goto out_cleanup;
386 }
387 radeon_ring_unlock_commit(rdev, ringB); 412 radeon_ring_unlock_commit(rdev, ringB);
413 r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB);
414 if (r)
415 goto out_cleanup;
388 416
389 mdelay(1000); 417 mdelay(1000);
390 418
@@ -393,7 +421,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev,
393 goto out_cleanup; 421 goto out_cleanup;
394 } 422 }
395 if (radeon_fence_signaled(fenceB)) { 423 if (radeon_fence_signaled(fenceB)) {
396 DRM_ERROR("Fence A signaled without waiting for semaphore.\n"); 424 DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
397 goto out_cleanup; 425 goto out_cleanup;
398 } 426 }
399 427
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
new file mode 100644
index 000000000000..906e5c0ca3b9
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -0,0 +1,831 @@
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31#include <linux/firmware.h>
32#include <linux/module.h>
33#include <drm/drmP.h>
34#include <drm/drm.h>
35
36#include "radeon.h"
37#include "r600d.h"
38
39/* 1 second timeout */
40#define UVD_IDLE_TIMEOUT_MS 1000
41
42/* Firmware Names */
43#define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
44#define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
45#define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"
46#define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"
47
48MODULE_FIRMWARE(FIRMWARE_RV710);
49MODULE_FIRMWARE(FIRMWARE_CYPRESS);
50MODULE_FIRMWARE(FIRMWARE_SUMO);
51MODULE_FIRMWARE(FIRMWARE_TAHITI);
52
53static void radeon_uvd_idle_work_handler(struct work_struct *work);
54
55int radeon_uvd_init(struct radeon_device *rdev)
56{
57 struct platform_device *pdev;
58 unsigned long bo_size;
59 const char *fw_name;
60 int i, r;
61
62 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
63
64 pdev = platform_device_register_simple("radeon_uvd", 0, NULL, 0);
65 r = IS_ERR(pdev);
66 if (r) {
67 dev_err(rdev->dev, "radeon_uvd: Failed to register firmware\n");
68 return -EINVAL;
69 }
70
71 switch (rdev->family) {
72 case CHIP_RV710:
73 case CHIP_RV730:
74 case CHIP_RV740:
75 fw_name = FIRMWARE_RV710;
76 break;
77
78 case CHIP_CYPRESS:
79 case CHIP_HEMLOCK:
80 case CHIP_JUNIPER:
81 case CHIP_REDWOOD:
82 case CHIP_CEDAR:
83 fw_name = FIRMWARE_CYPRESS;
84 break;
85
86 case CHIP_SUMO:
87 case CHIP_SUMO2:
88 case CHIP_PALM:
89 case CHIP_CAYMAN:
90 case CHIP_BARTS:
91 case CHIP_TURKS:
92 case CHIP_CAICOS:
93 fw_name = FIRMWARE_SUMO;
94 break;
95
96 case CHIP_TAHITI:
97 case CHIP_VERDE:
98 case CHIP_PITCAIRN:
99 case CHIP_ARUBA:
100 fw_name = FIRMWARE_TAHITI;
101 break;
102
103 default:
104 return -EINVAL;
105 }
106
107 r = request_firmware(&rdev->uvd_fw, fw_name, &pdev->dev);
108 if (r) {
109 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
110 fw_name);
111 platform_device_unregister(pdev);
112 return r;
113 }
114
115 platform_device_unregister(pdev);
116
117 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
118 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
119 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
120 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
121 if (r) {
122 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
123 return r;
124 }
125
126 r = radeon_uvd_resume(rdev);
127 if (r)
128 return r;
129
130 memset(rdev->uvd.cpu_addr, 0, bo_size);
131 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
132
133 r = radeon_uvd_suspend(rdev);
134 if (r)
135 return r;
136
137 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
138 atomic_set(&rdev->uvd.handles[i], 0);
139 rdev->uvd.filp[i] = NULL;
140 }
141
142 return 0;
143}
144
145void radeon_uvd_fini(struct radeon_device *rdev)
146{
147 radeon_uvd_suspend(rdev);
148 radeon_bo_unref(&rdev->uvd.vcpu_bo);
149}
150
151int radeon_uvd_suspend(struct radeon_device *rdev)
152{
153 int r;
154
155 if (rdev->uvd.vcpu_bo == NULL)
156 return 0;
157
158 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
159 if (!r) {
160 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
161 radeon_bo_unpin(rdev->uvd.vcpu_bo);
162 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
163 }
164 return r;
165}
166
167int radeon_uvd_resume(struct radeon_device *rdev)
168{
169 int r;
170
171 if (rdev->uvd.vcpu_bo == NULL)
172 return -EINVAL;
173
174 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
175 if (r) {
176 radeon_bo_unref(&rdev->uvd.vcpu_bo);
177 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
178 return r;
179 }
180
181 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
182 &rdev->uvd.gpu_addr);
183 if (r) {
184 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
185 radeon_bo_unref(&rdev->uvd.vcpu_bo);
186 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
187 return r;
188 }
189
190 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
191 if (r) {
192 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
193 return r;
194 }
195
196 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
197
198 return 0;
199}
200
201void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
202{
203 rbo->placement.fpfn = 0 >> PAGE_SHIFT;
204 rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
205}
206
207void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
208{
209 int i, r;
210 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
211 if (rdev->uvd.filp[i] == filp) {
212 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
213 struct radeon_fence *fence;
214
215 r = radeon_uvd_get_destroy_msg(rdev,
216 R600_RING_TYPE_UVD_INDEX, handle, &fence);
217 if (r) {
218 DRM_ERROR("Error destroying UVD (%d)!\n", r);
219 continue;
220 }
221
222 radeon_fence_wait(fence, false);
223 radeon_fence_unref(&fence);
224
225 rdev->uvd.filp[i] = NULL;
226 atomic_set(&rdev->uvd.handles[i], 0);
227 }
228 }
229}
230
231static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
232{
233 unsigned stream_type = msg[4];
234 unsigned width = msg[6];
235 unsigned height = msg[7];
236 unsigned dpb_size = msg[9];
237 unsigned pitch = msg[28];
238
239 unsigned width_in_mb = width / 16;
240 unsigned height_in_mb = ALIGN(height / 16, 2);
241
242 unsigned image_size, tmp, min_dpb_size;
243
244 image_size = width * height;
245 image_size += image_size / 2;
246 image_size = ALIGN(image_size, 1024);
247
248 switch (stream_type) {
249 case 0: /* H264 */
250
251 /* reference picture buffer */
252 min_dpb_size = image_size * 17;
253
254 /* macroblock context buffer */
255 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
256
257 /* IT surface buffer */
258 min_dpb_size += width_in_mb * height_in_mb * 32;
259 break;
260
261 case 1: /* VC1 */
262
263 /* reference picture buffer */
264 min_dpb_size = image_size * 3;
265
266 /* CONTEXT_BUFFER */
267 min_dpb_size += width_in_mb * height_in_mb * 128;
268
269 /* IT surface buffer */
270 min_dpb_size += width_in_mb * 64;
271
272 /* DB surface buffer */
273 min_dpb_size += width_in_mb * 128;
274
275 /* BP */
276 tmp = max(width_in_mb, height_in_mb);
277 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
278 break;
279
280 case 3: /* MPEG2 */
281
282 /* reference picture buffer */
283 min_dpb_size = image_size * 3;
284 break;
285
286 case 4: /* MPEG4 */
287
288 /* reference picture buffer */
289 min_dpb_size = image_size * 3;
290
291 /* CM */
292 min_dpb_size += width_in_mb * height_in_mb * 64;
293
294 /* IT surface buffer */
295 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
296 break;
297
298 default:
299 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
300 return -EINVAL;
301 }
302
303 if (width > pitch) {
304 DRM_ERROR("Invalid UVD decoding target pitch!\n");
305 return -EINVAL;
306 }
307
308 if (dpb_size < min_dpb_size) {
309 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
310 dpb_size, min_dpb_size);
311 return -EINVAL;
312 }
313
314 buf_sizes[0x1] = dpb_size;
315 buf_sizes[0x2] = image_size;
316 return 0;
317}
318
319static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
320 unsigned offset, unsigned buf_sizes[])
321{
322 int32_t *msg, msg_type, handle;
323 void *ptr;
324
325 int i, r;
326
327 if (offset & 0x3F) {
328 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
329 return -EINVAL;
330 }
331
332 r = radeon_bo_kmap(bo, &ptr);
333 if (r)
334 return r;
335
336 msg = ptr + offset;
337
338 msg_type = msg[1];
339 handle = msg[2];
340
341 if (handle == 0) {
342 DRM_ERROR("Invalid UVD handle!\n");
343 return -EINVAL;
344 }
345
346 if (msg_type == 1) {
347 /* it's a decode msg, calc buffer sizes */
348 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
349 radeon_bo_kunmap(bo);
350 if (r)
351 return r;
352
353 } else if (msg_type == 2) {
354 /* it's a destroy msg, free the handle */
355 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
356 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
357 radeon_bo_kunmap(bo);
358 return 0;
359 } else {
360 /* it's a create msg, no special handling needed */
361 radeon_bo_kunmap(bo);
362 }
363
364 /* create or decode, validate the handle */
365 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
366 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
367 return 0;
368 }
369
370 /* handle not found try to alloc a new one */
371 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
372 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
373 p->rdev->uvd.filp[i] = p->filp;
374 return 0;
375 }
376 }
377
378 DRM_ERROR("No more free UVD handles!\n");
379 return -EINVAL;
380}
381
382static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
383 int data0, int data1,
384 unsigned buf_sizes[])
385{
386 struct radeon_cs_chunk *relocs_chunk;
387 struct radeon_cs_reloc *reloc;
388 unsigned idx, cmd, offset;
389 uint64_t start, end;
390 int r;
391
392 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
393 offset = radeon_get_ib_value(p, data0);
394 idx = radeon_get_ib_value(p, data1);
395 if (idx >= relocs_chunk->length_dw) {
396 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
397 idx, relocs_chunk->length_dw);
398 return -EINVAL;
399 }
400
401 reloc = p->relocs_ptr[(idx / 4)];
402 start = reloc->lobj.gpu_offset;
403 end = start + radeon_bo_size(reloc->robj);
404 start += offset;
405
406 p->ib.ptr[data0] = start & 0xFFFFFFFF;
407 p->ib.ptr[data1] = start >> 32;
408
409 cmd = radeon_get_ib_value(p, p->idx) >> 1;
410
411 if (cmd < 0x4) {
412 if ((end - start) < buf_sizes[cmd]) {
413 DRM_ERROR("buffer to small (%d / %d)!\n",
414 (unsigned)(end - start), buf_sizes[cmd]);
415 return -EINVAL;
416 }
417
418 } else if (cmd != 0x100) {
419 DRM_ERROR("invalid UVD command %X!\n", cmd);
420 return -EINVAL;
421 }
422
423 if ((start >> 28) != (end >> 28)) {
424 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
425 start, end);
426 return -EINVAL;
427 }
428
429 /* TODO: is this still necessary on NI+ ? */
430 if ((cmd == 0 || cmd == 0x3) &&
431 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
432 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
433 start, end);
434 return -EINVAL;
435 }
436
437 if (cmd == 0) {
438 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
439 if (r)
440 return r;
441 }
442
443 return 0;
444}
445
446static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
447 struct radeon_cs_packet *pkt,
448 int *data0, int *data1,
449 unsigned buf_sizes[])
450{
451 int i, r;
452
453 p->idx++;
454 for (i = 0; i <= pkt->count; ++i) {
455 switch (pkt->reg + i*4) {
456 case UVD_GPCOM_VCPU_DATA0:
457 *data0 = p->idx;
458 break;
459 case UVD_GPCOM_VCPU_DATA1:
460 *data1 = p->idx;
461 break;
462 case UVD_GPCOM_VCPU_CMD:
463 r = radeon_uvd_cs_reloc(p, *data0, *data1, buf_sizes);
464 if (r)
465 return r;
466 break;
467 case UVD_ENGINE_CNTL:
468 break;
469 default:
470 DRM_ERROR("Invalid reg 0x%X!\n",
471 pkt->reg + i*4);
472 return -EINVAL;
473 }
474 p->idx++;
475 }
476 return 0;
477}
478
479int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
480{
481 struct radeon_cs_packet pkt;
482 int r, data0 = 0, data1 = 0;
483
484 /* minimum buffer sizes */
485 unsigned buf_sizes[] = {
486 [0x00000000] = 2048,
487 [0x00000001] = 32 * 1024 * 1024,
488 [0x00000002] = 2048 * 1152 * 3,
489 [0x00000003] = 2048,
490 };
491
492 if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
493 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
494 p->chunks[p->chunk_ib_idx].length_dw);
495 return -EINVAL;
496 }
497
498 if (p->chunk_relocs_idx == -1) {
499 DRM_ERROR("No relocation chunk !\n");
500 return -EINVAL;
501 }
502
503
504 do {
505 r = radeon_cs_packet_parse(p, &pkt, p->idx);
506 if (r)
507 return r;
508 switch (pkt.type) {
509 case RADEON_PACKET_TYPE0:
510 r = radeon_uvd_cs_reg(p, &pkt, &data0,
511 &data1, buf_sizes);
512 if (r)
513 return r;
514 break;
515 case RADEON_PACKET_TYPE2:
516 p->idx += pkt.count + 2;
517 break;
518 default:
519 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
520 return -EINVAL;
521 }
522 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
523 return 0;
524}
525
526static int radeon_uvd_send_msg(struct radeon_device *rdev,
527 int ring, struct radeon_bo *bo,
528 struct radeon_fence **fence)
529{
530 struct ttm_validate_buffer tv;
531 struct list_head head;
532 struct radeon_ib ib;
533 uint64_t addr;
534 int i, r;
535
536 memset(&tv, 0, sizeof(tv));
537 tv.bo = &bo->tbo;
538
539 INIT_LIST_HEAD(&head);
540 list_add(&tv.head, &head);
541
542 r = ttm_eu_reserve_buffers(&head);
543 if (r)
544 return r;
545
546 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
547 radeon_uvd_force_into_uvd_segment(bo);
548
549 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
550 if (r) {
551 ttm_eu_backoff_reservation(&head);
552 return r;
553 }
554
555 r = radeon_ib_get(rdev, ring, &ib, NULL, 16);
556 if (r) {
557 ttm_eu_backoff_reservation(&head);
558 return r;
559 }
560
561 addr = radeon_bo_gpu_offset(bo);
562 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
563 ib.ptr[1] = addr;
564 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
565 ib.ptr[3] = addr >> 32;
566 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
567 ib.ptr[5] = 0;
568 for (i = 6; i < 16; ++i)
569 ib.ptr[i] = PACKET2(0);
570 ib.length_dw = 16;
571
572 r = radeon_ib_schedule(rdev, &ib, NULL);
573 if (r) {
574 ttm_eu_backoff_reservation(&head);
575 return r;
576 }
577 ttm_eu_fence_buffer_objects(&head, ib.fence);
578
579 if (fence)
580 *fence = radeon_fence_ref(ib.fence);
581
582 radeon_ib_free(rdev, &ib);
583 radeon_bo_unref(&bo);
584 return 0;
585}
586
587/* multiple fence commands without any stream commands in between can
588 crash the vcpu so just try to emmit a dummy create/destroy msg to
589 avoid this */
590int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
591 uint32_t handle, struct radeon_fence **fence)
592{
593 struct radeon_bo *bo;
594 uint32_t *msg;
595 int r, i;
596
597 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
598 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
599 if (r)
600 return r;
601
602 r = radeon_bo_reserve(bo, false);
603 if (r) {
604 radeon_bo_unref(&bo);
605 return r;
606 }
607
608 r = radeon_bo_kmap(bo, (void **)&msg);
609 if (r) {
610 radeon_bo_unreserve(bo);
611 radeon_bo_unref(&bo);
612 return r;
613 }
614
615 /* stitch together an UVD create msg */
616 msg[0] = 0x00000de4;
617 msg[1] = 0x00000000;
618 msg[2] = handle;
619 msg[3] = 0x00000000;
620 msg[4] = 0x00000000;
621 msg[5] = 0x00000000;
622 msg[6] = 0x00000000;
623 msg[7] = 0x00000780;
624 msg[8] = 0x00000440;
625 msg[9] = 0x00000000;
626 msg[10] = 0x01b37000;
627 for (i = 11; i < 1024; ++i)
628 msg[i] = 0x0;
629
630 radeon_bo_kunmap(bo);
631 radeon_bo_unreserve(bo);
632
633 return radeon_uvd_send_msg(rdev, ring, bo, fence);
634}
635
636int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
637 uint32_t handle, struct radeon_fence **fence)
638{
639 struct radeon_bo *bo;
640 uint32_t *msg;
641 int r, i;
642
643 r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
644 RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
645 if (r)
646 return r;
647
648 r = radeon_bo_reserve(bo, false);
649 if (r) {
650 radeon_bo_unref(&bo);
651 return r;
652 }
653
654 r = radeon_bo_kmap(bo, (void **)&msg);
655 if (r) {
656 radeon_bo_unreserve(bo);
657 radeon_bo_unref(&bo);
658 return r;
659 }
660
661 /* stitch together an UVD destroy msg */
662 msg[0] = 0x00000de4;
663 msg[1] = 0x00000002;
664 msg[2] = handle;
665 msg[3] = 0x00000000;
666 for (i = 4; i < 1024; ++i)
667 msg[i] = 0x0;
668
669 radeon_bo_kunmap(bo);
670 radeon_bo_unreserve(bo);
671
672 return radeon_uvd_send_msg(rdev, ring, bo, fence);
673}
674
675static void radeon_uvd_idle_work_handler(struct work_struct *work)
676{
677 struct radeon_device *rdev =
678 container_of(work, struct radeon_device, uvd.idle_work.work);
679
680 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0)
681 radeon_set_uvd_clocks(rdev, 0, 0);
682 else
683 schedule_delayed_work(&rdev->uvd.idle_work,
684 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
685}
686
687void radeon_uvd_note_usage(struct radeon_device *rdev)
688{
689 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
690 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
691 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
692 if (set_clocks)
693 radeon_set_uvd_clocks(rdev, 53300, 40000);
694}
695
696static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
697 unsigned target_freq,
698 unsigned pd_min,
699 unsigned pd_even)
700{
701 unsigned post_div = vco_freq / target_freq;
702
703 /* adjust to post divider minimum value */
704 if (post_div < pd_min)
705 post_div = pd_min;
706
707 /* we alway need a frequency less than or equal the target */
708 if ((vco_freq / post_div) > target_freq)
709 post_div += 1;
710
711 /* post dividers above a certain value must be even */
712 if (post_div > pd_even && post_div % 2)
713 post_div += 1;
714
715 return post_div;
716}
717
718/**
719 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
720 *
721 * @rdev: radeon_device pointer
722 * @vclk: wanted VCLK
723 * @dclk: wanted DCLK
724 * @vco_min: minimum VCO frequency
725 * @vco_max: maximum VCO frequency
726 * @fb_factor: factor to multiply vco freq with
727 * @fb_mask: limit and bitmask for feedback divider
728 * @pd_min: post divider minimum
729 * @pd_max: post divider maximum
730 * @pd_even: post divider must be even above this value
731 * @optimal_fb_div: resulting feedback divider
732 * @optimal_vclk_div: resulting vclk post divider
733 * @optimal_dclk_div: resulting dclk post divider
734 *
735 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
736 * Returns zero on success -EINVAL on error.
737 */
738int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
739 unsigned vclk, unsigned dclk,
740 unsigned vco_min, unsigned vco_max,
741 unsigned fb_factor, unsigned fb_mask,
742 unsigned pd_min, unsigned pd_max,
743 unsigned pd_even,
744 unsigned *optimal_fb_div,
745 unsigned *optimal_vclk_div,
746 unsigned *optimal_dclk_div)
747{
748 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
749
750 /* start off with something large */
751 unsigned optimal_score = ~0;
752
753 /* loop through vco from low to high */
754 vco_min = max(max(vco_min, vclk), dclk);
755 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
756
757 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
758 unsigned vclk_div, dclk_div, score;
759
760 do_div(fb_div, ref_freq);
761
762 /* fb div out of range ? */
763 if (fb_div > fb_mask)
764 break; /* it can oly get worse */
765
766 fb_div &= fb_mask;
767
768 /* calc vclk divider with current vco freq */
769 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
770 pd_min, pd_even);
771 if (vclk_div > pd_max)
772 break; /* vco is too big, it has to stop */
773
774 /* calc dclk divider with current vco freq */
775 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
776 pd_min, pd_even);
777 if (vclk_div > pd_max)
778 break; /* vco is too big, it has to stop */
779
780 /* calc score with current vco freq */
781 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
782
783 /* determine if this vco setting is better than current optimal settings */
784 if (score < optimal_score) {
785 *optimal_fb_div = fb_div;
786 *optimal_vclk_div = vclk_div;
787 *optimal_dclk_div = dclk_div;
788 optimal_score = score;
789 if (optimal_score == 0)
790 break; /* it can't get better than this */
791 }
792 }
793
794 /* did we found a valid setup ? */
795 if (optimal_score == ~0)
796 return -EINVAL;
797
798 return 0;
799}
800
801int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
802 unsigned cg_upll_func_cntl)
803{
804 unsigned i;
805
806 /* make sure UPLL_CTLREQ is deasserted */
807 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
808
809 mdelay(10);
810
811 /* assert UPLL_CTLREQ */
812 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
813
814 /* wait for CTLACK and CTLACK2 to get asserted */
815 for (i = 0; i < 100; ++i) {
816 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
817 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
818 break;
819 mdelay(10);
820 }
821
822 /* deassert UPLL_CTLREQ */
823 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
824
825 if (i == 100) {
826 DRM_ERROR("Timeout setting UVD clocks!\n");
827 return -ETIMEDOUT;
828 }
829
830 return 0;
831}
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 5a0fc74c2ba6..46fa1b07c560 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -52,23 +52,59 @@ static const u32 crtc_offsets[2] =
52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
53}; 53};
54 54
55static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
56{
57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
58 return true;
59 else
60 return false;
61}
62
63static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
64{
65 u32 pos1, pos2;
66
67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
69
70 if (pos1 != pos2)
71 return true;
72 else
73 return false;
74}
75
76/**
77 * avivo_wait_for_vblank - vblank wait asic callback.
78 *
79 * @rdev: radeon_device pointer
80 * @crtc: crtc to wait for vblank on
81 *
82 * Wait for vblank on the requested crtc (r5xx-r7xx).
83 */
55void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 84void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
56{ 85{
57 int i; 86 unsigned i = 0;
58 87
59 if (crtc >= rdev->num_crtc) 88 if (crtc >= rdev->num_crtc)
60 return; 89 return;
61 90
62 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) { 91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
63 for (i = 0; i < rdev->usec_timeout; i++) { 92 return;
64 if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)) 93
94 /* depending on when we hit vblank, we may be close to active; if so,
95 * wait for another frame.
96 */
97 while (avivo_is_in_vblank(rdev, crtc)) {
98 if (i++ % 100 == 0) {
99 if (!avivo_is_counter_moving(rdev, crtc))
65 break; 100 break;
66 udelay(1);
67 } 101 }
68 for (i = 0; i < rdev->usec_timeout; i++) { 102 }
69 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 103
104 while (!avivo_is_in_vblank(rdev, crtc)) {
105 if (i++ % 100 == 0) {
106 if (!avivo_is_counter_moving(rdev, crtc))
70 break; 107 break;
71 udelay(1);
72 } 108 }
73 } 109 }
74} 110}
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 5706d2ac75ab..ab4c86cfd552 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -148,6 +148,8 @@ void rs690_pm_info(struct radeon_device *rdev)
148static void rs690_mc_init(struct radeon_device *rdev) 148static void rs690_mc_init(struct radeon_device *rdev)
149{ 149{
150 u64 base; 150 u64 base;
151 uint32_t h_addr, l_addr;
152 unsigned long long k8_addr;
151 153
152 rs400_gart_adjust_size(rdev); 154 rs400_gart_adjust_size(rdev);
153 rdev->mc.vram_is_ddr = true; 155 rdev->mc.vram_is_ddr = true;
@@ -160,6 +162,27 @@ static void rs690_mc_init(struct radeon_device *rdev)
160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 162 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 base = G_000100_MC_FB_START(base) << 16; 163 base = G_000100_MC_FB_START(base) << 16;
162 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 164 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
165
166 /* Use K8 direct mapping for fast fb access. */
167 rdev->fastfb_working = false;
168 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
169 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
170 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
171#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
172 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
173#endif
174 {
175 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
176 * memory is present.
177 */
178 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
179 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
180 (unsigned long long)rdev->mc.aper_base, k8_addr);
181 rdev->mc.aper_base = (resource_size_t)k8_addr;
182 rdev->fastfb_working = true;
183 }
184 }
185
163 rs690_pm_info(rdev); 186 rs690_pm_info(rdev);
164 radeon_vram_location(rdev, &rdev->mc, base); 187 radeon_vram_location(rdev, &rdev->mc, base);
165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 188 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
diff --git a/drivers/gpu/drm/radeon/rs690d.h b/drivers/gpu/drm/radeon/rs690d.h
index 36e6398a98ae..8af3ccf20cc0 100644
--- a/drivers/gpu/drm/radeon/rs690d.h
+++ b/drivers/gpu/drm/radeon/rs690d.h
@@ -29,6 +29,9 @@
29#define __RS690D_H__ 29#define __RS690D_H__
30 30
31/* Registers */ 31/* Registers */
32#define R_00001E_K8_FB_LOCATION 0x00001E
33#define R_00005F_MC_MISC_UMA_CNTL 0x00005F
34#define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
32#define R_000078_MC_INDEX 0x000078 35#define R_000078_MC_INDEX 0x000078
33#define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) 36#define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
34#define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) 37#define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF)
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 435ed3551364..ffcba730c57c 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -303,8 +303,10 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
303 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 303 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
304 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 304 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
305 radeon_wait_for_vblank(rdev, i); 305 radeon_wait_for_vblank(rdev, i);
306 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
306 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 307 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
307 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 308 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
309 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
308 } 310 }
309 /* wait for the next frame */ 311 /* wait for the next frame */
310 frame_count = radeon_get_vblank_counter(rdev, i); 312 frame_count = radeon_get_vblank_counter(rdev, i);
@@ -313,6 +315,15 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
313 break; 315 break;
314 udelay(1); 316 udelay(1);
315 } 317 }
318
319 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
320 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
321 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
322 tmp &= ~AVIVO_CRTC_EN;
323 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
324 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
325 save->crtc_enabled[i] = false;
326 /* ***** */
316 } else { 327 } else {
317 save->crtc_enabled[i] = false; 328 save->crtc_enabled[i] = false;
318 } 329 }
@@ -338,6 +349,22 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
338 } 349 }
339 /* wait for the MC to settle */ 350 /* wait for the MC to settle */
340 udelay(100); 351 udelay(100);
352
353 /* lock double buffered regs */
354 for (i = 0; i < rdev->num_crtc; i++) {
355 if (save->crtc_enabled[i]) {
356 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
357 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
358 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
359 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
360 }
361 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
362 if (!(tmp & 1)) {
363 tmp |= 1;
364 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
365 }
366 }
367 }
341} 368}
342 369
343void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 370void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -348,7 +375,7 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
348 /* update crtc base addresses */ 375 /* update crtc base addresses */
349 for (i = 0; i < rdev->num_crtc; i++) { 376 for (i = 0; i < rdev->num_crtc; i++) {
350 if (rdev->family >= CHIP_RV770) { 377 if (rdev->family >= CHIP_RV770) {
351 if (i == 1) { 378 if (i == 0) {
352 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 379 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
353 upper_32_bits(rdev->mc.vram_start)); 380 upper_32_bits(rdev->mc.vram_start));
354 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 381 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
@@ -367,6 +394,33 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
367 } 394 }
368 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 395 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
369 396
397 /* unlock regs and wait for update */
398 for (i = 0; i < rdev->num_crtc; i++) {
399 if (save->crtc_enabled[i]) {
400 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
401 if ((tmp & 0x3) != 0) {
402 tmp &= ~0x3;
403 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
404 }
405 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
406 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
407 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
408 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
409 }
410 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
411 if (tmp & 1) {
412 tmp &= ~1;
413 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
414 }
415 for (j = 0; j < rdev->usec_timeout; j++) {
416 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
417 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
418 break;
419 udelay(1);
420 }
421 }
422 }
423
370 if (rdev->family >= CHIP_R600) { 424 if (rdev->family >= CHIP_R600) {
371 /* unblackout the MC */ 425 /* unblackout the MC */
372 if (rdev->family >= CHIP_RV770) 426 if (rdev->family >= CHIP_RV770)
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index d63fe1d0f53f..83f612a9500b 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -42,6 +42,739 @@
42static void rv770_gpu_init(struct radeon_device *rdev); 42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev); 43void rv770_fini(struct radeon_device *rdev);
44static void rv770_pcie_gen2_enable(struct radeon_device *rdev); 44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
46
47int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
48{
49 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
50 int r;
51
52 /* RV740 uses evergreen uvd clk programming */
53 if (rdev->family == CHIP_RV740)
54 return evergreen_set_uvd_clocks(rdev, vclk, dclk);
55
56 /* bypass vclk and dclk with bclk */
57 WREG32_P(CG_UPLL_FUNC_CNTL_2,
58 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
59 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
60
61 if (!vclk || !dclk) {
62 /* keep the Bypass mode, put PLL to sleep */
63 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
64 return 0;
65 }
66
67 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
68 43663, 0x03FFFFFE, 1, 30, ~0,
69 &fb_div, &vclk_div, &dclk_div);
70 if (r)
71 return r;
72
73 fb_div |= 1;
74 vclk_div -= 1;
75 dclk_div -= 1;
76
77 /* set UPLL_FB_DIV to 0x50000 */
78 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
79
80 /* deassert UPLL_RESET and UPLL_SLEEP */
81 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
82
83 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
84 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
86
87 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
88 if (r)
89 return r;
90
91 /* assert PLL_RESET */
92 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
93
94 /* set the required FB_DIV, REF_DIV, Post divder values */
95 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
96 WREG32_P(CG_UPLL_FUNC_CNTL_2,
97 UPLL_SW_HILEN(vclk_div >> 1) |
98 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
99 UPLL_SW_HILEN2(dclk_div >> 1) |
100 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
101 ~UPLL_SW_MASK);
102
103 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
104 ~UPLL_FB_DIV_MASK);
105
106 /* give the PLL some time to settle */
107 mdelay(15);
108
109 /* deassert PLL_RESET */
110 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
111
112 mdelay(15);
113
114 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
115 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
116 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
117
118 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
119 if (r)
120 return r;
121
122 /* switch VCLK and DCLK selection */
123 WREG32_P(CG_UPLL_FUNC_CNTL_2,
124 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
125 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
126
127 mdelay(100);
128
129 return 0;
130}
131
132static const u32 r7xx_golden_registers[] =
133{
134 0x8d00, 0xffffffff, 0x0e0e0074,
135 0x8d04, 0xffffffff, 0x013a2b34,
136 0x9508, 0xffffffff, 0x00000002,
137 0x8b20, 0xffffffff, 0,
138 0x88c4, 0xffffffff, 0x000000c2,
139 0x28350, 0xffffffff, 0,
140 0x9058, 0xffffffff, 0x0fffc40f,
141 0x240c, 0xffffffff, 0x00000380,
142 0x733c, 0xffffffff, 0x00000002,
143 0x2650, 0x00040000, 0,
144 0x20bc, 0x00040000, 0,
145 0x7300, 0xffffffff, 0x001000f0
146};
147
148static const u32 r7xx_golden_dyn_gpr_registers[] =
149{
150 0x8db0, 0xffffffff, 0x98989898,
151 0x8db4, 0xffffffff, 0x98989898,
152 0x8db8, 0xffffffff, 0x98989898,
153 0x8dbc, 0xffffffff, 0x98989898,
154 0x8dc0, 0xffffffff, 0x98989898,
155 0x8dc4, 0xffffffff, 0x98989898,
156 0x8dc8, 0xffffffff, 0x98989898,
157 0x8dcc, 0xffffffff, 0x98989898,
158 0x88c4, 0xffffffff, 0x00000082
159};
160
161static const u32 rv770_golden_registers[] =
162{
163 0x562c, 0xffffffff, 0,
164 0x3f90, 0xffffffff, 0,
165 0x9148, 0xffffffff, 0,
166 0x3f94, 0xffffffff, 0,
167 0x914c, 0xffffffff, 0,
168 0x9698, 0x18000000, 0x18000000
169};
170
171static const u32 rv770ce_golden_registers[] =
172{
173 0x562c, 0xffffffff, 0,
174 0x3f90, 0xffffffff, 0x00cc0000,
175 0x9148, 0xffffffff, 0x00cc0000,
176 0x3f94, 0xffffffff, 0x00cc0000,
177 0x914c, 0xffffffff, 0x00cc0000,
178 0x9b7c, 0xffffffff, 0x00fa0000,
179 0x3f8c, 0xffffffff, 0x00fa0000,
180 0x9698, 0x18000000, 0x18000000
181};
182
183static const u32 rv770_mgcg_init[] =
184{
185 0x8bcc, 0xffffffff, 0x130300f9,
186 0x5448, 0xffffffff, 0x100,
187 0x55e4, 0xffffffff, 0x100,
188 0x160c, 0xffffffff, 0x100,
189 0x5644, 0xffffffff, 0x100,
190 0xc164, 0xffffffff, 0x100,
191 0x8a18, 0xffffffff, 0x100,
192 0x897c, 0xffffffff, 0x8000100,
193 0x8b28, 0xffffffff, 0x3c000100,
194 0x9144, 0xffffffff, 0x100,
195 0x9a1c, 0xffffffff, 0x10000,
196 0x9a50, 0xffffffff, 0x100,
197 0x9a1c, 0xffffffff, 0x10001,
198 0x9a50, 0xffffffff, 0x100,
199 0x9a1c, 0xffffffff, 0x10002,
200 0x9a50, 0xffffffff, 0x100,
201 0x9a1c, 0xffffffff, 0x10003,
202 0x9a50, 0xffffffff, 0x100,
203 0x9a1c, 0xffffffff, 0x0,
204 0x9870, 0xffffffff, 0x100,
205 0x8d58, 0xffffffff, 0x100,
206 0x9500, 0xffffffff, 0x0,
207 0x9510, 0xffffffff, 0x100,
208 0x9500, 0xffffffff, 0x1,
209 0x9510, 0xffffffff, 0x100,
210 0x9500, 0xffffffff, 0x2,
211 0x9510, 0xffffffff, 0x100,
212 0x9500, 0xffffffff, 0x3,
213 0x9510, 0xffffffff, 0x100,
214 0x9500, 0xffffffff, 0x4,
215 0x9510, 0xffffffff, 0x100,
216 0x9500, 0xffffffff, 0x5,
217 0x9510, 0xffffffff, 0x100,
218 0x9500, 0xffffffff, 0x6,
219 0x9510, 0xffffffff, 0x100,
220 0x9500, 0xffffffff, 0x7,
221 0x9510, 0xffffffff, 0x100,
222 0x9500, 0xffffffff, 0x8,
223 0x9510, 0xffffffff, 0x100,
224 0x9500, 0xffffffff, 0x9,
225 0x9510, 0xffffffff, 0x100,
226 0x9500, 0xffffffff, 0x8000,
227 0x9490, 0xffffffff, 0x0,
228 0x949c, 0xffffffff, 0x100,
229 0x9490, 0xffffffff, 0x1,
230 0x949c, 0xffffffff, 0x100,
231 0x9490, 0xffffffff, 0x2,
232 0x949c, 0xffffffff, 0x100,
233 0x9490, 0xffffffff, 0x3,
234 0x949c, 0xffffffff, 0x100,
235 0x9490, 0xffffffff, 0x4,
236 0x949c, 0xffffffff, 0x100,
237 0x9490, 0xffffffff, 0x5,
238 0x949c, 0xffffffff, 0x100,
239 0x9490, 0xffffffff, 0x6,
240 0x949c, 0xffffffff, 0x100,
241 0x9490, 0xffffffff, 0x7,
242 0x949c, 0xffffffff, 0x100,
243 0x9490, 0xffffffff, 0x8,
244 0x949c, 0xffffffff, 0x100,
245 0x9490, 0xffffffff, 0x9,
246 0x949c, 0xffffffff, 0x100,
247 0x9490, 0xffffffff, 0x8000,
248 0x9604, 0xffffffff, 0x0,
249 0x9654, 0xffffffff, 0x100,
250 0x9604, 0xffffffff, 0x1,
251 0x9654, 0xffffffff, 0x100,
252 0x9604, 0xffffffff, 0x2,
253 0x9654, 0xffffffff, 0x100,
254 0x9604, 0xffffffff, 0x3,
255 0x9654, 0xffffffff, 0x100,
256 0x9604, 0xffffffff, 0x4,
257 0x9654, 0xffffffff, 0x100,
258 0x9604, 0xffffffff, 0x5,
259 0x9654, 0xffffffff, 0x100,
260 0x9604, 0xffffffff, 0x6,
261 0x9654, 0xffffffff, 0x100,
262 0x9604, 0xffffffff, 0x7,
263 0x9654, 0xffffffff, 0x100,
264 0x9604, 0xffffffff, 0x8,
265 0x9654, 0xffffffff, 0x100,
266 0x9604, 0xffffffff, 0x9,
267 0x9654, 0xffffffff, 0x100,
268 0x9604, 0xffffffff, 0x80000000,
269 0x9030, 0xffffffff, 0x100,
270 0x9034, 0xffffffff, 0x100,
271 0x9038, 0xffffffff, 0x100,
272 0x903c, 0xffffffff, 0x100,
273 0x9040, 0xffffffff, 0x100,
274 0xa200, 0xffffffff, 0x100,
275 0xa204, 0xffffffff, 0x100,
276 0xa208, 0xffffffff, 0x100,
277 0xa20c, 0xffffffff, 0x100,
278 0x971c, 0xffffffff, 0x100,
279 0x915c, 0xffffffff, 0x00020001,
280 0x9160, 0xffffffff, 0x00040003,
281 0x916c, 0xffffffff, 0x00060005,
282 0x9170, 0xffffffff, 0x00080007,
283 0x9174, 0xffffffff, 0x000a0009,
284 0x9178, 0xffffffff, 0x000c000b,
285 0x917c, 0xffffffff, 0x000e000d,
286 0x9180, 0xffffffff, 0x0010000f,
287 0x918c, 0xffffffff, 0x00120011,
288 0x9190, 0xffffffff, 0x00140013,
289 0x9194, 0xffffffff, 0x00020001,
290 0x9198, 0xffffffff, 0x00040003,
291 0x919c, 0xffffffff, 0x00060005,
292 0x91a8, 0xffffffff, 0x00080007,
293 0x91ac, 0xffffffff, 0x000a0009,
294 0x91b0, 0xffffffff, 0x000c000b,
295 0x91b4, 0xffffffff, 0x000e000d,
296 0x91b8, 0xffffffff, 0x0010000f,
297 0x91c4, 0xffffffff, 0x00120011,
298 0x91c8, 0xffffffff, 0x00140013,
299 0x91cc, 0xffffffff, 0x00020001,
300 0x91d0, 0xffffffff, 0x00040003,
301 0x91d4, 0xffffffff, 0x00060005,
302 0x91e0, 0xffffffff, 0x00080007,
303 0x91e4, 0xffffffff, 0x000a0009,
304 0x91e8, 0xffffffff, 0x000c000b,
305 0x91ec, 0xffffffff, 0x00020001,
306 0x91f0, 0xffffffff, 0x00040003,
307 0x91f4, 0xffffffff, 0x00060005,
308 0x9200, 0xffffffff, 0x00080007,
309 0x9204, 0xffffffff, 0x000a0009,
310 0x9208, 0xffffffff, 0x000c000b,
311 0x920c, 0xffffffff, 0x000e000d,
312 0x9210, 0xffffffff, 0x0010000f,
313 0x921c, 0xffffffff, 0x00120011,
314 0x9220, 0xffffffff, 0x00140013,
315 0x9224, 0xffffffff, 0x00020001,
316 0x9228, 0xffffffff, 0x00040003,
317 0x922c, 0xffffffff, 0x00060005,
318 0x9238, 0xffffffff, 0x00080007,
319 0x923c, 0xffffffff, 0x000a0009,
320 0x9240, 0xffffffff, 0x000c000b,
321 0x9244, 0xffffffff, 0x000e000d,
322 0x9248, 0xffffffff, 0x0010000f,
323 0x9254, 0xffffffff, 0x00120011,
324 0x9258, 0xffffffff, 0x00140013,
325 0x925c, 0xffffffff, 0x00020001,
326 0x9260, 0xffffffff, 0x00040003,
327 0x9264, 0xffffffff, 0x00060005,
328 0x9270, 0xffffffff, 0x00080007,
329 0x9274, 0xffffffff, 0x000a0009,
330 0x9278, 0xffffffff, 0x000c000b,
331 0x927c, 0xffffffff, 0x000e000d,
332 0x9280, 0xffffffff, 0x0010000f,
333 0x928c, 0xffffffff, 0x00120011,
334 0x9290, 0xffffffff, 0x00140013,
335 0x9294, 0xffffffff, 0x00020001,
336 0x929c, 0xffffffff, 0x00040003,
337 0x92a0, 0xffffffff, 0x00060005,
338 0x92a4, 0xffffffff, 0x00080007
339};
340
341static const u32 rv710_golden_registers[] =
342{
343 0x3f90, 0x00ff0000, 0x00fc0000,
344 0x9148, 0x00ff0000, 0x00fc0000,
345 0x3f94, 0x00ff0000, 0x00fc0000,
346 0x914c, 0x00ff0000, 0x00fc0000,
347 0xb4c, 0x00000020, 0x00000020,
348 0xa180, 0xffffffff, 0x00003f3f
349};
350
351static const u32 rv710_mgcg_init[] =
352{
353 0x8bcc, 0xffffffff, 0x13030040,
354 0x5448, 0xffffffff, 0x100,
355 0x55e4, 0xffffffff, 0x100,
356 0x160c, 0xffffffff, 0x100,
357 0x5644, 0xffffffff, 0x100,
358 0xc164, 0xffffffff, 0x100,
359 0x8a18, 0xffffffff, 0x100,
360 0x897c, 0xffffffff, 0x8000100,
361 0x8b28, 0xffffffff, 0x3c000100,
362 0x9144, 0xffffffff, 0x100,
363 0x9a1c, 0xffffffff, 0x10000,
364 0x9a50, 0xffffffff, 0x100,
365 0x9a1c, 0xffffffff, 0x0,
366 0x9870, 0xffffffff, 0x100,
367 0x8d58, 0xffffffff, 0x100,
368 0x9500, 0xffffffff, 0x0,
369 0x9510, 0xffffffff, 0x100,
370 0x9500, 0xffffffff, 0x1,
371 0x9510, 0xffffffff, 0x100,
372 0x9500, 0xffffffff, 0x8000,
373 0x9490, 0xffffffff, 0x0,
374 0x949c, 0xffffffff, 0x100,
375 0x9490, 0xffffffff, 0x1,
376 0x949c, 0xffffffff, 0x100,
377 0x9490, 0xffffffff, 0x8000,
378 0x9604, 0xffffffff, 0x0,
379 0x9654, 0xffffffff, 0x100,
380 0x9604, 0xffffffff, 0x1,
381 0x9654, 0xffffffff, 0x100,
382 0x9604, 0xffffffff, 0x80000000,
383 0x9030, 0xffffffff, 0x100,
384 0x9034, 0xffffffff, 0x100,
385 0x9038, 0xffffffff, 0x100,
386 0x903c, 0xffffffff, 0x100,
387 0x9040, 0xffffffff, 0x100,
388 0xa200, 0xffffffff, 0x100,
389 0xa204, 0xffffffff, 0x100,
390 0xa208, 0xffffffff, 0x100,
391 0xa20c, 0xffffffff, 0x100,
392 0x971c, 0xffffffff, 0x100,
393 0x915c, 0xffffffff, 0x00020001,
394 0x9174, 0xffffffff, 0x00000003,
395 0x9178, 0xffffffff, 0x00050001,
396 0x917c, 0xffffffff, 0x00030002,
397 0x918c, 0xffffffff, 0x00000004,
398 0x9190, 0xffffffff, 0x00070006,
399 0x9194, 0xffffffff, 0x00050001,
400 0x9198, 0xffffffff, 0x00030002,
401 0x91a8, 0xffffffff, 0x00000004,
402 0x91ac, 0xffffffff, 0x00070006,
403 0x91e8, 0xffffffff, 0x00000001,
404 0x9294, 0xffffffff, 0x00000001,
405 0x929c, 0xffffffff, 0x00000002,
406 0x92a0, 0xffffffff, 0x00040003,
407 0x9150, 0xffffffff, 0x4d940000
408};
409
410static const u32 rv730_golden_registers[] =
411{
412 0x3f90, 0x00ff0000, 0x00f00000,
413 0x9148, 0x00ff0000, 0x00f00000,
414 0x3f94, 0x00ff0000, 0x00f00000,
415 0x914c, 0x00ff0000, 0x00f00000,
416 0x900c, 0xffffffff, 0x003b033f,
417 0xb4c, 0x00000020, 0x00000020,
418 0xa180, 0xffffffff, 0x00003f3f
419};
420
421static const u32 rv730_mgcg_init[] =
422{
423 0x8bcc, 0xffffffff, 0x130300f9,
424 0x5448, 0xffffffff, 0x100,
425 0x55e4, 0xffffffff, 0x100,
426 0x160c, 0xffffffff, 0x100,
427 0x5644, 0xffffffff, 0x100,
428 0xc164, 0xffffffff, 0x100,
429 0x8a18, 0xffffffff, 0x100,
430 0x897c, 0xffffffff, 0x8000100,
431 0x8b28, 0xffffffff, 0x3c000100,
432 0x9144, 0xffffffff, 0x100,
433 0x9a1c, 0xffffffff, 0x10000,
434 0x9a50, 0xffffffff, 0x100,
435 0x9a1c, 0xffffffff, 0x10001,
436 0x9a50, 0xffffffff, 0x100,
437 0x9a1c, 0xffffffff, 0x0,
438 0x9870, 0xffffffff, 0x100,
439 0x8d58, 0xffffffff, 0x100,
440 0x9500, 0xffffffff, 0x0,
441 0x9510, 0xffffffff, 0x100,
442 0x9500, 0xffffffff, 0x1,
443 0x9510, 0xffffffff, 0x100,
444 0x9500, 0xffffffff, 0x2,
445 0x9510, 0xffffffff, 0x100,
446 0x9500, 0xffffffff, 0x3,
447 0x9510, 0xffffffff, 0x100,
448 0x9500, 0xffffffff, 0x4,
449 0x9510, 0xffffffff, 0x100,
450 0x9500, 0xffffffff, 0x5,
451 0x9510, 0xffffffff, 0x100,
452 0x9500, 0xffffffff, 0x6,
453 0x9510, 0xffffffff, 0x100,
454 0x9500, 0xffffffff, 0x7,
455 0x9510, 0xffffffff, 0x100,
456 0x9500, 0xffffffff, 0x8000,
457 0x9490, 0xffffffff, 0x0,
458 0x949c, 0xffffffff, 0x100,
459 0x9490, 0xffffffff, 0x1,
460 0x949c, 0xffffffff, 0x100,
461 0x9490, 0xffffffff, 0x2,
462 0x949c, 0xffffffff, 0x100,
463 0x9490, 0xffffffff, 0x3,
464 0x949c, 0xffffffff, 0x100,
465 0x9490, 0xffffffff, 0x4,
466 0x949c, 0xffffffff, 0x100,
467 0x9490, 0xffffffff, 0x5,
468 0x949c, 0xffffffff, 0x100,
469 0x9490, 0xffffffff, 0x6,
470 0x949c, 0xffffffff, 0x100,
471 0x9490, 0xffffffff, 0x7,
472 0x949c, 0xffffffff, 0x100,
473 0x9490, 0xffffffff, 0x8000,
474 0x9604, 0xffffffff, 0x0,
475 0x9654, 0xffffffff, 0x100,
476 0x9604, 0xffffffff, 0x1,
477 0x9654, 0xffffffff, 0x100,
478 0x9604, 0xffffffff, 0x2,
479 0x9654, 0xffffffff, 0x100,
480 0x9604, 0xffffffff, 0x3,
481 0x9654, 0xffffffff, 0x100,
482 0x9604, 0xffffffff, 0x4,
483 0x9654, 0xffffffff, 0x100,
484 0x9604, 0xffffffff, 0x5,
485 0x9654, 0xffffffff, 0x100,
486 0x9604, 0xffffffff, 0x6,
487 0x9654, 0xffffffff, 0x100,
488 0x9604, 0xffffffff, 0x7,
489 0x9654, 0xffffffff, 0x100,
490 0x9604, 0xffffffff, 0x80000000,
491 0x9030, 0xffffffff, 0x100,
492 0x9034, 0xffffffff, 0x100,
493 0x9038, 0xffffffff, 0x100,
494 0x903c, 0xffffffff, 0x100,
495 0x9040, 0xffffffff, 0x100,
496 0xa200, 0xffffffff, 0x100,
497 0xa204, 0xffffffff, 0x100,
498 0xa208, 0xffffffff, 0x100,
499 0xa20c, 0xffffffff, 0x100,
500 0x971c, 0xffffffff, 0x100,
501 0x915c, 0xffffffff, 0x00020001,
502 0x916c, 0xffffffff, 0x00040003,
503 0x9170, 0xffffffff, 0x00000005,
504 0x9178, 0xffffffff, 0x00050001,
505 0x917c, 0xffffffff, 0x00030002,
506 0x918c, 0xffffffff, 0x00000004,
507 0x9190, 0xffffffff, 0x00070006,
508 0x9194, 0xffffffff, 0x00050001,
509 0x9198, 0xffffffff, 0x00030002,
510 0x91a8, 0xffffffff, 0x00000004,
511 0x91ac, 0xffffffff, 0x00070006,
512 0x91b0, 0xffffffff, 0x00050001,
513 0x91b4, 0xffffffff, 0x00030002,
514 0x91c4, 0xffffffff, 0x00000004,
515 0x91c8, 0xffffffff, 0x00070006,
516 0x91cc, 0xffffffff, 0x00050001,
517 0x91d0, 0xffffffff, 0x00030002,
518 0x91e0, 0xffffffff, 0x00000004,
519 0x91e4, 0xffffffff, 0x00070006,
520 0x91e8, 0xffffffff, 0x00000001,
521 0x91ec, 0xffffffff, 0x00050001,
522 0x91f0, 0xffffffff, 0x00030002,
523 0x9200, 0xffffffff, 0x00000004,
524 0x9204, 0xffffffff, 0x00070006,
525 0x9208, 0xffffffff, 0x00050001,
526 0x920c, 0xffffffff, 0x00030002,
527 0x921c, 0xffffffff, 0x00000004,
528 0x9220, 0xffffffff, 0x00070006,
529 0x9224, 0xffffffff, 0x00050001,
530 0x9228, 0xffffffff, 0x00030002,
531 0x9238, 0xffffffff, 0x00000004,
532 0x923c, 0xffffffff, 0x00070006,
533 0x9240, 0xffffffff, 0x00050001,
534 0x9244, 0xffffffff, 0x00030002,
535 0x9254, 0xffffffff, 0x00000004,
536 0x9258, 0xffffffff, 0x00070006,
537 0x9294, 0xffffffff, 0x00000001,
538 0x929c, 0xffffffff, 0x00000002,
539 0x92a0, 0xffffffff, 0x00040003,
540 0x92a4, 0xffffffff, 0x00000005
541};
542
543static const u32 rv740_golden_registers[] =
544{
545 0x88c4, 0xffffffff, 0x00000082,
546 0x28a50, 0xfffffffc, 0x00000004,
547 0x2650, 0x00040000, 0,
548 0x20bc, 0x00040000, 0,
549 0x733c, 0xffffffff, 0x00000002,
550 0x7300, 0xffffffff, 0x001000f0,
551 0x3f90, 0x00ff0000, 0,
552 0x9148, 0x00ff0000, 0,
553 0x3f94, 0x00ff0000, 0,
554 0x914c, 0x00ff0000, 0,
555 0x240c, 0xffffffff, 0x00000380,
556 0x8a14, 0x00000007, 0x00000007,
557 0x8b24, 0xffffffff, 0x00ff0fff,
558 0x28a4c, 0xffffffff, 0x00004000,
559 0xa180, 0xffffffff, 0x00003f3f,
560 0x8d00, 0xffffffff, 0x0e0e003a,
561 0x8d04, 0xffffffff, 0x013a0e2a,
562 0x8c00, 0xffffffff, 0xe400000f,
563 0x8db0, 0xffffffff, 0x98989898,
564 0x8db4, 0xffffffff, 0x98989898,
565 0x8db8, 0xffffffff, 0x98989898,
566 0x8dbc, 0xffffffff, 0x98989898,
567 0x8dc0, 0xffffffff, 0x98989898,
568 0x8dc4, 0xffffffff, 0x98989898,
569 0x8dc8, 0xffffffff, 0x98989898,
570 0x8dcc, 0xffffffff, 0x98989898,
571 0x9058, 0xffffffff, 0x0fffc40f,
572 0x900c, 0xffffffff, 0x003b033f,
573 0x28350, 0xffffffff, 0,
574 0x8cf0, 0x1fffffff, 0x08e00420,
575 0x9508, 0xffffffff, 0x00000002,
576 0x88c4, 0xffffffff, 0x000000c2,
577 0x9698, 0x18000000, 0x18000000
578};
579
580static const u32 rv740_mgcg_init[] =
581{
582 0x8bcc, 0xffffffff, 0x13030100,
583 0x5448, 0xffffffff, 0x100,
584 0x55e4, 0xffffffff, 0x100,
585 0x160c, 0xffffffff, 0x100,
586 0x5644, 0xffffffff, 0x100,
587 0xc164, 0xffffffff, 0x100,
588 0x8a18, 0xffffffff, 0x100,
589 0x897c, 0xffffffff, 0x100,
590 0x8b28, 0xffffffff, 0x100,
591 0x9144, 0xffffffff, 0x100,
592 0x9a1c, 0xffffffff, 0x10000,
593 0x9a50, 0xffffffff, 0x100,
594 0x9a1c, 0xffffffff, 0x10001,
595 0x9a50, 0xffffffff, 0x100,
596 0x9a1c, 0xffffffff, 0x10002,
597 0x9a50, 0xffffffff, 0x100,
598 0x9a1c, 0xffffffff, 0x10003,
599 0x9a50, 0xffffffff, 0x100,
600 0x9a1c, 0xffffffff, 0x0,
601 0x9870, 0xffffffff, 0x100,
602 0x8d58, 0xffffffff, 0x100,
603 0x9500, 0xffffffff, 0x0,
604 0x9510, 0xffffffff, 0x100,
605 0x9500, 0xffffffff, 0x1,
606 0x9510, 0xffffffff, 0x100,
607 0x9500, 0xffffffff, 0x2,
608 0x9510, 0xffffffff, 0x100,
609 0x9500, 0xffffffff, 0x3,
610 0x9510, 0xffffffff, 0x100,
611 0x9500, 0xffffffff, 0x4,
612 0x9510, 0xffffffff, 0x100,
613 0x9500, 0xffffffff, 0x5,
614 0x9510, 0xffffffff, 0x100,
615 0x9500, 0xffffffff, 0x6,
616 0x9510, 0xffffffff, 0x100,
617 0x9500, 0xffffffff, 0x7,
618 0x9510, 0xffffffff, 0x100,
619 0x9500, 0xffffffff, 0x8000,
620 0x9490, 0xffffffff, 0x0,
621 0x949c, 0xffffffff, 0x100,
622 0x9490, 0xffffffff, 0x1,
623 0x949c, 0xffffffff, 0x100,
624 0x9490, 0xffffffff, 0x2,
625 0x949c, 0xffffffff, 0x100,
626 0x9490, 0xffffffff, 0x3,
627 0x949c, 0xffffffff, 0x100,
628 0x9490, 0xffffffff, 0x4,
629 0x949c, 0xffffffff, 0x100,
630 0x9490, 0xffffffff, 0x5,
631 0x949c, 0xffffffff, 0x100,
632 0x9490, 0xffffffff, 0x6,
633 0x949c, 0xffffffff, 0x100,
634 0x9490, 0xffffffff, 0x7,
635 0x949c, 0xffffffff, 0x100,
636 0x9490, 0xffffffff, 0x8000,
637 0x9604, 0xffffffff, 0x0,
638 0x9654, 0xffffffff, 0x100,
639 0x9604, 0xffffffff, 0x1,
640 0x9654, 0xffffffff, 0x100,
641 0x9604, 0xffffffff, 0x2,
642 0x9654, 0xffffffff, 0x100,
643 0x9604, 0xffffffff, 0x3,
644 0x9654, 0xffffffff, 0x100,
645 0x9604, 0xffffffff, 0x4,
646 0x9654, 0xffffffff, 0x100,
647 0x9604, 0xffffffff, 0x5,
648 0x9654, 0xffffffff, 0x100,
649 0x9604, 0xffffffff, 0x6,
650 0x9654, 0xffffffff, 0x100,
651 0x9604, 0xffffffff, 0x7,
652 0x9654, 0xffffffff, 0x100,
653 0x9604, 0xffffffff, 0x80000000,
654 0x9030, 0xffffffff, 0x100,
655 0x9034, 0xffffffff, 0x100,
656 0x9038, 0xffffffff, 0x100,
657 0x903c, 0xffffffff, 0x100,
658 0x9040, 0xffffffff, 0x100,
659 0xa200, 0xffffffff, 0x100,
660 0xa204, 0xffffffff, 0x100,
661 0xa208, 0xffffffff, 0x100,
662 0xa20c, 0xffffffff, 0x100,
663 0x971c, 0xffffffff, 0x100,
664 0x915c, 0xffffffff, 0x00020001,
665 0x9160, 0xffffffff, 0x00040003,
666 0x916c, 0xffffffff, 0x00060005,
667 0x9170, 0xffffffff, 0x00080007,
668 0x9174, 0xffffffff, 0x000a0009,
669 0x9178, 0xffffffff, 0x000c000b,
670 0x917c, 0xffffffff, 0x000e000d,
671 0x9180, 0xffffffff, 0x0010000f,
672 0x918c, 0xffffffff, 0x00120011,
673 0x9190, 0xffffffff, 0x00140013,
674 0x9194, 0xffffffff, 0x00020001,
675 0x9198, 0xffffffff, 0x00040003,
676 0x919c, 0xffffffff, 0x00060005,
677 0x91a8, 0xffffffff, 0x00080007,
678 0x91ac, 0xffffffff, 0x000a0009,
679 0x91b0, 0xffffffff, 0x000c000b,
680 0x91b4, 0xffffffff, 0x000e000d,
681 0x91b8, 0xffffffff, 0x0010000f,
682 0x91c4, 0xffffffff, 0x00120011,
683 0x91c8, 0xffffffff, 0x00140013,
684 0x91cc, 0xffffffff, 0x00020001,
685 0x91d0, 0xffffffff, 0x00040003,
686 0x91d4, 0xffffffff, 0x00060005,
687 0x91e0, 0xffffffff, 0x00080007,
688 0x91e4, 0xffffffff, 0x000a0009,
689 0x91e8, 0xffffffff, 0x000c000b,
690 0x91ec, 0xffffffff, 0x00020001,
691 0x91f0, 0xffffffff, 0x00040003,
692 0x91f4, 0xffffffff, 0x00060005,
693 0x9200, 0xffffffff, 0x00080007,
694 0x9204, 0xffffffff, 0x000a0009,
695 0x9208, 0xffffffff, 0x000c000b,
696 0x920c, 0xffffffff, 0x000e000d,
697 0x9210, 0xffffffff, 0x0010000f,
698 0x921c, 0xffffffff, 0x00120011,
699 0x9220, 0xffffffff, 0x00140013,
700 0x9224, 0xffffffff, 0x00020001,
701 0x9228, 0xffffffff, 0x00040003,
702 0x922c, 0xffffffff, 0x00060005,
703 0x9238, 0xffffffff, 0x00080007,
704 0x923c, 0xffffffff, 0x000a0009,
705 0x9240, 0xffffffff, 0x000c000b,
706 0x9244, 0xffffffff, 0x000e000d,
707 0x9248, 0xffffffff, 0x0010000f,
708 0x9254, 0xffffffff, 0x00120011,
709 0x9258, 0xffffffff, 0x00140013,
710 0x9294, 0xffffffff, 0x00020001,
711 0x929c, 0xffffffff, 0x00040003,
712 0x92a0, 0xffffffff, 0x00060005,
713 0x92a4, 0xffffffff, 0x00080007
714};
715
716static void rv770_init_golden_registers(struct radeon_device *rdev)
717{
718 switch (rdev->family) {
719 case CHIP_RV770:
720 radeon_program_register_sequence(rdev,
721 r7xx_golden_registers,
722 (const u32)ARRAY_SIZE(r7xx_golden_registers));
723 radeon_program_register_sequence(rdev,
724 r7xx_golden_dyn_gpr_registers,
725 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
726 if (rdev->pdev->device == 0x994e)
727 radeon_program_register_sequence(rdev,
728 rv770ce_golden_registers,
729 (const u32)ARRAY_SIZE(rv770ce_golden_registers));
730 else
731 radeon_program_register_sequence(rdev,
732 rv770_golden_registers,
733 (const u32)ARRAY_SIZE(rv770_golden_registers));
734 radeon_program_register_sequence(rdev,
735 rv770_mgcg_init,
736 (const u32)ARRAY_SIZE(rv770_mgcg_init));
737 break;
738 case CHIP_RV730:
739 radeon_program_register_sequence(rdev,
740 r7xx_golden_registers,
741 (const u32)ARRAY_SIZE(r7xx_golden_registers));
742 radeon_program_register_sequence(rdev,
743 r7xx_golden_dyn_gpr_registers,
744 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
745 radeon_program_register_sequence(rdev,
746 rv730_golden_registers,
747 (const u32)ARRAY_SIZE(rv770_golden_registers));
748 radeon_program_register_sequence(rdev,
749 rv730_mgcg_init,
750 (const u32)ARRAY_SIZE(rv770_mgcg_init));
751 break;
752 case CHIP_RV710:
753 radeon_program_register_sequence(rdev,
754 r7xx_golden_registers,
755 (const u32)ARRAY_SIZE(r7xx_golden_registers));
756 radeon_program_register_sequence(rdev,
757 r7xx_golden_dyn_gpr_registers,
758 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
759 radeon_program_register_sequence(rdev,
760 rv710_golden_registers,
761 (const u32)ARRAY_SIZE(rv770_golden_registers));
762 radeon_program_register_sequence(rdev,
763 rv710_mgcg_init,
764 (const u32)ARRAY_SIZE(rv770_mgcg_init));
765 break;
766 case CHIP_RV740:
767 radeon_program_register_sequence(rdev,
768 rv740_golden_registers,
769 (const u32)ARRAY_SIZE(rv770_golden_registers));
770 radeon_program_register_sequence(rdev,
771 rv740_mgcg_init,
772 (const u32)ARRAY_SIZE(rv770_mgcg_init));
773 break;
774 default:
775 break;
776 }
777}
45 778
46#define PCIE_BUS_CLK 10000 779#define PCIE_BUS_CLK 10000
47#define TCLK (PCIE_BUS_CLK / 10) 780#define TCLK (PCIE_BUS_CLK / 10)
@@ -68,6 +801,105 @@ u32 rv770_get_xclk(struct radeon_device *rdev)
68 return reference_clock; 801 return reference_clock;
69} 802}
70 803
804int rv770_uvd_resume(struct radeon_device *rdev)
805{
806 uint64_t addr;
807 uint32_t chip_id, size;
808 int r;
809
810 r = radeon_uvd_resume(rdev);
811 if (r)
812 return r;
813
814 /* programm the VCPU memory controller bits 0-27 */
815 addr = rdev->uvd.gpu_addr >> 3;
816 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
817 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
818 WREG32(UVD_VCPU_CACHE_SIZE0, size);
819
820 addr += size;
821 size = RADEON_UVD_STACK_SIZE >> 3;
822 WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
823 WREG32(UVD_VCPU_CACHE_SIZE1, size);
824
825 addr += size;
826 size = RADEON_UVD_HEAP_SIZE >> 3;
827 WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
828 WREG32(UVD_VCPU_CACHE_SIZE2, size);
829
830 /* bits 28-31 */
831 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
832 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
833
834 /* bits 32-39 */
835 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
836 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
837
838 /* tell firmware which hardware it is running on */
839 switch (rdev->family) {
840 default:
841 return -EINVAL;
842 case CHIP_RV710:
843 chip_id = 0x01000005;
844 break;
845 case CHIP_RV730:
846 chip_id = 0x01000006;
847 break;
848 case CHIP_RV740:
849 chip_id = 0x01000007;
850 break;
851 case CHIP_CYPRESS:
852 case CHIP_HEMLOCK:
853 chip_id = 0x01000008;
854 break;
855 case CHIP_JUNIPER:
856 chip_id = 0x01000009;
857 break;
858 case CHIP_REDWOOD:
859 chip_id = 0x0100000a;
860 break;
861 case CHIP_CEDAR:
862 chip_id = 0x0100000b;
863 break;
864 case CHIP_SUMO:
865 chip_id = 0x0100000c;
866 break;
867 case CHIP_SUMO2:
868 chip_id = 0x0100000d;
869 break;
870 case CHIP_PALM:
871 chip_id = 0x0100000e;
872 break;
873 case CHIP_CAYMAN:
874 chip_id = 0x0100000f;
875 break;
876 case CHIP_BARTS:
877 chip_id = 0x01000010;
878 break;
879 case CHIP_TURKS:
880 chip_id = 0x01000011;
881 break;
882 case CHIP_CAICOS:
883 chip_id = 0x01000012;
884 break;
885 case CHIP_TAHITI:
886 chip_id = 0x01000014;
887 break;
888 case CHIP_VERDE:
889 chip_id = 0x01000015;
890 break;
891 case CHIP_PITCAIRN:
892 chip_id = 0x01000016;
893 break;
894 case CHIP_ARUBA:
895 chip_id = 0x01000017;
896 break;
897 }
898 WREG32(UVD_VCPU_CHIP_ID, chip_id);
899
900 return 0;
901}
902
71u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 903u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
72{ 904{
73 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 905 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
@@ -611,6 +1443,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
611 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1443 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
612 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1444 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
613 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); 1445 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
1446 if (rdev->family == CHIP_RV730) {
1447 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
1448 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
1449 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
1450 }
614 1451
615 WREG32(CGTS_SYS_TCC_DISABLE, 0); 1452 WREG32(CGTS_SYS_TCC_DISABLE, 0);
616 WREG32(CGTS_TCC_DISABLE, 0); 1453 WREG32(CGTS_TCC_DISABLE, 0);
@@ -840,7 +1677,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
840 } 1677 }
841 if (rdev->flags & RADEON_IS_AGP) { 1678 if (rdev->flags & RADEON_IS_AGP) {
842 size_bf = mc->gtt_start; 1679 size_bf = mc->gtt_start;
843 size_af = 0xFFFFFFFF - mc->gtt_end; 1680 size_af = mc->mc_mask - mc->gtt_end;
844 if (size_bf > size_af) { 1681 if (size_bf > size_af) {
845 if (mc->mc_vram_size > size_bf) { 1682 if (mc->mc_vram_size > size_bf) {
846 dev_warn(rdev->dev, "limiting VRAM\n"); 1683 dev_warn(rdev->dev, "limiting VRAM\n");
@@ -1040,6 +1877,17 @@ static int rv770_startup(struct radeon_device *rdev)
1040 return r; 1877 return r;
1041 } 1878 }
1042 1879
1880 r = rv770_uvd_resume(rdev);
1881 if (!r) {
1882 r = radeon_fence_driver_start_ring(rdev,
1883 R600_RING_TYPE_UVD_INDEX);
1884 if (r)
1885 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1886 }
1887
1888 if (r)
1889 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1890
1043 /* Enable IRQ */ 1891 /* Enable IRQ */
1044 r = r600_irq_init(rdev); 1892 r = r600_irq_init(rdev);
1045 if (r) { 1893 if (r) {
@@ -1074,6 +1922,19 @@ static int rv770_startup(struct radeon_device *rdev)
1074 if (r) 1922 if (r)
1075 return r; 1923 return r;
1076 1924
1925 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1926 if (ring->ring_size) {
1927 r = radeon_ring_init(rdev, ring, ring->ring_size,
1928 R600_WB_UVD_RPTR_OFFSET,
1929 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
1930 0, 0xfffff, RADEON_CP_PACKET2);
1931 if (!r)
1932 r = r600_uvd_init(rdev);
1933
1934 if (r)
1935 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
1936 }
1937
1077 r = radeon_ib_pool_init(rdev); 1938 r = radeon_ib_pool_init(rdev);
1078 if (r) { 1939 if (r) {
1079 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1940 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -1100,6 +1961,9 @@ int rv770_resume(struct radeon_device *rdev)
1100 /* post card */ 1961 /* post card */
1101 atom_asic_init(rdev->mode_info.atom_context); 1962 atom_asic_init(rdev->mode_info.atom_context);
1102 1963
1964 /* init golden registers */
1965 rv770_init_golden_registers(rdev);
1966
1103 rdev->accel_working = true; 1967 rdev->accel_working = true;
1104 r = rv770_startup(rdev); 1968 r = rv770_startup(rdev);
1105 if (r) { 1969 if (r) {
@@ -1115,6 +1979,7 @@ int rv770_resume(struct radeon_device *rdev)
1115int rv770_suspend(struct radeon_device *rdev) 1979int rv770_suspend(struct radeon_device *rdev)
1116{ 1980{
1117 r600_audio_fini(rdev); 1981 r600_audio_fini(rdev);
1982 radeon_uvd_suspend(rdev);
1118 r700_cp_stop(rdev); 1983 r700_cp_stop(rdev);
1119 r600_dma_stop(rdev); 1984 r600_dma_stop(rdev);
1120 r600_irq_suspend(rdev); 1985 r600_irq_suspend(rdev);
@@ -1156,6 +2021,8 @@ int rv770_init(struct radeon_device *rdev)
1156 DRM_INFO("GPU not posted. posting now...\n"); 2021 DRM_INFO("GPU not posted. posting now...\n");
1157 atom_asic_init(rdev->mode_info.atom_context); 2022 atom_asic_init(rdev->mode_info.atom_context);
1158 } 2023 }
2024 /* init golden registers */
2025 rv770_init_golden_registers(rdev);
1159 /* Initialize scratch registers */ 2026 /* Initialize scratch registers */
1160 r600_scratch_init(rdev); 2027 r600_scratch_init(rdev);
1161 /* Initialize surface registers */ 2028 /* Initialize surface registers */
@@ -1190,6 +2057,13 @@ int rv770_init(struct radeon_device *rdev)
1190 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 2057 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
1191 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 2058 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
1192 2059
2060 r = radeon_uvd_init(rdev);
2061 if (!r) {
2062 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
2063 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
2064 4096);
2065 }
2066
1193 rdev->ih.ring_obj = NULL; 2067 rdev->ih.ring_obj = NULL;
1194 r600_ih_ring_init(rdev, 64 * 1024); 2068 r600_ih_ring_init(rdev, 64 * 1024);
1195 2069
@@ -1224,6 +2098,7 @@ void rv770_fini(struct radeon_device *rdev)
1224 radeon_ib_pool_fini(rdev); 2098 radeon_ib_pool_fini(rdev);
1225 radeon_irq_kms_fini(rdev); 2099 radeon_irq_kms_fini(rdev);
1226 rv770_pcie_gart_fini(rdev); 2100 rv770_pcie_gart_fini(rdev);
2101 radeon_uvd_fini(rdev);
1227 r600_vram_scratch_fini(rdev); 2102 r600_vram_scratch_fini(rdev);
1228 radeon_gem_fini(rdev); 2103 radeon_gem_fini(rdev);
1229 radeon_fence_driver_fini(rdev); 2104 radeon_fence_driver_fini(rdev);
@@ -1264,23 +2139,23 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1264 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 2139 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
1265 2140
1266 /* advertise upconfig capability */ 2141 /* advertise upconfig capability */
1267 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 2142 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1268 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 2143 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1269 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2144 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1270 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 2145 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1271 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 2146 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1272 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 2147 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1273 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 2148 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1274 LC_RECONFIG_ARC_MISSING_ESCAPE); 2149 LC_RECONFIG_ARC_MISSING_ESCAPE);
1275 link_width_cntl |= lanes | LC_RECONFIG_NOW | 2150 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1276 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; 2151 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1277 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2152 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1278 } else { 2153 } else {
1279 link_width_cntl |= LC_UPCONFIGURE_DIS; 2154 link_width_cntl |= LC_UPCONFIGURE_DIS;
1280 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2155 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1281 } 2156 }
1282 2157
1283 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 2158 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1284 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 2159 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1285 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 2160 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1286 2161
@@ -1293,29 +2168,29 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1293 WREG16(0x4088, link_cntl2); 2168 WREG16(0x4088, link_cntl2);
1294 WREG32(MM_CFGREGS_CNTL, 0); 2169 WREG32(MM_CFGREGS_CNTL, 0);
1295 2170
1296 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 2171 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1297 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 2172 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1298 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 2173 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1299 2174
1300 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 2175 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1301 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 2176 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1302 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 2177 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1303 2178
1304 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 2179 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1305 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 2180 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1306 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 2181 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1307 2182
1308 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 2183 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1309 speed_cntl |= LC_GEN2_EN_STRAP; 2184 speed_cntl |= LC_GEN2_EN_STRAP;
1310 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 2185 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1311 2186
1312 } else { 2187 } else {
1313 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 2188 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1314 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 2189 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1315 if (1) 2190 if (1)
1316 link_width_cntl |= LC_UPCONFIGURE_DIS; 2191 link_width_cntl |= LC_UPCONFIGURE_DIS;
1317 else 2192 else
1318 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 2193 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1319 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 2194 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1320 } 2195 }
1321} 2196}
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index c55f950a4af7..85b16266f748 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -38,6 +38,30 @@
38#define R7XX_MAX_PIPES 8 38#define R7XX_MAX_PIPES 8
39#define R7XX_MAX_PIPES_MASK 0xff 39#define R7XX_MAX_PIPES_MASK 0xff
40 40
41/* discrete uvd clocks */
42#define CG_UPLL_FUNC_CNTL 0x718
43# define UPLL_RESET_MASK 0x00000001
44# define UPLL_SLEEP_MASK 0x00000002
45# define UPLL_BYPASS_EN_MASK 0x00000004
46# define UPLL_CTLREQ_MASK 0x00000008
47# define UPLL_REF_DIV(x) ((x) << 16)
48# define UPLL_REF_DIV_MASK 0x003F0000
49# define UPLL_CTLACK_MASK 0x40000000
50# define UPLL_CTLACK2_MASK 0x80000000
51#define CG_UPLL_FUNC_CNTL_2 0x71c
52# define UPLL_SW_HILEN(x) ((x) << 0)
53# define UPLL_SW_LOLEN(x) ((x) << 4)
54# define UPLL_SW_HILEN2(x) ((x) << 8)
55# define UPLL_SW_LOLEN2(x) ((x) << 12)
56# define UPLL_SW_MASK 0x0000FFFF
57# define VCLK_SRC_SEL(x) ((x) << 20)
58# define VCLK_SRC_SEL_MASK 0x01F00000
59# define DCLK_SRC_SEL(x) ((x) << 25)
60# define DCLK_SRC_SEL_MASK 0x3E000000
61#define CG_UPLL_FUNC_CNTL_3 0x720
62# define UPLL_FB_DIV(x) ((x) << 0)
63# define UPLL_FB_DIV_MASK 0x01FFFFFF
64
41/* Registers */ 65/* Registers */
42#define CB_COLOR0_BASE 0x28040 66#define CB_COLOR0_BASE 0x28040
43#define CB_COLOR1_BASE 0x28044 67#define CB_COLOR1_BASE 0x28044
@@ -112,6 +136,11 @@
112#define DMA_TILING_CONFIG 0x3ec8 136#define DMA_TILING_CONFIG 0x3ec8
113#define DMA_TILING_CONFIG2 0xd0b8 137#define DMA_TILING_CONFIG2 0xd0b8
114 138
139/* RV730 only */
140#define UVD_UDEC_TILING_CONFIG 0xef40
141#define UVD_UDEC_DB_TILING_CONFIG 0xef44
142#define UVD_UDEC_DBW_TILING_CONFIG 0xef48
143
115#define GC_USER_SHADER_PIPE_CONFIG 0x8954 144#define GC_USER_SHADER_PIPE_CONFIG 0x8954
116#define INACTIVE_QD_PIPES(x) ((x) << 8) 145#define INACTIVE_QD_PIPES(x) ((x) << 8)
117#define INACTIVE_QD_PIPES_MASK 0x0000FF00 146#define INACTIVE_QD_PIPES_MASK 0x0000FF00
@@ -671,4 +700,18 @@
671# define TARGET_LINK_SPEED_MASK (0xf << 0) 700# define TARGET_LINK_SPEED_MASK (0xf << 0)
672# define SELECTABLE_DEEMPHASIS (1 << 6) 701# define SELECTABLE_DEEMPHASIS (1 << 6)
673 702
703/* UVD */
704#define UVD_LMI_EXT40_ADDR 0xf498
705#define UVD_VCPU_CHIP_ID 0xf4d4
706#define UVD_VCPU_CACHE_OFFSET0 0xf4d8
707#define UVD_VCPU_CACHE_SIZE0 0xf4dc
708#define UVD_VCPU_CACHE_OFFSET1 0xf4e0
709#define UVD_VCPU_CACHE_SIZE1 0xf4e4
710#define UVD_VCPU_CACHE_OFFSET2 0xf4e8
711#define UVD_VCPU_CACHE_SIZE2 0xf4ec
712#define UVD_LMI_ADDR_EXT 0xf594
713
714#define UVD_RBC_RB_RPTR 0xf690
715#define UVD_RBC_RB_WPTR 0xf694
716
674#endif 717#endif
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index bafbe3216952..f0b6c2f87c4d 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -70,6 +70,794 @@ extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
70extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 70extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
71extern bool evergreen_is_display_hung(struct radeon_device *rdev); 71extern bool evergreen_is_display_hung(struct radeon_device *rdev);
72 72
73static const u32 tahiti_golden_rlc_registers[] =
74{
75 0xc424, 0xffffffff, 0x00601005,
76 0xc47c, 0xffffffff, 0x10104040,
77 0xc488, 0xffffffff, 0x0100000a,
78 0xc314, 0xffffffff, 0x00000800,
79 0xc30c, 0xffffffff, 0x800000f4,
80 0xf4a8, 0xffffffff, 0x00000000
81};
82
83static const u32 tahiti_golden_registers[] =
84{
85 0x9a10, 0x00010000, 0x00018208,
86 0x9830, 0xffffffff, 0x00000000,
87 0x9834, 0xf00fffff, 0x00000400,
88 0x9838, 0x0002021c, 0x00020200,
89 0xc78, 0x00000080, 0x00000000,
90 0xd030, 0x000300c0, 0x00800040,
91 0xd830, 0x000300c0, 0x00800040,
92 0x5bb0, 0x000000f0, 0x00000070,
93 0x5bc0, 0x00200000, 0x50100000,
94 0x7030, 0x31000311, 0x00000011,
95 0x277c, 0x00000003, 0x000007ff,
96 0x240c, 0x000007ff, 0x00000000,
97 0x8a14, 0xf000001f, 0x00000007,
98 0x8b24, 0xffffffff, 0x00ffffff,
99 0x8b10, 0x0000ff0f, 0x00000000,
100 0x28a4c, 0x07ffffff, 0x4e000000,
101 0x28350, 0x3f3f3fff, 0x2a00126a,
102 0x30, 0x000000ff, 0x0040,
103 0x34, 0x00000040, 0x00004040,
104 0x9100, 0x07ffffff, 0x03000000,
105 0x8e88, 0x01ff1f3f, 0x00000000,
106 0x8e84, 0x01ff1f3f, 0x00000000,
107 0x9060, 0x0000007f, 0x00000020,
108 0x9508, 0x00010000, 0x00010000,
109 0xac14, 0x00000200, 0x000002fb,
110 0xac10, 0xffffffff, 0x0000543b,
111 0xac0c, 0xffffffff, 0xa9210876,
112 0x88d0, 0xffffffff, 0x000fff40,
113 0x88d4, 0x0000001f, 0x00000010,
114 0x1410, 0x20000000, 0x20fffed8,
115 0x15c0, 0x000c0fc0, 0x000c0400
116};
117
118static const u32 tahiti_golden_registers2[] =
119{
120 0xc64, 0x00000001, 0x00000001
121};
122
123static const u32 pitcairn_golden_rlc_registers[] =
124{
125 0xc424, 0xffffffff, 0x00601004,
126 0xc47c, 0xffffffff, 0x10102020,
127 0xc488, 0xffffffff, 0x01000020,
128 0xc314, 0xffffffff, 0x00000800,
129 0xc30c, 0xffffffff, 0x800000a4
130};
131
132static const u32 pitcairn_golden_registers[] =
133{
134 0x9a10, 0x00010000, 0x00018208,
135 0x9830, 0xffffffff, 0x00000000,
136 0x9834, 0xf00fffff, 0x00000400,
137 0x9838, 0x0002021c, 0x00020200,
138 0xc78, 0x00000080, 0x00000000,
139 0xd030, 0x000300c0, 0x00800040,
140 0xd830, 0x000300c0, 0x00800040,
141 0x5bb0, 0x000000f0, 0x00000070,
142 0x5bc0, 0x00200000, 0x50100000,
143 0x7030, 0x31000311, 0x00000011,
144 0x2ae4, 0x00073ffe, 0x000022a2,
145 0x240c, 0x000007ff, 0x00000000,
146 0x8a14, 0xf000001f, 0x00000007,
147 0x8b24, 0xffffffff, 0x00ffffff,
148 0x8b10, 0x0000ff0f, 0x00000000,
149 0x28a4c, 0x07ffffff, 0x4e000000,
150 0x28350, 0x3f3f3fff, 0x2a00126a,
151 0x30, 0x000000ff, 0x0040,
152 0x34, 0x00000040, 0x00004040,
153 0x9100, 0x07ffffff, 0x03000000,
154 0x9060, 0x0000007f, 0x00000020,
155 0x9508, 0x00010000, 0x00010000,
156 0xac14, 0x000003ff, 0x000000f7,
157 0xac10, 0xffffffff, 0x00000000,
158 0xac0c, 0xffffffff, 0x32761054,
159 0x88d4, 0x0000001f, 0x00000010,
160 0x15c0, 0x000c0fc0, 0x000c0400
161};
162
163static const u32 verde_golden_rlc_registers[] =
164{
165 0xc424, 0xffffffff, 0x033f1005,
166 0xc47c, 0xffffffff, 0x10808020,
167 0xc488, 0xffffffff, 0x00800008,
168 0xc314, 0xffffffff, 0x00001000,
169 0xc30c, 0xffffffff, 0x80010014
170};
171
172static const u32 verde_golden_registers[] =
173{
174 0x9a10, 0x00010000, 0x00018208,
175 0x9830, 0xffffffff, 0x00000000,
176 0x9834, 0xf00fffff, 0x00000400,
177 0x9838, 0x0002021c, 0x00020200,
178 0xc78, 0x00000080, 0x00000000,
179 0xd030, 0x000300c0, 0x00800040,
180 0xd030, 0x000300c0, 0x00800040,
181 0xd830, 0x000300c0, 0x00800040,
182 0xd830, 0x000300c0, 0x00800040,
183 0x5bb0, 0x000000f0, 0x00000070,
184 0x5bc0, 0x00200000, 0x50100000,
185 0x7030, 0x31000311, 0x00000011,
186 0x2ae4, 0x00073ffe, 0x000022a2,
187 0x2ae4, 0x00073ffe, 0x000022a2,
188 0x2ae4, 0x00073ffe, 0x000022a2,
189 0x240c, 0x000007ff, 0x00000000,
190 0x240c, 0x000007ff, 0x00000000,
191 0x240c, 0x000007ff, 0x00000000,
192 0x8a14, 0xf000001f, 0x00000007,
193 0x8a14, 0xf000001f, 0x00000007,
194 0x8a14, 0xf000001f, 0x00000007,
195 0x8b24, 0xffffffff, 0x00ffffff,
196 0x8b10, 0x0000ff0f, 0x00000000,
197 0x28a4c, 0x07ffffff, 0x4e000000,
198 0x28350, 0x3f3f3fff, 0x0000124a,
199 0x28350, 0x3f3f3fff, 0x0000124a,
200 0x28350, 0x3f3f3fff, 0x0000124a,
201 0x30, 0x000000ff, 0x0040,
202 0x34, 0x00000040, 0x00004040,
203 0x9100, 0x07ffffff, 0x03000000,
204 0x9100, 0x07ffffff, 0x03000000,
205 0x8e88, 0x01ff1f3f, 0x00000000,
206 0x8e88, 0x01ff1f3f, 0x00000000,
207 0x8e88, 0x01ff1f3f, 0x00000000,
208 0x8e84, 0x01ff1f3f, 0x00000000,
209 0x8e84, 0x01ff1f3f, 0x00000000,
210 0x8e84, 0x01ff1f3f, 0x00000000,
211 0x9060, 0x0000007f, 0x00000020,
212 0x9508, 0x00010000, 0x00010000,
213 0xac14, 0x000003ff, 0x00000003,
214 0xac14, 0x000003ff, 0x00000003,
215 0xac14, 0x000003ff, 0x00000003,
216 0xac10, 0xffffffff, 0x00000000,
217 0xac10, 0xffffffff, 0x00000000,
218 0xac10, 0xffffffff, 0x00000000,
219 0xac0c, 0xffffffff, 0x00001032,
220 0xac0c, 0xffffffff, 0x00001032,
221 0xac0c, 0xffffffff, 0x00001032,
222 0x88d4, 0x0000001f, 0x00000010,
223 0x88d4, 0x0000001f, 0x00000010,
224 0x88d4, 0x0000001f, 0x00000010,
225 0x15c0, 0x000c0fc0, 0x000c0400
226};
227
228static const u32 oland_golden_rlc_registers[] =
229{
230 0xc424, 0xffffffff, 0x00601005,
231 0xc47c, 0xffffffff, 0x10104040,
232 0xc488, 0xffffffff, 0x0100000a,
233 0xc314, 0xffffffff, 0x00000800,
234 0xc30c, 0xffffffff, 0x800000f4
235};
236
237static const u32 oland_golden_registers[] =
238{
239 0x9a10, 0x00010000, 0x00018208,
240 0x9830, 0xffffffff, 0x00000000,
241 0x9834, 0xf00fffff, 0x00000400,
242 0x9838, 0x0002021c, 0x00020200,
243 0xc78, 0x00000080, 0x00000000,
244 0xd030, 0x000300c0, 0x00800040,
245 0xd830, 0x000300c0, 0x00800040,
246 0x5bb0, 0x000000f0, 0x00000070,
247 0x5bc0, 0x00200000, 0x50100000,
248 0x7030, 0x31000311, 0x00000011,
249 0x2ae4, 0x00073ffe, 0x000022a2,
250 0x240c, 0x000007ff, 0x00000000,
251 0x8a14, 0xf000001f, 0x00000007,
252 0x8b24, 0xffffffff, 0x00ffffff,
253 0x8b10, 0x0000ff0f, 0x00000000,
254 0x28a4c, 0x07ffffff, 0x4e000000,
255 0x28350, 0x3f3f3fff, 0x00000082,
256 0x30, 0x000000ff, 0x0040,
257 0x34, 0x00000040, 0x00004040,
258 0x9100, 0x07ffffff, 0x03000000,
259 0x9060, 0x0000007f, 0x00000020,
260 0x9508, 0x00010000, 0x00010000,
261 0xac14, 0x000003ff, 0x000000f3,
262 0xac10, 0xffffffff, 0x00000000,
263 0xac0c, 0xffffffff, 0x00003210,
264 0x88d4, 0x0000001f, 0x00000010,
265 0x15c0, 0x000c0fc0, 0x000c0400
266};
267
268static const u32 tahiti_mgcg_cgcg_init[] =
269{
270 0xc400, 0xffffffff, 0xfffffffc,
271 0x802c, 0xffffffff, 0xe0000000,
272 0x9a60, 0xffffffff, 0x00000100,
273 0x92a4, 0xffffffff, 0x00000100,
274 0xc164, 0xffffffff, 0x00000100,
275 0x9774, 0xffffffff, 0x00000100,
276 0x8984, 0xffffffff, 0x06000100,
277 0x8a18, 0xffffffff, 0x00000100,
278 0x92a0, 0xffffffff, 0x00000100,
279 0xc380, 0xffffffff, 0x00000100,
280 0x8b28, 0xffffffff, 0x00000100,
281 0x9144, 0xffffffff, 0x00000100,
282 0x8d88, 0xffffffff, 0x00000100,
283 0x8d8c, 0xffffffff, 0x00000100,
284 0x9030, 0xffffffff, 0x00000100,
285 0x9034, 0xffffffff, 0x00000100,
286 0x9038, 0xffffffff, 0x00000100,
287 0x903c, 0xffffffff, 0x00000100,
288 0xad80, 0xffffffff, 0x00000100,
289 0xac54, 0xffffffff, 0x00000100,
290 0x897c, 0xffffffff, 0x06000100,
291 0x9868, 0xffffffff, 0x00000100,
292 0x9510, 0xffffffff, 0x00000100,
293 0xaf04, 0xffffffff, 0x00000100,
294 0xae04, 0xffffffff, 0x00000100,
295 0x949c, 0xffffffff, 0x00000100,
296 0x802c, 0xffffffff, 0xe0000000,
297 0x9160, 0xffffffff, 0x00010000,
298 0x9164, 0xffffffff, 0x00030002,
299 0x9168, 0xffffffff, 0x00040007,
300 0x916c, 0xffffffff, 0x00060005,
301 0x9170, 0xffffffff, 0x00090008,
302 0x9174, 0xffffffff, 0x00020001,
303 0x9178, 0xffffffff, 0x00040003,
304 0x917c, 0xffffffff, 0x00000007,
305 0x9180, 0xffffffff, 0x00060005,
306 0x9184, 0xffffffff, 0x00090008,
307 0x9188, 0xffffffff, 0x00030002,
308 0x918c, 0xffffffff, 0x00050004,
309 0x9190, 0xffffffff, 0x00000008,
310 0x9194, 0xffffffff, 0x00070006,
311 0x9198, 0xffffffff, 0x000a0009,
312 0x919c, 0xffffffff, 0x00040003,
313 0x91a0, 0xffffffff, 0x00060005,
314 0x91a4, 0xffffffff, 0x00000009,
315 0x91a8, 0xffffffff, 0x00080007,
316 0x91ac, 0xffffffff, 0x000b000a,
317 0x91b0, 0xffffffff, 0x00050004,
318 0x91b4, 0xffffffff, 0x00070006,
319 0x91b8, 0xffffffff, 0x0008000b,
320 0x91bc, 0xffffffff, 0x000a0009,
321 0x91c0, 0xffffffff, 0x000d000c,
322 0x91c4, 0xffffffff, 0x00060005,
323 0x91c8, 0xffffffff, 0x00080007,
324 0x91cc, 0xffffffff, 0x0000000b,
325 0x91d0, 0xffffffff, 0x000a0009,
326 0x91d4, 0xffffffff, 0x000d000c,
327 0x91d8, 0xffffffff, 0x00070006,
328 0x91dc, 0xffffffff, 0x00090008,
329 0x91e0, 0xffffffff, 0x0000000c,
330 0x91e4, 0xffffffff, 0x000b000a,
331 0x91e8, 0xffffffff, 0x000e000d,
332 0x91ec, 0xffffffff, 0x00080007,
333 0x91f0, 0xffffffff, 0x000a0009,
334 0x91f4, 0xffffffff, 0x0000000d,
335 0x91f8, 0xffffffff, 0x000c000b,
336 0x91fc, 0xffffffff, 0x000f000e,
337 0x9200, 0xffffffff, 0x00090008,
338 0x9204, 0xffffffff, 0x000b000a,
339 0x9208, 0xffffffff, 0x000c000f,
340 0x920c, 0xffffffff, 0x000e000d,
341 0x9210, 0xffffffff, 0x00110010,
342 0x9214, 0xffffffff, 0x000a0009,
343 0x9218, 0xffffffff, 0x000c000b,
344 0x921c, 0xffffffff, 0x0000000f,
345 0x9220, 0xffffffff, 0x000e000d,
346 0x9224, 0xffffffff, 0x00110010,
347 0x9228, 0xffffffff, 0x000b000a,
348 0x922c, 0xffffffff, 0x000d000c,
349 0x9230, 0xffffffff, 0x00000010,
350 0x9234, 0xffffffff, 0x000f000e,
351 0x9238, 0xffffffff, 0x00120011,
352 0x923c, 0xffffffff, 0x000c000b,
353 0x9240, 0xffffffff, 0x000e000d,
354 0x9244, 0xffffffff, 0x00000011,
355 0x9248, 0xffffffff, 0x0010000f,
356 0x924c, 0xffffffff, 0x00130012,
357 0x9250, 0xffffffff, 0x000d000c,
358 0x9254, 0xffffffff, 0x000f000e,
359 0x9258, 0xffffffff, 0x00100013,
360 0x925c, 0xffffffff, 0x00120011,
361 0x9260, 0xffffffff, 0x00150014,
362 0x9264, 0xffffffff, 0x000e000d,
363 0x9268, 0xffffffff, 0x0010000f,
364 0x926c, 0xffffffff, 0x00000013,
365 0x9270, 0xffffffff, 0x00120011,
366 0x9274, 0xffffffff, 0x00150014,
367 0x9278, 0xffffffff, 0x000f000e,
368 0x927c, 0xffffffff, 0x00110010,
369 0x9280, 0xffffffff, 0x00000014,
370 0x9284, 0xffffffff, 0x00130012,
371 0x9288, 0xffffffff, 0x00160015,
372 0x928c, 0xffffffff, 0x0010000f,
373 0x9290, 0xffffffff, 0x00120011,
374 0x9294, 0xffffffff, 0x00000015,
375 0x9298, 0xffffffff, 0x00140013,
376 0x929c, 0xffffffff, 0x00170016,
377 0x9150, 0xffffffff, 0x96940200,
378 0x8708, 0xffffffff, 0x00900100,
379 0xc478, 0xffffffff, 0x00000080,
380 0xc404, 0xffffffff, 0x0020003f,
381 0x30, 0xffffffff, 0x0000001c,
382 0x34, 0x000f0000, 0x000f0000,
383 0x160c, 0xffffffff, 0x00000100,
384 0x1024, 0xffffffff, 0x00000100,
385 0x102c, 0x00000101, 0x00000000,
386 0x20a8, 0xffffffff, 0x00000104,
387 0x264c, 0x000c0000, 0x000c0000,
388 0x2648, 0x000c0000, 0x000c0000,
389 0x55e4, 0xff000fff, 0x00000100,
390 0x55e8, 0x00000001, 0x00000001,
391 0x2f50, 0x00000001, 0x00000001,
392 0x30cc, 0xc0000fff, 0x00000104,
393 0xc1e4, 0x00000001, 0x00000001,
394 0xd0c0, 0xfffffff0, 0x00000100,
395 0xd8c0, 0xfffffff0, 0x00000100
396};
397
398static const u32 pitcairn_mgcg_cgcg_init[] =
399{
400 0xc400, 0xffffffff, 0xfffffffc,
401 0x802c, 0xffffffff, 0xe0000000,
402 0x9a60, 0xffffffff, 0x00000100,
403 0x92a4, 0xffffffff, 0x00000100,
404 0xc164, 0xffffffff, 0x00000100,
405 0x9774, 0xffffffff, 0x00000100,
406 0x8984, 0xffffffff, 0x06000100,
407 0x8a18, 0xffffffff, 0x00000100,
408 0x92a0, 0xffffffff, 0x00000100,
409 0xc380, 0xffffffff, 0x00000100,
410 0x8b28, 0xffffffff, 0x00000100,
411 0x9144, 0xffffffff, 0x00000100,
412 0x8d88, 0xffffffff, 0x00000100,
413 0x8d8c, 0xffffffff, 0x00000100,
414 0x9030, 0xffffffff, 0x00000100,
415 0x9034, 0xffffffff, 0x00000100,
416 0x9038, 0xffffffff, 0x00000100,
417 0x903c, 0xffffffff, 0x00000100,
418 0xad80, 0xffffffff, 0x00000100,
419 0xac54, 0xffffffff, 0x00000100,
420 0x897c, 0xffffffff, 0x06000100,
421 0x9868, 0xffffffff, 0x00000100,
422 0x9510, 0xffffffff, 0x00000100,
423 0xaf04, 0xffffffff, 0x00000100,
424 0xae04, 0xffffffff, 0x00000100,
425 0x949c, 0xffffffff, 0x00000100,
426 0x802c, 0xffffffff, 0xe0000000,
427 0x9160, 0xffffffff, 0x00010000,
428 0x9164, 0xffffffff, 0x00030002,
429 0x9168, 0xffffffff, 0x00040007,
430 0x916c, 0xffffffff, 0x00060005,
431 0x9170, 0xffffffff, 0x00090008,
432 0x9174, 0xffffffff, 0x00020001,
433 0x9178, 0xffffffff, 0x00040003,
434 0x917c, 0xffffffff, 0x00000007,
435 0x9180, 0xffffffff, 0x00060005,
436 0x9184, 0xffffffff, 0x00090008,
437 0x9188, 0xffffffff, 0x00030002,
438 0x918c, 0xffffffff, 0x00050004,
439 0x9190, 0xffffffff, 0x00000008,
440 0x9194, 0xffffffff, 0x00070006,
441 0x9198, 0xffffffff, 0x000a0009,
442 0x919c, 0xffffffff, 0x00040003,
443 0x91a0, 0xffffffff, 0x00060005,
444 0x91a4, 0xffffffff, 0x00000009,
445 0x91a8, 0xffffffff, 0x00080007,
446 0x91ac, 0xffffffff, 0x000b000a,
447 0x91b0, 0xffffffff, 0x00050004,
448 0x91b4, 0xffffffff, 0x00070006,
449 0x91b8, 0xffffffff, 0x0008000b,
450 0x91bc, 0xffffffff, 0x000a0009,
451 0x91c0, 0xffffffff, 0x000d000c,
452 0x9200, 0xffffffff, 0x00090008,
453 0x9204, 0xffffffff, 0x000b000a,
454 0x9208, 0xffffffff, 0x000c000f,
455 0x920c, 0xffffffff, 0x000e000d,
456 0x9210, 0xffffffff, 0x00110010,
457 0x9214, 0xffffffff, 0x000a0009,
458 0x9218, 0xffffffff, 0x000c000b,
459 0x921c, 0xffffffff, 0x0000000f,
460 0x9220, 0xffffffff, 0x000e000d,
461 0x9224, 0xffffffff, 0x00110010,
462 0x9228, 0xffffffff, 0x000b000a,
463 0x922c, 0xffffffff, 0x000d000c,
464 0x9230, 0xffffffff, 0x00000010,
465 0x9234, 0xffffffff, 0x000f000e,
466 0x9238, 0xffffffff, 0x00120011,
467 0x923c, 0xffffffff, 0x000c000b,
468 0x9240, 0xffffffff, 0x000e000d,
469 0x9244, 0xffffffff, 0x00000011,
470 0x9248, 0xffffffff, 0x0010000f,
471 0x924c, 0xffffffff, 0x00130012,
472 0x9250, 0xffffffff, 0x000d000c,
473 0x9254, 0xffffffff, 0x000f000e,
474 0x9258, 0xffffffff, 0x00100013,
475 0x925c, 0xffffffff, 0x00120011,
476 0x9260, 0xffffffff, 0x00150014,
477 0x9150, 0xffffffff, 0x96940200,
478 0x8708, 0xffffffff, 0x00900100,
479 0xc478, 0xffffffff, 0x00000080,
480 0xc404, 0xffffffff, 0x0020003f,
481 0x30, 0xffffffff, 0x0000001c,
482 0x34, 0x000f0000, 0x000f0000,
483 0x160c, 0xffffffff, 0x00000100,
484 0x1024, 0xffffffff, 0x00000100,
485 0x102c, 0x00000101, 0x00000000,
486 0x20a8, 0xffffffff, 0x00000104,
487 0x55e4, 0xff000fff, 0x00000100,
488 0x55e8, 0x00000001, 0x00000001,
489 0x2f50, 0x00000001, 0x00000001,
490 0x30cc, 0xc0000fff, 0x00000104,
491 0xc1e4, 0x00000001, 0x00000001,
492 0xd0c0, 0xfffffff0, 0x00000100,
493 0xd8c0, 0xfffffff0, 0x00000100
494};
495
496static const u32 verde_mgcg_cgcg_init[] =
497{
498 0xc400, 0xffffffff, 0xfffffffc,
499 0x802c, 0xffffffff, 0xe0000000,
500 0x9a60, 0xffffffff, 0x00000100,
501 0x92a4, 0xffffffff, 0x00000100,
502 0xc164, 0xffffffff, 0x00000100,
503 0x9774, 0xffffffff, 0x00000100,
504 0x8984, 0xffffffff, 0x06000100,
505 0x8a18, 0xffffffff, 0x00000100,
506 0x92a0, 0xffffffff, 0x00000100,
507 0xc380, 0xffffffff, 0x00000100,
508 0x8b28, 0xffffffff, 0x00000100,
509 0x9144, 0xffffffff, 0x00000100,
510 0x8d88, 0xffffffff, 0x00000100,
511 0x8d8c, 0xffffffff, 0x00000100,
512 0x9030, 0xffffffff, 0x00000100,
513 0x9034, 0xffffffff, 0x00000100,
514 0x9038, 0xffffffff, 0x00000100,
515 0x903c, 0xffffffff, 0x00000100,
516 0xad80, 0xffffffff, 0x00000100,
517 0xac54, 0xffffffff, 0x00000100,
518 0x897c, 0xffffffff, 0x06000100,
519 0x9868, 0xffffffff, 0x00000100,
520 0x9510, 0xffffffff, 0x00000100,
521 0xaf04, 0xffffffff, 0x00000100,
522 0xae04, 0xffffffff, 0x00000100,
523 0x949c, 0xffffffff, 0x00000100,
524 0x802c, 0xffffffff, 0xe0000000,
525 0x9160, 0xffffffff, 0x00010000,
526 0x9164, 0xffffffff, 0x00030002,
527 0x9168, 0xffffffff, 0x00040007,
528 0x916c, 0xffffffff, 0x00060005,
529 0x9170, 0xffffffff, 0x00090008,
530 0x9174, 0xffffffff, 0x00020001,
531 0x9178, 0xffffffff, 0x00040003,
532 0x917c, 0xffffffff, 0x00000007,
533 0x9180, 0xffffffff, 0x00060005,
534 0x9184, 0xffffffff, 0x00090008,
535 0x9188, 0xffffffff, 0x00030002,
536 0x918c, 0xffffffff, 0x00050004,
537 0x9190, 0xffffffff, 0x00000008,
538 0x9194, 0xffffffff, 0x00070006,
539 0x9198, 0xffffffff, 0x000a0009,
540 0x919c, 0xffffffff, 0x00040003,
541 0x91a0, 0xffffffff, 0x00060005,
542 0x91a4, 0xffffffff, 0x00000009,
543 0x91a8, 0xffffffff, 0x00080007,
544 0x91ac, 0xffffffff, 0x000b000a,
545 0x91b0, 0xffffffff, 0x00050004,
546 0x91b4, 0xffffffff, 0x00070006,
547 0x91b8, 0xffffffff, 0x0008000b,
548 0x91bc, 0xffffffff, 0x000a0009,
549 0x91c0, 0xffffffff, 0x000d000c,
550 0x9200, 0xffffffff, 0x00090008,
551 0x9204, 0xffffffff, 0x000b000a,
552 0x9208, 0xffffffff, 0x000c000f,
553 0x920c, 0xffffffff, 0x000e000d,
554 0x9210, 0xffffffff, 0x00110010,
555 0x9214, 0xffffffff, 0x000a0009,
556 0x9218, 0xffffffff, 0x000c000b,
557 0x921c, 0xffffffff, 0x0000000f,
558 0x9220, 0xffffffff, 0x000e000d,
559 0x9224, 0xffffffff, 0x00110010,
560 0x9228, 0xffffffff, 0x000b000a,
561 0x922c, 0xffffffff, 0x000d000c,
562 0x9230, 0xffffffff, 0x00000010,
563 0x9234, 0xffffffff, 0x000f000e,
564 0x9238, 0xffffffff, 0x00120011,
565 0x923c, 0xffffffff, 0x000c000b,
566 0x9240, 0xffffffff, 0x000e000d,
567 0x9244, 0xffffffff, 0x00000011,
568 0x9248, 0xffffffff, 0x0010000f,
569 0x924c, 0xffffffff, 0x00130012,
570 0x9250, 0xffffffff, 0x000d000c,
571 0x9254, 0xffffffff, 0x000f000e,
572 0x9258, 0xffffffff, 0x00100013,
573 0x925c, 0xffffffff, 0x00120011,
574 0x9260, 0xffffffff, 0x00150014,
575 0x9150, 0xffffffff, 0x96940200,
576 0x8708, 0xffffffff, 0x00900100,
577 0xc478, 0xffffffff, 0x00000080,
578 0xc404, 0xffffffff, 0x0020003f,
579 0x30, 0xffffffff, 0x0000001c,
580 0x34, 0x000f0000, 0x000f0000,
581 0x160c, 0xffffffff, 0x00000100,
582 0x1024, 0xffffffff, 0x00000100,
583 0x102c, 0x00000101, 0x00000000,
584 0x20a8, 0xffffffff, 0x00000104,
585 0x264c, 0x000c0000, 0x000c0000,
586 0x2648, 0x000c0000, 0x000c0000,
587 0x55e4, 0xff000fff, 0x00000100,
588 0x55e8, 0x00000001, 0x00000001,
589 0x2f50, 0x00000001, 0x00000001,
590 0x30cc, 0xc0000fff, 0x00000104,
591 0xc1e4, 0x00000001, 0x00000001,
592 0xd0c0, 0xfffffff0, 0x00000100,
593 0xd8c0, 0xfffffff0, 0x00000100
594};
595
596static const u32 oland_mgcg_cgcg_init[] =
597{
598 0xc400, 0xffffffff, 0xfffffffc,
599 0x802c, 0xffffffff, 0xe0000000,
600 0x9a60, 0xffffffff, 0x00000100,
601 0x92a4, 0xffffffff, 0x00000100,
602 0xc164, 0xffffffff, 0x00000100,
603 0x9774, 0xffffffff, 0x00000100,
604 0x8984, 0xffffffff, 0x06000100,
605 0x8a18, 0xffffffff, 0x00000100,
606 0x92a0, 0xffffffff, 0x00000100,
607 0xc380, 0xffffffff, 0x00000100,
608 0x8b28, 0xffffffff, 0x00000100,
609 0x9144, 0xffffffff, 0x00000100,
610 0x8d88, 0xffffffff, 0x00000100,
611 0x8d8c, 0xffffffff, 0x00000100,
612 0x9030, 0xffffffff, 0x00000100,
613 0x9034, 0xffffffff, 0x00000100,
614 0x9038, 0xffffffff, 0x00000100,
615 0x903c, 0xffffffff, 0x00000100,
616 0xad80, 0xffffffff, 0x00000100,
617 0xac54, 0xffffffff, 0x00000100,
618 0x897c, 0xffffffff, 0x06000100,
619 0x9868, 0xffffffff, 0x00000100,
620 0x9510, 0xffffffff, 0x00000100,
621 0xaf04, 0xffffffff, 0x00000100,
622 0xae04, 0xffffffff, 0x00000100,
623 0x949c, 0xffffffff, 0x00000100,
624 0x802c, 0xffffffff, 0xe0000000,
625 0x9160, 0xffffffff, 0x00010000,
626 0x9164, 0xffffffff, 0x00030002,
627 0x9168, 0xffffffff, 0x00040007,
628 0x916c, 0xffffffff, 0x00060005,
629 0x9170, 0xffffffff, 0x00090008,
630 0x9174, 0xffffffff, 0x00020001,
631 0x9178, 0xffffffff, 0x00040003,
632 0x917c, 0xffffffff, 0x00000007,
633 0x9180, 0xffffffff, 0x00060005,
634 0x9184, 0xffffffff, 0x00090008,
635 0x9188, 0xffffffff, 0x00030002,
636 0x918c, 0xffffffff, 0x00050004,
637 0x9190, 0xffffffff, 0x00000008,
638 0x9194, 0xffffffff, 0x00070006,
639 0x9198, 0xffffffff, 0x000a0009,
640 0x919c, 0xffffffff, 0x00040003,
641 0x91a0, 0xffffffff, 0x00060005,
642 0x91a4, 0xffffffff, 0x00000009,
643 0x91a8, 0xffffffff, 0x00080007,
644 0x91ac, 0xffffffff, 0x000b000a,
645 0x91b0, 0xffffffff, 0x00050004,
646 0x91b4, 0xffffffff, 0x00070006,
647 0x91b8, 0xffffffff, 0x0008000b,
648 0x91bc, 0xffffffff, 0x000a0009,
649 0x91c0, 0xffffffff, 0x000d000c,
650 0x91c4, 0xffffffff, 0x00060005,
651 0x91c8, 0xffffffff, 0x00080007,
652 0x91cc, 0xffffffff, 0x0000000b,
653 0x91d0, 0xffffffff, 0x000a0009,
654 0x91d4, 0xffffffff, 0x000d000c,
655 0x9150, 0xffffffff, 0x96940200,
656 0x8708, 0xffffffff, 0x00900100,
657 0xc478, 0xffffffff, 0x00000080,
658 0xc404, 0xffffffff, 0x0020003f,
659 0x30, 0xffffffff, 0x0000001c,
660 0x34, 0x000f0000, 0x000f0000,
661 0x160c, 0xffffffff, 0x00000100,
662 0x1024, 0xffffffff, 0x00000100,
663 0x102c, 0x00000101, 0x00000000,
664 0x20a8, 0xffffffff, 0x00000104,
665 0x264c, 0x000c0000, 0x000c0000,
666 0x2648, 0x000c0000, 0x000c0000,
667 0x55e4, 0xff000fff, 0x00000100,
668 0x55e8, 0x00000001, 0x00000001,
669 0x2f50, 0x00000001, 0x00000001,
670 0x30cc, 0xc0000fff, 0x00000104,
671 0xc1e4, 0x00000001, 0x00000001,
672 0xd0c0, 0xfffffff0, 0x00000100,
673 0xd8c0, 0xfffffff0, 0x00000100
674};
675
676static u32 verde_pg_init[] =
677{
678 0x353c, 0xffffffff, 0x40000,
679 0x3538, 0xffffffff, 0x200010ff,
680 0x353c, 0xffffffff, 0x0,
681 0x353c, 0xffffffff, 0x0,
682 0x353c, 0xffffffff, 0x0,
683 0x353c, 0xffffffff, 0x0,
684 0x353c, 0xffffffff, 0x0,
685 0x353c, 0xffffffff, 0x7007,
686 0x3538, 0xffffffff, 0x300010ff,
687 0x353c, 0xffffffff, 0x0,
688 0x353c, 0xffffffff, 0x0,
689 0x353c, 0xffffffff, 0x0,
690 0x353c, 0xffffffff, 0x0,
691 0x353c, 0xffffffff, 0x0,
692 0x353c, 0xffffffff, 0x400000,
693 0x3538, 0xffffffff, 0x100010ff,
694 0x353c, 0xffffffff, 0x0,
695 0x353c, 0xffffffff, 0x0,
696 0x353c, 0xffffffff, 0x0,
697 0x353c, 0xffffffff, 0x0,
698 0x353c, 0xffffffff, 0x0,
699 0x353c, 0xffffffff, 0x120200,
700 0x3538, 0xffffffff, 0x500010ff,
701 0x353c, 0xffffffff, 0x0,
702 0x353c, 0xffffffff, 0x0,
703 0x353c, 0xffffffff, 0x0,
704 0x353c, 0xffffffff, 0x0,
705 0x353c, 0xffffffff, 0x0,
706 0x353c, 0xffffffff, 0x1e1e16,
707 0x3538, 0xffffffff, 0x600010ff,
708 0x353c, 0xffffffff, 0x0,
709 0x353c, 0xffffffff, 0x0,
710 0x353c, 0xffffffff, 0x0,
711 0x353c, 0xffffffff, 0x0,
712 0x353c, 0xffffffff, 0x0,
713 0x353c, 0xffffffff, 0x171f1e,
714 0x3538, 0xffffffff, 0x700010ff,
715 0x353c, 0xffffffff, 0x0,
716 0x353c, 0xffffffff, 0x0,
717 0x353c, 0xffffffff, 0x0,
718 0x353c, 0xffffffff, 0x0,
719 0x353c, 0xffffffff, 0x0,
720 0x353c, 0xffffffff, 0x0,
721 0x3538, 0xffffffff, 0x9ff,
722 0x3500, 0xffffffff, 0x0,
723 0x3504, 0xffffffff, 0x10000800,
724 0x3504, 0xffffffff, 0xf,
725 0x3504, 0xffffffff, 0xf,
726 0x3500, 0xffffffff, 0x4,
727 0x3504, 0xffffffff, 0x1000051e,
728 0x3504, 0xffffffff, 0xffff,
729 0x3504, 0xffffffff, 0xffff,
730 0x3500, 0xffffffff, 0x8,
731 0x3504, 0xffffffff, 0x80500,
732 0x3500, 0xffffffff, 0x12,
733 0x3504, 0xffffffff, 0x9050c,
734 0x3500, 0xffffffff, 0x1d,
735 0x3504, 0xffffffff, 0xb052c,
736 0x3500, 0xffffffff, 0x2a,
737 0x3504, 0xffffffff, 0x1053e,
738 0x3500, 0xffffffff, 0x2d,
739 0x3504, 0xffffffff, 0x10546,
740 0x3500, 0xffffffff, 0x30,
741 0x3504, 0xffffffff, 0xa054e,
742 0x3500, 0xffffffff, 0x3c,
743 0x3504, 0xffffffff, 0x1055f,
744 0x3500, 0xffffffff, 0x3f,
745 0x3504, 0xffffffff, 0x10567,
746 0x3500, 0xffffffff, 0x42,
747 0x3504, 0xffffffff, 0x1056f,
748 0x3500, 0xffffffff, 0x45,
749 0x3504, 0xffffffff, 0x10572,
750 0x3500, 0xffffffff, 0x48,
751 0x3504, 0xffffffff, 0x20575,
752 0x3500, 0xffffffff, 0x4c,
753 0x3504, 0xffffffff, 0x190801,
754 0x3500, 0xffffffff, 0x67,
755 0x3504, 0xffffffff, 0x1082a,
756 0x3500, 0xffffffff, 0x6a,
757 0x3504, 0xffffffff, 0x1b082d,
758 0x3500, 0xffffffff, 0x87,
759 0x3504, 0xffffffff, 0x310851,
760 0x3500, 0xffffffff, 0xba,
761 0x3504, 0xffffffff, 0x891,
762 0x3500, 0xffffffff, 0xbc,
763 0x3504, 0xffffffff, 0x893,
764 0x3500, 0xffffffff, 0xbe,
765 0x3504, 0xffffffff, 0x20895,
766 0x3500, 0xffffffff, 0xc2,
767 0x3504, 0xffffffff, 0x20899,
768 0x3500, 0xffffffff, 0xc6,
769 0x3504, 0xffffffff, 0x2089d,
770 0x3500, 0xffffffff, 0xca,
771 0x3504, 0xffffffff, 0x8a1,
772 0x3500, 0xffffffff, 0xcc,
773 0x3504, 0xffffffff, 0x8a3,
774 0x3500, 0xffffffff, 0xce,
775 0x3504, 0xffffffff, 0x308a5,
776 0x3500, 0xffffffff, 0xd3,
777 0x3504, 0xffffffff, 0x6d08cd,
778 0x3500, 0xffffffff, 0x142,
779 0x3504, 0xffffffff, 0x2000095a,
780 0x3504, 0xffffffff, 0x1,
781 0x3500, 0xffffffff, 0x144,
782 0x3504, 0xffffffff, 0x301f095b,
783 0x3500, 0xffffffff, 0x165,
784 0x3504, 0xffffffff, 0xc094d,
785 0x3500, 0xffffffff, 0x173,
786 0x3504, 0xffffffff, 0xf096d,
787 0x3500, 0xffffffff, 0x184,
788 0x3504, 0xffffffff, 0x15097f,
789 0x3500, 0xffffffff, 0x19b,
790 0x3504, 0xffffffff, 0xc0998,
791 0x3500, 0xffffffff, 0x1a9,
792 0x3504, 0xffffffff, 0x409a7,
793 0x3500, 0xffffffff, 0x1af,
794 0x3504, 0xffffffff, 0xcdc,
795 0x3500, 0xffffffff, 0x1b1,
796 0x3504, 0xffffffff, 0x800,
797 0x3508, 0xffffffff, 0x6c9b2000,
798 0x3510, 0xfc00, 0x2000,
799 0x3544, 0xffffffff, 0xfc0,
800 0x28d4, 0x00000100, 0x100
801};
802
803static void si_init_golden_registers(struct radeon_device *rdev)
804{
805 switch (rdev->family) {
806 case CHIP_TAHITI:
807 radeon_program_register_sequence(rdev,
808 tahiti_golden_registers,
809 (const u32)ARRAY_SIZE(tahiti_golden_registers));
810 radeon_program_register_sequence(rdev,
811 tahiti_golden_rlc_registers,
812 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
813 radeon_program_register_sequence(rdev,
814 tahiti_mgcg_cgcg_init,
815 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
816 radeon_program_register_sequence(rdev,
817 tahiti_golden_registers2,
818 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
819 break;
820 case CHIP_PITCAIRN:
821 radeon_program_register_sequence(rdev,
822 pitcairn_golden_registers,
823 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
824 radeon_program_register_sequence(rdev,
825 pitcairn_golden_rlc_registers,
826 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
827 radeon_program_register_sequence(rdev,
828 pitcairn_mgcg_cgcg_init,
829 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
830 break;
831 case CHIP_VERDE:
832 radeon_program_register_sequence(rdev,
833 verde_golden_registers,
834 (const u32)ARRAY_SIZE(verde_golden_registers));
835 radeon_program_register_sequence(rdev,
836 verde_golden_rlc_registers,
837 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
838 radeon_program_register_sequence(rdev,
839 verde_mgcg_cgcg_init,
840 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
841 radeon_program_register_sequence(rdev,
842 verde_pg_init,
843 (const u32)ARRAY_SIZE(verde_pg_init));
844 break;
845 case CHIP_OLAND:
846 radeon_program_register_sequence(rdev,
847 oland_golden_registers,
848 (const u32)ARRAY_SIZE(oland_golden_registers));
849 radeon_program_register_sequence(rdev,
850 oland_golden_rlc_registers,
851 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
852 radeon_program_register_sequence(rdev,
853 oland_mgcg_cgcg_init,
854 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
855 break;
856 default:
857 break;
858 }
859}
860
73#define PCIE_BUS_CLK 10000 861#define PCIE_BUS_CLK 10000
74#define TCLK (PCIE_BUS_CLK / 10) 862#define TCLK (PCIE_BUS_CLK / 10)
75 863
@@ -1211,6 +1999,7 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
1211 gb_tile_moden = 0; 1999 gb_tile_moden = 0;
1212 break; 2000 break;
1213 } 2001 }
2002 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
1214 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 2003 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1215 } 2004 }
1216 } else if ((rdev->family == CHIP_VERDE) || 2005 } else if ((rdev->family == CHIP_VERDE) ||
@@ -1451,6 +2240,7 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
1451 gb_tile_moden = 0; 2240 gb_tile_moden = 0;
1452 break; 2241 break;
1453 } 2242 }
2243 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
1454 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 2244 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1455 } 2245 }
1456 } else 2246 } else
@@ -1463,7 +2253,7 @@ static void si_select_se_sh(struct radeon_device *rdev,
1463 u32 data = INSTANCE_BROADCAST_WRITES; 2253 u32 data = INSTANCE_BROADCAST_WRITES;
1464 2254
1465 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 2255 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1466 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; 2256 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1467 else if (se_num == 0xffffffff) 2257 else if (se_num == 0xffffffff)
1468 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); 2258 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1469 else if (sh_num == 0xffffffff) 2259 else if (sh_num == 0xffffffff)
@@ -1765,9 +2555,13 @@ static void si_gpu_init(struct radeon_device *rdev)
1765 2555
1766 WREG32(GB_ADDR_CONFIG, gb_addr_config); 2556 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1767 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 2557 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2558 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1768 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 2559 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1769 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 2560 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1770 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 2561 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
2562 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
2563 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2564 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1771 2565
1772 si_tiling_mode_table_init(rdev); 2566 si_tiling_mode_table_init(rdev);
1773 2567
@@ -2538,46 +3332,6 @@ static void si_mc_program(struct radeon_device *rdev)
2538 rv515_vga_render_disable(rdev); 3332 rv515_vga_render_disable(rdev);
2539} 3333}
2540 3334
2541/* SI MC address space is 40 bits */
2542static void si_vram_location(struct radeon_device *rdev,
2543 struct radeon_mc *mc, u64 base)
2544{
2545 mc->vram_start = base;
2546 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2547 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2548 mc->real_vram_size = mc->aper_size;
2549 mc->mc_vram_size = mc->aper_size;
2550 }
2551 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2552 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2553 mc->mc_vram_size >> 20, mc->vram_start,
2554 mc->vram_end, mc->real_vram_size >> 20);
2555}
2556
2557static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2558{
2559 u64 size_af, size_bf;
2560
2561 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2562 size_bf = mc->vram_start & ~mc->gtt_base_align;
2563 if (size_bf > size_af) {
2564 if (mc->gtt_size > size_bf) {
2565 dev_warn(rdev->dev, "limiting GTT\n");
2566 mc->gtt_size = size_bf;
2567 }
2568 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2569 } else {
2570 if (mc->gtt_size > size_af) {
2571 dev_warn(rdev->dev, "limiting GTT\n");
2572 mc->gtt_size = size_af;
2573 }
2574 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2575 }
2576 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2577 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2578 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2579}
2580
2581static void si_vram_gtt_location(struct radeon_device *rdev, 3335static void si_vram_gtt_location(struct radeon_device *rdev,
2582 struct radeon_mc *mc) 3336 struct radeon_mc *mc)
2583{ 3337{
@@ -2587,9 +3341,9 @@ static void si_vram_gtt_location(struct radeon_device *rdev,
2587 mc->real_vram_size = 0xFFC0000000ULL; 3341 mc->real_vram_size = 0xFFC0000000ULL;
2588 mc->mc_vram_size = 0xFFC0000000ULL; 3342 mc->mc_vram_size = 0xFFC0000000ULL;
2589 } 3343 }
2590 si_vram_location(rdev, &rdev->mc, 0); 3344 radeon_vram_location(rdev, &rdev->mc, 0);
2591 rdev->mc.gtt_base_align = 0; 3345 rdev->mc.gtt_base_align = 0;
2592 si_gtt_location(rdev, mc); 3346 radeon_gtt_location(rdev, mc);
2593} 3347}
2594 3348
2595static int si_mc_init(struct radeon_device *rdev) 3349static int si_mc_init(struct radeon_device *rdev)
@@ -4322,14 +5076,6 @@ static int si_startup(struct radeon_device *rdev)
4322 return r; 5076 return r;
4323 si_gpu_init(rdev); 5077 si_gpu_init(rdev);
4324 5078
4325#if 0
4326 r = evergreen_blit_init(rdev);
4327 if (r) {
4328 r600_blit_fini(rdev);
4329 rdev->asic->copy = NULL;
4330 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
4331 }
4332#endif
4333 /* allocate rlc buffers */ 5079 /* allocate rlc buffers */
4334 r = si_rlc_init(rdev); 5080 r = si_rlc_init(rdev);
4335 if (r) { 5081 if (r) {
@@ -4372,6 +5118,16 @@ static int si_startup(struct radeon_device *rdev)
4372 return r; 5118 return r;
4373 } 5119 }
4374 5120
5121 r = rv770_uvd_resume(rdev);
5122 if (!r) {
5123 r = radeon_fence_driver_start_ring(rdev,
5124 R600_RING_TYPE_UVD_INDEX);
5125 if (r)
5126 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
5127 }
5128 if (r)
5129 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
5130
4375 /* Enable IRQ */ 5131 /* Enable IRQ */
4376 r = si_irq_init(rdev); 5132 r = si_irq_init(rdev);
4377 if (r) { 5133 if (r) {
@@ -4429,6 +5185,18 @@ static int si_startup(struct radeon_device *rdev)
4429 if (r) 5185 if (r)
4430 return r; 5186 return r;
4431 5187
5188 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
5189 if (ring->ring_size) {
5190 r = radeon_ring_init(rdev, ring, ring->ring_size,
5191 R600_WB_UVD_RPTR_OFFSET,
5192 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
5193 0, 0xfffff, RADEON_CP_PACKET2);
5194 if (!r)
5195 r = r600_uvd_init(rdev);
5196 if (r)
5197 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
5198 }
5199
4432 r = radeon_ib_pool_init(rdev); 5200 r = radeon_ib_pool_init(rdev);
4433 if (r) { 5201 if (r) {
4434 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 5202 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -4455,6 +5223,9 @@ int si_resume(struct radeon_device *rdev)
4455 /* post card */ 5223 /* post card */
4456 atom_asic_init(rdev->mode_info.atom_context); 5224 atom_asic_init(rdev->mode_info.atom_context);
4457 5225
5226 /* init golden registers */
5227 si_init_golden_registers(rdev);
5228
4458 rdev->accel_working = true; 5229 rdev->accel_working = true;
4459 r = si_startup(rdev); 5230 r = si_startup(rdev);
4460 if (r) { 5231 if (r) {
@@ -4472,6 +5243,8 @@ int si_suspend(struct radeon_device *rdev)
4472 radeon_vm_manager_fini(rdev); 5243 radeon_vm_manager_fini(rdev);
4473 si_cp_enable(rdev, false); 5244 si_cp_enable(rdev, false);
4474 cayman_dma_stop(rdev); 5245 cayman_dma_stop(rdev);
5246 r600_uvd_rbc_stop(rdev);
5247 radeon_uvd_suspend(rdev);
4475 si_irq_suspend(rdev); 5248 si_irq_suspend(rdev);
4476 radeon_wb_disable(rdev); 5249 radeon_wb_disable(rdev);
4477 si_pcie_gart_disable(rdev); 5250 si_pcie_gart_disable(rdev);
@@ -4512,6 +5285,8 @@ int si_init(struct radeon_device *rdev)
4512 DRM_INFO("GPU not posted. posting now...\n"); 5285 DRM_INFO("GPU not posted. posting now...\n");
4513 atom_asic_init(rdev->mode_info.atom_context); 5286 atom_asic_init(rdev->mode_info.atom_context);
4514 } 5287 }
5288 /* init golden registers */
5289 si_init_golden_registers(rdev);
4515 /* Initialize scratch registers */ 5290 /* Initialize scratch registers */
4516 si_scratch_init(rdev); 5291 si_scratch_init(rdev);
4517 /* Initialize surface registers */ 5292 /* Initialize surface registers */
@@ -4557,6 +5332,13 @@ int si_init(struct radeon_device *rdev)
4557 ring->ring_obj = NULL; 5332 ring->ring_obj = NULL;
4558 r600_ring_init(rdev, ring, 64 * 1024); 5333 r600_ring_init(rdev, ring, 64 * 1024);
4559 5334
5335 r = radeon_uvd_init(rdev);
5336 if (!r) {
5337 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
5338 ring->ring_obj = NULL;
5339 r600_ring_init(rdev, ring, 4096);
5340 }
5341
4560 rdev->ih.ring_obj = NULL; 5342 rdev->ih.ring_obj = NULL;
4561 r600_ih_ring_init(rdev, 64 * 1024); 5343 r600_ih_ring_init(rdev, 64 * 1024);
4562 5344
@@ -4594,9 +5376,6 @@ int si_init(struct radeon_device *rdev)
4594 5376
4595void si_fini(struct radeon_device *rdev) 5377void si_fini(struct radeon_device *rdev)
4596{ 5378{
4597#if 0
4598 r600_blit_fini(rdev);
4599#endif
4600 si_cp_fini(rdev); 5379 si_cp_fini(rdev);
4601 cayman_dma_fini(rdev); 5380 cayman_dma_fini(rdev);
4602 si_irq_fini(rdev); 5381 si_irq_fini(rdev);
@@ -4605,6 +5384,7 @@ void si_fini(struct radeon_device *rdev)
4605 radeon_vm_manager_fini(rdev); 5384 radeon_vm_manager_fini(rdev);
4606 radeon_ib_pool_fini(rdev); 5385 radeon_ib_pool_fini(rdev);
4607 radeon_irq_kms_fini(rdev); 5386 radeon_irq_kms_fini(rdev);
5387 radeon_uvd_fini(rdev);
4608 si_pcie_gart_fini(rdev); 5388 si_pcie_gart_fini(rdev);
4609 r600_vram_scratch_fini(rdev); 5389 r600_vram_scratch_fini(rdev);
4610 radeon_gem_fini(rdev); 5390 radeon_gem_fini(rdev);
@@ -4634,3 +5414,94 @@ uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
4634 mutex_unlock(&rdev->gpu_clock_mutex); 5414 mutex_unlock(&rdev->gpu_clock_mutex);
4635 return clock; 5415 return clock;
4636} 5416}
5417
5418int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
5419{
5420 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
5421 int r;
5422
5423 /* bypass vclk and dclk with bclk */
5424 WREG32_P(CG_UPLL_FUNC_CNTL_2,
5425 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
5426 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
5427
5428 /* put PLL in bypass mode */
5429 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
5430
5431 if (!vclk || !dclk) {
5432 /* keep the Bypass mode, put PLL to sleep */
5433 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
5434 return 0;
5435 }
5436
5437 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
5438 16384, 0x03FFFFFF, 0, 128, 5,
5439 &fb_div, &vclk_div, &dclk_div);
5440 if (r)
5441 return r;
5442
5443 /* set RESET_ANTI_MUX to 0 */
5444 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
5445
5446 /* set VCO_MODE to 1 */
5447 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
5448
5449 /* toggle UPLL_SLEEP to 1 then back to 0 */
5450 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
5451 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
5452
5453 /* deassert UPLL_RESET */
5454 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
5455
5456 mdelay(1);
5457
5458 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
5459 if (r)
5460 return r;
5461
5462 /* assert UPLL_RESET again */
5463 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
5464
5465 /* disable spread spectrum. */
5466 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
5467
5468 /* set feedback divider */
5469 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
5470
5471 /* set ref divider to 0 */
5472 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
5473
5474 if (fb_div < 307200)
5475 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
5476 else
5477 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
5478
5479 /* set PDIV_A and PDIV_B */
5480 WREG32_P(CG_UPLL_FUNC_CNTL_2,
5481 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
5482 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
5483
5484 /* give the PLL some time to settle */
5485 mdelay(15);
5486
5487 /* deassert PLL_RESET */
5488 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
5489
5490 mdelay(15);
5491
5492 /* switch from bypass mode to normal mode */
5493 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
5494
5495 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
5496 if (r)
5497 return r;
5498
5499 /* switch VCLK and DCLK selection */
5500 WREG32_P(CG_UPLL_FUNC_CNTL_2,
5501 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
5502 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
5503
5504 mdelay(100);
5505
5506 return 0;
5507}
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 23fc08fc8e7f..222877ba6cf5 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -29,6 +29,35 @@
29#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 29#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 30#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31 31
32/* discrete uvd clocks */
33#define CG_UPLL_FUNC_CNTL 0x634
34# define UPLL_RESET_MASK 0x00000001
35# define UPLL_SLEEP_MASK 0x00000002
36# define UPLL_BYPASS_EN_MASK 0x00000004
37# define UPLL_CTLREQ_MASK 0x00000008
38# define UPLL_VCO_MODE_MASK 0x00000600
39# define UPLL_REF_DIV_MASK 0x003F0000
40# define UPLL_CTLACK_MASK 0x40000000
41# define UPLL_CTLACK2_MASK 0x80000000
42#define CG_UPLL_FUNC_CNTL_2 0x638
43# define UPLL_PDIV_A(x) ((x) << 0)
44# define UPLL_PDIV_A_MASK 0x0000007F
45# define UPLL_PDIV_B(x) ((x) << 8)
46# define UPLL_PDIV_B_MASK 0x00007F00
47# define VCLK_SRC_SEL(x) ((x) << 20)
48# define VCLK_SRC_SEL_MASK 0x01F00000
49# define DCLK_SRC_SEL(x) ((x) << 25)
50# define DCLK_SRC_SEL_MASK 0x3E000000
51#define CG_UPLL_FUNC_CNTL_3 0x63C
52# define UPLL_FB_DIV(x) ((x) << 0)
53# define UPLL_FB_DIV_MASK 0x01FFFFFF
54#define CG_UPLL_FUNC_CNTL_4 0x644
55# define UPLL_SPARE_ISPARE9 0x00020000
56#define CG_UPLL_FUNC_CNTL_5 0x648
57# define RESET_ANTI_MUX_MASK 0x00000200
58#define CG_UPLL_SPREAD_SPECTRUM 0x650
59# define SSEN_MASK 0x00000001
60
32#define CG_MULT_THERMAL_STATUS 0x714 61#define CG_MULT_THERMAL_STATUS 0x714
33#define ASIC_MAX_TEMP(x) ((x) << 0) 62#define ASIC_MAX_TEMP(x) ((x) << 0)
34#define ASIC_MAX_TEMP_MASK 0x000001ff 63#define ASIC_MAX_TEMP_MASK 0x000001ff
@@ -65,6 +94,8 @@
65 94
66#define DMIF_ADDR_CONFIG 0xBD4 95#define DMIF_ADDR_CONFIG 0xBD4
67 96
97#define DMIF_ADDR_CALC 0xC00
98
68#define SRBM_STATUS 0xE50 99#define SRBM_STATUS 0xE50
69#define GRBM_RQ_PENDING (1 << 5) 100#define GRBM_RQ_PENDING (1 << 5)
70#define VMC_BUSY (1 << 8) 101#define VMC_BUSY (1 << 8)
@@ -798,6 +829,15 @@
798# define THREAD_TRACE_FINISH (55 << 0) 829# define THREAD_TRACE_FINISH (55 << 0)
799 830
800/* 831/*
832 * UVD
833 */
834#define UVD_UDEC_ADDR_CONFIG 0xEF4C
835#define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
836#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
837#define UVD_RBC_RB_RPTR 0xF690
838#define UVD_RBC_RB_WPTR 0xF694
839
840/*
801 * PM4 841 * PM4
802 */ 842 */
803#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 843#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 18:08:30 -0400