diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-12-03 18:07:25 -0500 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2012-12-12 17:16:48 -0500 |
commit | b997a8ba26377895506a26a3f2b8f1e7abc4ed22 (patch) | |
tree | 37f88ab4d3cc4e25806f15df9da74aba13ee771a /drivers/gpu/drm/radeon/sid.h | |
parent | 6253e4c75d96006c06b9ac8f417eba873de2497b (diff) |
drm/radeon: add register headers for CP DMA on r6xx-SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/sid.h')
-rw-r--r-- | drivers/gpu/drm/radeon/sid.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index e153c254fbfb..62b46215d423 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h | |||
@@ -849,6 +849,54 @@ | |||
849 | #define PACKET3_WAIT_REG_MEM 0x3C | 849 | #define PACKET3_WAIT_REG_MEM 0x3C |
850 | #define PACKET3_MEM_WRITE 0x3D | 850 | #define PACKET3_MEM_WRITE 0x3D |
851 | #define PACKET3_COPY_DATA 0x40 | 851 | #define PACKET3_COPY_DATA 0x40 |
852 | #define PACKET3_CP_DMA 0x41 | ||
853 | /* 1. header | ||
854 | * 2. SRC_ADDR_LO or DATA [31:0] | ||
855 | * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | | ||
856 | * SRC_ADDR_HI [7:0] | ||
857 | * 4. DST_ADDR_LO [31:0] | ||
858 | * 5. DST_ADDR_HI [7:0] | ||
859 | * 6. COMMAND [30:21] | BYTE_COUNT [20:0] | ||
860 | */ | ||
861 | # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) | ||
862 | /* 0 - SRC_ADDR | ||
863 | * 1 - GDS | ||
864 | */ | ||
865 | # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) | ||
866 | /* 0 - ME | ||
867 | * 1 - PFP | ||
868 | */ | ||
869 | # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) | ||
870 | /* 0 - SRC_ADDR | ||
871 | * 1 - GDS | ||
872 | * 2 - DATA | ||
873 | */ | ||
874 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) | ||
875 | /* COMMAND */ | ||
876 | # define PACKET3_CP_DMA_DIS_WC (1 << 21) | ||
877 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) | ||
878 | /* 0 - none | ||
879 | * 1 - 8 in 16 | ||
880 | * 2 - 8 in 32 | ||
881 | * 3 - 8 in 64 | ||
882 | */ | ||
883 | # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) | ||
884 | /* 0 - none | ||
885 | * 1 - 8 in 16 | ||
886 | * 2 - 8 in 32 | ||
887 | * 3 - 8 in 64 | ||
888 | */ | ||
889 | # define PACKET3_CP_DMA_CMD_SAS (1 << 26) | ||
890 | /* 0 - memory | ||
891 | * 1 - register | ||
892 | */ | ||
893 | # define PACKET3_CP_DMA_CMD_DAS (1 << 27) | ||
894 | /* 0 - memory | ||
895 | * 1 - register | ||
896 | */ | ||
897 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) | ||
898 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) | ||
899 | # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) | ||
852 | #define PACKET3_PFP_SYNC_ME 0x42 | 900 | #define PACKET3_PFP_SYNC_ME 0x42 |
853 | #define PACKET3_SURFACE_SYNC 0x43 | 901 | #define PACKET3_SURFACE_SYNC 0x43 |
854 | # define PACKET3_DEST_BASE_0_ENA (1 << 0) | 902 | # define PACKET3_DEST_BASE_0_ENA (1 << 0) |