drm/radeon/kms: add dpm support for SI (v7)

This adds dpm support for SI asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2/gen3 switching - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: enable hainan support, rebase v3: guard acpi stuff v4: fix 64 bit math v5: fix 64 bit div harder v6: fix thermal interrupt check noticed by Jerome v7: attempt fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
author: Alex Deucher <alexander.deucher@amd.com> 2013-06-25 17:56:16 -0400
committer: Alex Deucher <alexander.deucher@amd.com> 2013-06-27 19:40:05 -0400
commit: a9e61410921bcc1aa8f594ffa6301d5baba90f3b (patch)
tree: 82c267bd9854a8d0cb7b3a8ccc8693194ecfd236 /drivers/gpu/drm/radeon/si_dpm.h
parent: a0ceada6b4da18e8539bc3229adae3dc9b05d9a2 (diff)
1 files changed, 227 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si_dpm.h b/drivers/gpu/drm/radeon/si_dpm.h
new file mode 100644
index 000000000000..4ce5032cdf49
--- /dev/null
+++ b/drivers/gpu/drm/radeon/si_dpm.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SI_DPM_H__
+#define __SI_DPM_H__
+#include "ni_dpm.h"
+#include "sislands_smc.h"
+enum si_cac_config_reg_type
+{
+        SISLANDS_CACCONFIG_MMR = 0,
+        SISLANDS_CACCONFIG_CGIND,
+        SISLANDS_CACCONFIG_MAX
+};
+struct si_cac_config_reg
+{
+        u32 offset;
+        u32 mask;
+        u32 shift;
+        u32 value;
+        enum si_cac_config_reg_type type;
+};
+struct si_powertune_data
+{
+        u32 cac_window;
+        u32 l2_lta_window_size_default;
+        u8 lts_truncate_default;
+        u8 shift_n_default;
+        u8 operating_temp;
+        struct ni_leakage_coeffients leakage_coefficients;
+        u32 fixed_kt;
+        u32 lkge_lut_v0_percent;
+        u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
+        bool enable_powertune_by_default;
+};
+struct si_dyn_powertune_data
+{
+        u32 cac_leakage;
+        s32 leakage_minimum_temperature;
+        u32 wintime;
+        u32 l2_lta_window_size;
+        u8 lts_truncate;
+        u8 shift_n;
+        u8 dc_pwr_value;
+        bool disable_uvd_powertune;
+};
+struct si_dte_data
+{
+        u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
+        u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
+        u32 k;
+        u32 t0;
+        u32 max_t;
+        u8 window_size;
+        u8 temp_select;
+        u8 dte_mode;
+        u8 tdep_count;
+        u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
+        u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
+        u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
+        u32 t_threshold;
+        bool enable_dte_by_default;
+};
+struct si_clock_registers {
+        u32 cg_spll_func_cntl;
+        u32 cg_spll_func_cntl_2;
+        u32 cg_spll_func_cntl_3;
+        u32 cg_spll_func_cntl_4;
+        u32 cg_spll_spread_spectrum;
+        u32 cg_spll_spread_spectrum_2;
+        u32 dll_cntl;
+        u32 mclk_pwrmgt_cntl;
+        u32 mpll_ad_func_cntl;
+        u32 mpll_dq_func_cntl;
+        u32 mpll_func_cntl;
+        u32 mpll_func_cntl_1;
+        u32 mpll_func_cntl_2;
+        u32 mpll_ss1;
+        u32 mpll_ss2;
+};
+struct si_mc_reg_entry {
+        u32 mclk_max;
+        u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
+};
+struct si_mc_reg_table {
+        u8 last;
+        u8 num_entries;
+        u16 valid_flag;
+        struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
+        SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
+};
+#define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT               0
+#define SISLANDS_MCREGISTERTABLE_ACPI_SLOT                  1
+#define SISLANDS_MCREGISTERTABLE_ULV_SLOT                   2
+#define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT     3
+struct si_leakage_voltage_entry
+{
+        u16 voltage;
+        u16 leakage_index;
+};
+#define SISLANDS_LEAKAGE_INDEX0     0xff01
+#define SISLANDS_MAX_LEAKAGE_COUNT  4
+struct si_leakage_voltage
+{
+        u16 count;
+        struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];
+};
+#define SISLANDS_MAX_HARDWARE_POWERLEVELS 5
+struct si_ulv_param {
+        bool supported;
+        u32 cg_ulv_control;
+        u32 cg_ulv_parameter;
+        u32 volt_change_delay;
+        struct rv7xx_pl pl;
+        bool one_pcie_lane_in_ulv;
+};
+struct si_power_info {
+        /* must be first! */
+        struct ni_power_info ni;
+        struct si_clock_registers clock_registers;
+        struct si_mc_reg_table mc_reg_table;
+        struct atom_voltage_table mvdd_voltage_table;
+        struct atom_voltage_table vddc_phase_shed_table;
+        struct si_leakage_voltage leakage_voltage;
+        u16 mvdd_bootup_value;
+        struct si_ulv_param ulv;
+        u32 max_cu;
+        /* pcie gen */
+        enum radeon_pcie_gen force_pcie_gen;
+        enum radeon_pcie_gen boot_pcie_gen;
+        enum radeon_pcie_gen acpi_pcie_gen;
+        u32 sys_pcie_mask;
+        /* flags */
+        bool enable_dte;
+        bool enable_ppm;
+        bool vddc_phase_shed_control;
+        bool pspp_notify_required;
+        bool sclk_deep_sleep_above_low;
+        /* smc offsets */
+        u32 sram_end;
+        u32 state_table_start;
+        u32 soft_regs_start;
+        u32 mc_reg_table_start;
+        u32 arb_table_start;
+        u32 cac_table_start;
+        u32 dte_table_start;
+        u32 spll_table_start;
+        u32 papm_cfg_table_start;
+        /* CAC stuff */
+        const struct si_cac_config_reg *cac_weights;
+        const struct si_cac_config_reg *lcac_config;
+        const struct si_cac_config_reg *cac_override;
+        const struct si_powertune_data *powertune_data;
+        struct si_dyn_powertune_data dyn_powertune_data;
+        /* DTE stuff */
+        struct si_dte_data dte_data;
+        /* scratch structs */
+        SMC_SIslands_MCRegisters smc_mc_reg_table;
+        SISLANDS_SMC_STATETABLE smc_statetable;
+        PP_SIslands_PAPMParameters papm_parm;
+};
+#define SISLANDS_INITIAL_STATE_ARB_INDEX    0
+#define SISLANDS_ACPI_STATE_ARB_INDEX       1
+#define SISLANDS_ULV_STATE_ARB_INDEX        2
+#define SISLANDS_DRIVER_STATE_ARB_INDEX     3
+#define SISLANDS_DPM2_MAX_PULSE_SKIP        256
+#define SISLANDS_DPM2_NEAR_TDP_DEC          10
+#define SISLANDS_DPM2_ABOVE_SAFE_INC        5
+#define SISLANDS_DPM2_BELOW_SAFE_INC        20
+#define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT            80
+#define SISLANDS_DPM2_MAXPS_PERCENT_H                   99
+#define SISLANDS_DPM2_MAXPS_PERCENT_M                   99
+#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
+#define SISLANDS_DPM2_SQ_RAMP_MIN_POWER                 0x12
+#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
+#define SISLANDS_DPM2_SQ_RAMP_STI_SIZE                  0x1E
+#define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO                 0xF
+#define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN         10
+#define SISLANDS_VRC_DFLT                               0xC000B3
+#define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT             1687
+#define SISLANDS_CGULVPARAMETER_DFLT                    0x00040035
+#define SISLANDS_CGULVCONTROL_DFLT                      0x1f007550
+#endif
author	Alex Deucher <alexander.deucher@amd.com>	2013-06-25 17:56:16 -0400
committer	Alex Deucher <alexander.deucher@amd.com>	2013-06-27 19:40:05 -0400
commit	a9e61410921bcc1aa8f594ffa6301d5baba90f3b (patch)
tree	82c267bd9854a8d0cb7b3a8ccc8693194ecfd236 /drivers/gpu/drm/radeon/si_dpm.h
parent	a0ceada6b4da18e8539bc3229adae3dc9b05d9a2 (diff)

diff --git a/drivers/gpu/drm/radeon/si_dpm.h b/drivers/gpu/drm/radeon/si_dpm.h new file mode 100644 index 000000000000..4ce5032cdf49 --- /dev/null +++ b/drivers/gpu/drm/radeon/si_dpm.h
@@ -0,0 +1,227 @@
	1	/*
	2	* Copyright 2012 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef __SI_DPM_H__
	24	#define __SI_DPM_H__
	25
	26	#include "ni_dpm.h"
	27	#include "sislands_smc.h"
	28
	29	enum si_cac_config_reg_type
	30	{
	31	SISLANDS_CACCONFIG_MMR = 0,
	32	SISLANDS_CACCONFIG_CGIND,
	33	SISLANDS_CACCONFIG_MAX
	34	};
	35
	36	struct si_cac_config_reg
	37	{
	38	u32 offset;
	39	u32 mask;
	40	u32 shift;
	41	u32 value;
	42	enum si_cac_config_reg_type type;
	43	};
	44
	45	struct si_powertune_data
	46	{
	47	u32 cac_window;
	48	u32 l2_lta_window_size_default;
	49	u8 lts_truncate_default;
	50	u8 shift_n_default;
	51	u8 operating_temp;
	52	struct ni_leakage_coeffients leakage_coefficients;
	53	u32 fixed_kt;
	54	u32 lkge_lut_v0_percent;
	55	u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
	56	bool enable_powertune_by_default;
	57	};
	58
	59	struct si_dyn_powertune_data
	60	{
	61	u32 cac_leakage;
	62	s32 leakage_minimum_temperature;
	63	u32 wintime;
	64	u32 l2_lta_window_size;
	65	u8 lts_truncate;
	66	u8 shift_n;
	67	u8 dc_pwr_value;
	68	bool disable_uvd_powertune;
	69	};
	70
	71	struct si_dte_data
	72	{
	73	u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
	74	u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
	75	u32 k;
	76	u32 t0;
	77	u32 max_t;
	78	u8 window_size;
	79	u8 temp_select;
	80	u8 dte_mode;
	81	u8 tdep_count;
	82	u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
	83	u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
	84	u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
	85	u32 t_threshold;
	86	bool enable_dte_by_default;
	87	};
	88
	89	struct si_clock_registers {
	90	u32 cg_spll_func_cntl;
	91	u32 cg_spll_func_cntl_2;
	92	u32 cg_spll_func_cntl_3;
	93	u32 cg_spll_func_cntl_4;
	94	u32 cg_spll_spread_spectrum;
	95	u32 cg_spll_spread_spectrum_2;
	96	u32 dll_cntl;
	97	u32 mclk_pwrmgt_cntl;
	98	u32 mpll_ad_func_cntl;
	99	u32 mpll_dq_func_cntl;
	100	u32 mpll_func_cntl;
	101	u32 mpll_func_cntl_1;
	102	u32 mpll_func_cntl_2;
	103	u32 mpll_ss1;
	104	u32 mpll_ss2;
	105	};
	106
	107	struct si_mc_reg_entry {
	108	u32 mclk_max;
	109	u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
	110	};
	111
	112	struct si_mc_reg_table {
	113	u8 last;
	114	u8 num_entries;
	115	u16 valid_flag;
	116	struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
	117	SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
	118	};
	119
	120	#define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0
	121	#define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1
	122	#define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2
	123	#define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3
	124
	125	struct si_leakage_voltage_entry
	126	{
	127	u16 voltage;
	128	u16 leakage_index;
	129	};
	130
	131	#define SISLANDS_LEAKAGE_INDEX0 0xff01
	132	#define SISLANDS_MAX_LEAKAGE_COUNT 4
	133
	134	struct si_leakage_voltage
	135	{
	136	u16 count;
	137	struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];
	138	};
	139
	140	#define SISLANDS_MAX_HARDWARE_POWERLEVELS 5
	141
	142	struct si_ulv_param {
	143	bool supported;
	144	u32 cg_ulv_control;
	145	u32 cg_ulv_parameter;
	146	u32 volt_change_delay;
	147	struct rv7xx_pl pl;
	148	bool one_pcie_lane_in_ulv;
	149	};
	150
	151	struct si_power_info {
	152	/* must be first! */
	153	struct ni_power_info ni;
	154	struct si_clock_registers clock_registers;
	155	struct si_mc_reg_table mc_reg_table;
	156	struct atom_voltage_table mvdd_voltage_table;
	157	struct atom_voltage_table vddc_phase_shed_table;
	158	struct si_leakage_voltage leakage_voltage;
	159	u16 mvdd_bootup_value;
	160	struct si_ulv_param ulv;
	161	u32 max_cu;
	162	/* pcie gen */
	163	enum radeon_pcie_gen force_pcie_gen;
	164	enum radeon_pcie_gen boot_pcie_gen;
	165	enum radeon_pcie_gen acpi_pcie_gen;
	166	u32 sys_pcie_mask;
	167	/* flags */
	168	bool enable_dte;
	169	bool enable_ppm;
	170	bool vddc_phase_shed_control;
	171	bool pspp_notify_required;
	172	bool sclk_deep_sleep_above_low;
	173	/* smc offsets */
	174	u32 sram_end;
	175	u32 state_table_start;
	176	u32 soft_regs_start;
	177	u32 mc_reg_table_start;
	178	u32 arb_table_start;
	179	u32 cac_table_start;
	180	u32 dte_table_start;
	181	u32 spll_table_start;
	182	u32 papm_cfg_table_start;
	183	/* CAC stuff */
	184	const struct si_cac_config_reg *cac_weights;
	185	const struct si_cac_config_reg *lcac_config;
	186	const struct si_cac_config_reg *cac_override;
	187	const struct si_powertune_data *powertune_data;
	188	struct si_dyn_powertune_data dyn_powertune_data;
	189	/* DTE stuff */
	190	struct si_dte_data dte_data;
	191	/* scratch structs */
	192	SMC_SIslands_MCRegisters smc_mc_reg_table;
	193	SISLANDS_SMC_STATETABLE smc_statetable;
	194	PP_SIslands_PAPMParameters papm_parm;
	195	};
	196
	197	#define SISLANDS_INITIAL_STATE_ARB_INDEX 0
	198	#define SISLANDS_ACPI_STATE_ARB_INDEX 1
	199	#define SISLANDS_ULV_STATE_ARB_INDEX 2
	200	#define SISLANDS_DRIVER_STATE_ARB_INDEX 3
	201
	202	#define SISLANDS_DPM2_MAX_PULSE_SKIP 256
	203
	204	#define SISLANDS_DPM2_NEAR_TDP_DEC 10
	205	#define SISLANDS_DPM2_ABOVE_SAFE_INC 5
	206	#define SISLANDS_DPM2_BELOW_SAFE_INC 20
	207
	208	#define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80
	209
	210	#define SISLANDS_DPM2_MAXPS_PERCENT_H 99
	211	#define SISLANDS_DPM2_MAXPS_PERCENT_M 99
	212
	213	#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
	214	#define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12
	215	#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
	216	#define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E
	217	#define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF
	218
	219	#define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10
	220
	221	#define SISLANDS_VRC_DFLT 0xC000B3
	222	#define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687
	223	#define SISLANDS_CGULVPARAMETER_DFLT 0x00040035
	224	#define SISLANDS_CGULVCONTROL_DFLT 0x1f007550
	225
	226
	227	#endif