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authorChristian König <deathsimple@vodafone.de>2013-04-08 06:41:29 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-04-09 10:31:33 -0400
commitf2ba57b5eab8817d86d0f108fdf1878e51dc0a37 (patch)
treee784f0573069f6341768968fe3d49df6d2c9a534 /drivers/gpu/drm/radeon/si.c
parent4474f3a91f95e3fcc62d97e36f1e8e3392c96ee0 (diff)
drm/radeon: UVD bringup v8
Just everything needed to decode videos using UVD. v6: just all the bugfixes and support for R7xx-SI merged in one patch v7: UVD_CGC_GATE is a write only register, lockup detection fix v8: split out VRAM fallback changes, remove support for RV770, add support for HEMLOCK, add buffer sizes checks Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c32
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index ace45da91434..3e9782dc35bf 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4333,6 +4333,16 @@ static int si_startup(struct radeon_device *rdev)
4333 return r; 4333 return r;
4334 } 4334 }
4335 4335
4336 r = rv770_uvd_resume(rdev);
4337 if (!r) {
4338 r = radeon_fence_driver_start_ring(rdev,
4339 R600_RING_TYPE_UVD_INDEX);
4340 if (r)
4341 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
4342 }
4343 if (r)
4344 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
4345
4336 /* Enable IRQ */ 4346 /* Enable IRQ */
4337 r = si_irq_init(rdev); 4347 r = si_irq_init(rdev);
4338 if (r) { 4348 if (r) {
@@ -4390,6 +4400,18 @@ static int si_startup(struct radeon_device *rdev)
4390 if (r) 4400 if (r)
4391 return r; 4401 return r;
4392 4402
4403 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4404 if (ring->ring_size) {
4405 r = radeon_ring_init(rdev, ring, ring->ring_size,
4406 R600_WB_UVD_RPTR_OFFSET,
4407 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
4408 0, 0xfffff, RADEON_CP_PACKET2);
4409 if (!r)
4410 r = r600_uvd_init(rdev);
4411 if (r)
4412 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
4413 }
4414
4393 r = radeon_ib_pool_init(rdev); 4415 r = radeon_ib_pool_init(rdev);
4394 if (r) { 4416 if (r) {
4395 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 4417 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -4433,6 +4455,8 @@ int si_suspend(struct radeon_device *rdev)
4433 radeon_vm_manager_fini(rdev); 4455 radeon_vm_manager_fini(rdev);
4434 si_cp_enable(rdev, false); 4456 si_cp_enable(rdev, false);
4435 cayman_dma_stop(rdev); 4457 cayman_dma_stop(rdev);
4458 r600_uvd_rbc_stop(rdev);
4459 radeon_uvd_suspend(rdev);
4436 si_irq_suspend(rdev); 4460 si_irq_suspend(rdev);
4437 radeon_wb_disable(rdev); 4461 radeon_wb_disable(rdev);
4438 si_pcie_gart_disable(rdev); 4462 si_pcie_gart_disable(rdev);
@@ -4518,6 +4542,13 @@ int si_init(struct radeon_device *rdev)
4518 ring->ring_obj = NULL; 4542 ring->ring_obj = NULL;
4519 r600_ring_init(rdev, ring, 64 * 1024); 4543 r600_ring_init(rdev, ring, 64 * 1024);
4520 4544
4545 r = radeon_uvd_init(rdev);
4546 if (!r) {
4547 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
4548 ring->ring_obj = NULL;
4549 r600_ring_init(rdev, ring, 4096);
4550 }
4551
4521 rdev->ih.ring_obj = NULL; 4552 rdev->ih.ring_obj = NULL;
4522 r600_ih_ring_init(rdev, 64 * 1024); 4553 r600_ih_ring_init(rdev, 64 * 1024);
4523 4554
@@ -4566,6 +4597,7 @@ void si_fini(struct radeon_device *rdev)
4566 radeon_vm_manager_fini(rdev); 4597 radeon_vm_manager_fini(rdev);
4567 radeon_ib_pool_fini(rdev); 4598 radeon_ib_pool_fini(rdev);
4568 radeon_irq_kms_fini(rdev); 4599 radeon_irq_kms_fini(rdev);
4600 radeon_uvd_fini(rdev);
4569 si_pcie_gart_fini(rdev); 4601 si_pcie_gart_fini(rdev);
4570 r600_vram_scratch_fini(rdev); 4602 r600_vram_scratch_fini(rdev);
4571 radeon_gem_fini(rdev); 4603 radeon_gem_fini(rdev);