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authorAlex Deucher <alexander.deucher@amd.com>2012-08-30 14:34:30 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-05-20 12:09:35 -0400
commit5153550ad7e1d8e7344aded830258d5be7292989 (patch)
treeea35603276c4f58d384b8c3a8b9c6b42c0f1751a /drivers/gpu/drm/radeon/si.c
parent8b02859d771e0f2800b841c4c7eb17f3a7852b88 (diff)
drm/radeon: don't touch DCE or VGA regs on Hainan (v3)
Hainan has no display hardware: - no DCE (crtc, uniphy, dac, etc.) - no VGA v2: fix bios fetch v3: fix interrupts Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c99
1 files changed, 59 insertions, 40 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 1d8c61518ff6..14472cca75ba 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3322,8 +3322,9 @@ static void si_mc_program(struct radeon_device *rdev)
3322 if (radeon_mc_wait_for_idle(rdev)) { 3322 if (radeon_mc_wait_for_idle(rdev)) {
3323 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 3323 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3324 } 3324 }
3325 /* Lockout access through VGA aperture*/ 3325 if (!ASIC_IS_NODCE(rdev))
3326 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 3326 /* Lockout access through VGA aperture*/
3327 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3327 /* Update configuration */ 3328 /* Update configuration */
3328 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 3329 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
3329 rdev->mc.vram_start >> 12); 3330 rdev->mc.vram_start >> 12);
@@ -3345,9 +3346,11 @@ static void si_mc_program(struct radeon_device *rdev)
3345 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 3346 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3346 } 3347 }
3347 evergreen_mc_resume(rdev, &save); 3348 evergreen_mc_resume(rdev, &save);
3348 /* we need to own VRAM, so turn off the VGA renderer here 3349 if (!ASIC_IS_NODCE(rdev)) {
3349 * to stop it overwriting our objects */ 3350 /* we need to own VRAM, so turn off the VGA renderer here
3350 rv515_vga_render_disable(rdev); 3351 * to stop it overwriting our objects */
3352 rv515_vga_render_disable(rdev);
3353 }
3351} 3354}
3352 3355
3353static void si_vram_gtt_location(struct radeon_device *rdev, 3356static void si_vram_gtt_location(struct radeon_device *rdev,
@@ -4269,8 +4272,10 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
4269 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 4272 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
4270 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); 4273 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
4271 WREG32(GRBM_INT_CNTL, 0); 4274 WREG32(GRBM_INT_CNTL, 0);
4272 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 4275 if (rdev->num_crtc >= 2) {
4273 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 4276 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
4277 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
4278 }
4274 if (rdev->num_crtc >= 4) { 4279 if (rdev->num_crtc >= 4) {
4275 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 4280 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
4276 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 4281 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
@@ -4280,8 +4285,10 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
4280 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 4285 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
4281 } 4286 }
4282 4287
4283 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 4288 if (rdev->num_crtc >= 2) {
4284 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 4289 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
4290 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
4291 }
4285 if (rdev->num_crtc >= 4) { 4292 if (rdev->num_crtc >= 4) {
4286 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 4293 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
4287 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 4294 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
@@ -4291,21 +4298,22 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
4291 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 4298 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
4292 } 4299 }
4293 4300
4294 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 4301 if (!ASIC_IS_NODCE(rdev)) {
4295 4302 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
4296 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4297 WREG32(DC_HPD1_INT_CONTROL, tmp);
4298 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4299 WREG32(DC_HPD2_INT_CONTROL, tmp);
4300 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4301 WREG32(DC_HPD3_INT_CONTROL, tmp);
4302 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4303 WREG32(DC_HPD4_INT_CONTROL, tmp);
4304 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4305 WREG32(DC_HPD5_INT_CONTROL, tmp);
4306 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4307 WREG32(DC_HPD6_INT_CONTROL, tmp);
4308 4303
4304 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4305 WREG32(DC_HPD1_INT_CONTROL, tmp);
4306 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4307 WREG32(DC_HPD2_INT_CONTROL, tmp);
4308 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4309 WREG32(DC_HPD3_INT_CONTROL, tmp);
4310 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4311 WREG32(DC_HPD4_INT_CONTROL, tmp);
4312 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4313 WREG32(DC_HPD5_INT_CONTROL, tmp);
4314 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4315 WREG32(DC_HPD6_INT_CONTROL, tmp);
4316 }
4309} 4317}
4310 4318
4311static int si_irq_init(struct radeon_device *rdev) 4319static int si_irq_init(struct radeon_device *rdev)
@@ -4384,7 +4392,7 @@ int si_irq_set(struct radeon_device *rdev)
4384 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 4392 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
4385 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; 4393 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
4386 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 4394 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
4387 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 4395 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
4388 u32 grbm_int_cntl = 0; 4396 u32 grbm_int_cntl = 0;
4389 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 4397 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
4390 u32 dma_cntl, dma_cntl1; 4398 u32 dma_cntl, dma_cntl1;
@@ -4401,12 +4409,14 @@ int si_irq_set(struct radeon_device *rdev)
4401 return 0; 4409 return 0;
4402 } 4410 }
4403 4411
4404 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 4412 if (!ASIC_IS_NODCE(rdev)) {
4405 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 4413 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
4406 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 4414 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
4407 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 4415 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
4408 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 4416 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
4409 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 4417 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
4418 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
4419 }
4410 4420
4411 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 4421 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
4412 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 4422 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
@@ -4497,8 +4507,10 @@ int si_irq_set(struct radeon_device *rdev)
4497 4507
4498 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 4508 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
4499 4509
4500 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 4510 if (rdev->num_crtc >= 2) {
4501 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 4511 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
4512 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
4513 }
4502 if (rdev->num_crtc >= 4) { 4514 if (rdev->num_crtc >= 4) {
4503 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 4515 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
4504 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 4516 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
@@ -4508,8 +4520,10 @@ int si_irq_set(struct radeon_device *rdev)
4508 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 4520 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
4509 } 4521 }
4510 4522
4511 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 4523 if (rdev->num_crtc >= 2) {
4512 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 4524 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
4525 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
4526 }
4513 if (rdev->num_crtc >= 4) { 4527 if (rdev->num_crtc >= 4) {
4514 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 4528 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
4515 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 4529 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
@@ -4519,12 +4533,14 @@ int si_irq_set(struct radeon_device *rdev)
4519 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 4533 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
4520 } 4534 }
4521 4535
4522 WREG32(DC_HPD1_INT_CONTROL, hpd1); 4536 if (!ASIC_IS_NODCE(rdev)) {
4523 WREG32(DC_HPD2_INT_CONTROL, hpd2); 4537 WREG32(DC_HPD1_INT_CONTROL, hpd1);
4524 WREG32(DC_HPD3_INT_CONTROL, hpd3); 4538 WREG32(DC_HPD2_INT_CONTROL, hpd2);
4525 WREG32(DC_HPD4_INT_CONTROL, hpd4); 4539 WREG32(DC_HPD3_INT_CONTROL, hpd3);
4526 WREG32(DC_HPD5_INT_CONTROL, hpd5); 4540 WREG32(DC_HPD4_INT_CONTROL, hpd4);
4527 WREG32(DC_HPD6_INT_CONTROL, hpd6); 4541 WREG32(DC_HPD5_INT_CONTROL, hpd5);
4542 WREG32(DC_HPD6_INT_CONTROL, hpd6);
4543 }
4528 4544
4529 return 0; 4545 return 0;
4530} 4546}
@@ -4533,6 +4549,9 @@ static inline void si_irq_ack(struct radeon_device *rdev)
4533{ 4549{
4534 u32 tmp; 4550 u32 tmp;
4535 4551
4552 if (ASIC_IS_NODCE(rdev))
4553 return;
4554
4536 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); 4555 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
4537 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 4556 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
4538 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 4557 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);