drm/radeon/kms: add dpm support for rv7xx (v4)

This adds dpm support for rv7xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: reduce stack usage v3: fix 64 bit div v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
author: Alex Deucher <alexander.deucher@amd.com> 2013-06-26 00:11:19 -0400
committer: Alex Deucher <alexander.deucher@amd.com> 2013-06-27 19:14:59 -0400
commit: 66229b200598a3b66b839d1759ff3f5b17ac5639 (patch)
tree: 5bfb3d7ba630171afe67c9aeae007a1db03d22d3 /drivers/gpu/drm/radeon/rv770_dpm.h
parent: 4a6369e9935e392402d4ccb67f5cddac953e8d3c (diff)
1 files changed, 273 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.h b/drivers/gpu/drm/radeon/rv770_dpm.h
new file mode 100644
index 000000000000..0f33f9bb244f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv770_dpm.h
@@ -0,0 +1,273 @@
+/*
+ * Copyright 2011 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __RV770_DPM_H__
+#define __RV770_DPM_H__
+#include "rv770_smc.h"
+struct rv770_clock_registers {
+        u32 cg_spll_func_cntl;
+        u32 cg_spll_func_cntl_2;
+        u32 cg_spll_func_cntl_3;
+        u32 cg_spll_spread_spectrum;
+        u32 cg_spll_spread_spectrum_2;
+        u32 mpll_ad_func_cntl;
+        u32 mpll_ad_func_cntl_2;
+        u32 mpll_dq_func_cntl;
+        u32 mpll_dq_func_cntl_2;
+        u32 mclk_pwrmgt_cntl;
+        u32 dll_cntl;
+        u32 mpll_ss1;
+        u32 mpll_ss2;
+};
+struct rv730_clock_registers {
+        u32 cg_spll_func_cntl;
+        u32 cg_spll_func_cntl_2;
+        u32 cg_spll_func_cntl_3;
+        u32 cg_spll_spread_spectrum;
+        u32 cg_spll_spread_spectrum_2;
+        u32 mclk_pwrmgt_cntl;
+        u32 dll_cntl;
+        u32 mpll_func_cntl;
+        u32 mpll_func_cntl2;
+        u32 mpll_func_cntl3;
+        u32 mpll_ss;
+        u32 mpll_ss2;
+};
+union r7xx_clock_registers {
+        struct rv770_clock_registers rv770;
+        struct rv730_clock_registers rv730;
+};
+struct vddc_table_entry {
+        u16 vddc;
+        u8 vddc_index;
+        u8 high_smio;
+        u32 low_smio;
+};
+#define MAX_NO_OF_MVDD_VALUES 2
+#define MAX_NO_VREG_STEPS 32
+struct rv7xx_power_info {
+        /* flags */
+        bool mem_gddr5;
+        bool pcie_gen2;
+        bool dynamic_pcie_gen2;
+        bool acpi_pcie_gen2;
+        bool boot_in_gen2;
+        bool voltage_control; /* vddc */
+        bool mvdd_control;
+        bool sclk_ss;
+        bool mclk_ss;
+        bool dynamic_ss;
+        bool gfx_clock_gating;
+        bool mg_clock_gating;
+        bool mgcgtssm;
+        bool power_gating;
+        bool thermal_protection;
+        bool display_gap;
+        bool dcodt;
+        bool ulps;
+        /* registers */
+        union r7xx_clock_registers clk_regs;
+        u32 s0_vid_lower_smio_cntl;
+        /* voltage */
+        u32 vddc_mask_low;
+        u32 mvdd_mask_low;
+        u32 mvdd_split_frequency;
+        u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
+        u16 max_vddc;
+        u16 max_vddc_in_table;
+        u16 min_vddc_in_table;
+        struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
+        u8 valid_vddc_entries;
+        /* dc odt */
+        u32 mclk_odt_threshold;
+        u8 odt_value_0[2];
+        u8 odt_value_1[2];
+        /* stored values */
+        u32 boot_sclk;
+        u16 acpi_vddc;
+        u32 ref_div;
+        u32 active_auto_throttle_sources;
+        u32 mclk_stutter_mode_threshold;
+        u32 mclk_strobe_mode_threshold;
+        u32 mclk_edc_enable_threshold;
+        u32 bsp;
+        u32 bsu;
+        u32 pbsp;
+        u32 pbsu;
+        u32 dsp;
+        u32 psp;
+        u32 asi;
+        u32 pasi;
+        u32 vrc;
+        u32 restricted_levels;
+        /* smc offsets */
+        u16 state_table_start;
+        u16 soft_regs_start;
+        u16 sram_end;
+        /* scratch structs */
+        RV770_SMC_STATETABLE smc_statetable;
+};
+struct rv7xx_pl {
+        u32 sclk;
+        u32 mclk;
+        u16 vddc;
+        u16 vddci; /* eg+ only */
+        u32 flags;
+};
+struct rv7xx_ps {
+        struct rv7xx_pl high;
+        struct rv7xx_pl medium;
+        struct rv7xx_pl low;
+        bool dc_compatible;
+};
+#define RV770_RLP_DFLT                                10
+#define RV770_RMP_DFLT                                25
+#define RV770_LHP_DFLT                                25
+#define RV770_LMP_DFLT                                10
+#define RV770_VRC_DFLT                                0x003f
+#define RV770_ASI_DFLT                                1000
+#define RV770_HASI_DFLT                               200000
+#define RV770_MGCGTTLOCAL0_DFLT                       0x00100000
+#define RV7XX_MGCGTTLOCAL0_DFLT                       0
+#define RV770_MGCGTTLOCAL1_DFLT                       0xFFFF0000
+#define RV770_MGCGCGTSSMCTRL_DFLT                     0x55940000
+#define MVDD_LOW_INDEX  0
+#define MVDD_HIGH_INDEX 1
+#define MVDD_LOW_VALUE  0
+#define MVDD_HIGH_VALUE 0xffff
+#define RV770_DEFAULT_VCLK_FREQ  53300 /* 10 khz */
+#define RV770_DEFAULT_DCLK_FREQ  40000 /* 10 khz */
+/* rv730/rv710 */
+int rv730_populate_sclk_value(struct radeon_device *rdev,
+                              u32 engine_clock,
+                              RV770_SMC_SCLK_VALUE *sclk);
+int rv730_populate_mclk_value(struct radeon_device *rdev,
+                              u32 engine_clock, u32 memory_clock,
+                              LPRV7XX_SMC_MCLK_VALUE mclk);
+void rv730_read_clock_registers(struct radeon_device *rdev);
+int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
+                                  RV770_SMC_STATETABLE *table);
+int rv730_populate_smc_initial_state(struct radeon_device *rdev,
+                                     struct radeon_ps *radeon_initial_state,
+                                     RV770_SMC_STATETABLE *table);
+void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
+                                            struct radeon_ps *radeon_state);
+void rv730_power_gating_enable(struct radeon_device *rdev,
+                               bool enable);
+void rv730_start_dpm(struct radeon_device *rdev);
+void rv730_stop_dpm(struct radeon_device *rdev);
+void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt);
+void rv730_get_odt_values(struct radeon_device *rdev);
+/* rv740 */
+int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
+                              RV770_SMC_SCLK_VALUE *sclk);
+int rv740_populate_mclk_value(struct radeon_device *rdev,
+                              u32 engine_clock, u32 memory_clock,
+                              RV7XX_SMC_MCLK_VALUE *mclk);
+void rv740_read_clock_registers(struct radeon_device *rdev);
+int rv740_populate_smc_acpi_state(struct radeon_device *rdev,
+                                  RV770_SMC_STATETABLE *table);
+void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev,
+                                       bool enable);
+u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
+u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
+u32 rv740_get_decoded_reference_divider(u32 encoded_ref);
+/* rv770 */
+u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
+int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
+                              RV770_SMC_VOLTAGE_VALUE *voltage);
+int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
+                              RV770_SMC_VOLTAGE_VALUE *voltage);
+u8 rv770_get_seq_value(struct radeon_device *rdev,
+                       struct rv7xx_pl *pl);
+int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
+                                      RV770_SMC_VOLTAGE_VALUE *voltage);
+u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
+                                        u32 engine_clock);
+void rv770_program_response_times(struct radeon_device *rdev);
+int rv770_populate_smc_sp(struct radeon_device *rdev,
+                          struct radeon_ps *radeon_state,
+                          RV770_SMC_SWSTATE *smc_state);
+int rv770_populate_smc_t(struct radeon_device *rdev,
+                         struct radeon_ps *radeon_state,
+                         RV770_SMC_SWSTATE *smc_state);
+void rv770_read_voltage_smio_registers(struct radeon_device *rdev);
+void rv770_get_memory_type(struct radeon_device *rdev);
+void r7xx_start_smc(struct radeon_device *rdev);
+u8 rv770_get_memory_module_index(struct radeon_device *rdev);
+void rv770_get_max_vddc(struct radeon_device *rdev);
+void rv770_get_pcie_gen2_status(struct radeon_device *rdev);
+void rv770_enable_acpi_pm(struct radeon_device *rdev);
+void rv770_restore_cgcg(struct radeon_device *rdev);
+bool rv770_dpm_enabled(struct radeon_device *rdev);
+void rv770_enable_voltage_control(struct radeon_device *rdev,
+                                  bool enable);
+void rv770_enable_backbias(struct radeon_device *rdev,
+                           bool enable);
+void rv770_enable_thermal_protection(struct radeon_device *rdev,
+                                     bool enable);
+void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
+                                       enum radeon_dpm_auto_throttle_src source,
+                                       bool enable);
+void rv770_setup_bsp(struct radeon_device *rdev);
+void rv770_program_git(struct radeon_device *rdev);
+void rv770_program_tp(struct radeon_device *rdev);
+void rv770_program_tpp(struct radeon_device *rdev);
+void rv770_program_sstp(struct radeon_device *rdev);
+void rv770_program_engine_speed_parameters(struct radeon_device *rdev);
+void rv770_program_vc(struct radeon_device *rdev);
+void rv770_clear_vc(struct radeon_device *rdev);
+int rv770_upload_firmware(struct radeon_device *rdev);
+void rv770_stop_dpm(struct radeon_device *rdev);
+void r7xx_stop_smc(struct radeon_device *rdev);
+void rv770_reset_smio_status(struct radeon_device *rdev);
+int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev);
+int rv770_unrestrict_performance_levels_after_switch(struct radeon_device *rdev);
+int rv770_halt_smc(struct radeon_device *rdev);
+int rv770_resume_smc(struct radeon_device *rdev);
+int rv770_set_sw_state(struct radeon_device *rdev);
+int rv770_set_boot_state(struct radeon_device *rdev);
+int rv7xx_parse_power_table(struct radeon_device *rdev);
+/* smc */
+int rv770_read_smc_soft_register(struct radeon_device *rdev,
+                                 u16 reg_offset, u32 *value);
+int rv770_write_smc_soft_register(struct radeon_device *rdev,
+                                  u16 reg_offset, u32 value);
+#endif
author	Alex Deucher <alexander.deucher@amd.com>	2013-06-26 00:11:19 -0400
committer	Alex Deucher <alexander.deucher@amd.com>	2013-06-27 19:14:59 -0400
commit	66229b200598a3b66b839d1759ff3f5b17ac5639 (patch)
tree	5bfb3d7ba630171afe67c9aeae007a1db03d22d3 /drivers/gpu/drm/radeon/rv770_dpm.h
parent	4a6369e9935e392402d4ccb67f5cddac953e8d3c (diff)

diff --git a/drivers/gpu/drm/radeon/rv770_dpm.h b/drivers/gpu/drm/radeon/rv770_dpm.h new file mode 100644 index 000000000000..0f33f9bb244f --- /dev/null +++ b/drivers/gpu/drm/radeon/rv770_dpm.h
@@ -0,0 +1,273 @@
	1	/*
	2	* Copyright 2011 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef __RV770_DPM_H__
	24	#define __RV770_DPM_H__
	25
	26	#include "rv770_smc.h"
	27
	28	struct rv770_clock_registers {
	29	u32 cg_spll_func_cntl;
	30	u32 cg_spll_func_cntl_2;
	31	u32 cg_spll_func_cntl_3;
	32	u32 cg_spll_spread_spectrum;
	33	u32 cg_spll_spread_spectrum_2;
	34	u32 mpll_ad_func_cntl;
	35	u32 mpll_ad_func_cntl_2;
	36	u32 mpll_dq_func_cntl;
	37	u32 mpll_dq_func_cntl_2;
	38	u32 mclk_pwrmgt_cntl;
	39	u32 dll_cntl;
	40	u32 mpll_ss1;
	41	u32 mpll_ss2;
	42	};
	43
	44	struct rv730_clock_registers {
	45	u32 cg_spll_func_cntl;
	46	u32 cg_spll_func_cntl_2;
	47	u32 cg_spll_func_cntl_3;
	48	u32 cg_spll_spread_spectrum;
	49	u32 cg_spll_spread_spectrum_2;
	50	u32 mclk_pwrmgt_cntl;
	51	u32 dll_cntl;
	52	u32 mpll_func_cntl;
	53	u32 mpll_func_cntl2;
	54	u32 mpll_func_cntl3;
	55	u32 mpll_ss;
	56	u32 mpll_ss2;
	57	};
	58
	59	union r7xx_clock_registers {
	60	struct rv770_clock_registers rv770;
	61	struct rv730_clock_registers rv730;
	62	};
	63
	64	struct vddc_table_entry {
	65	u16 vddc;
	66	u8 vddc_index;
	67	u8 high_smio;
	68	u32 low_smio;
	69	};
	70
	71	#define MAX_NO_OF_MVDD_VALUES 2
	72	#define MAX_NO_VREG_STEPS 32
	73
	74	struct rv7xx_power_info {
	75	/* flags */
	76	bool mem_gddr5;
	77	bool pcie_gen2;
	78	bool dynamic_pcie_gen2;
	79	bool acpi_pcie_gen2;
	80	bool boot_in_gen2;
	81	bool voltage_control; /* vddc */
	82	bool mvdd_control;
	83	bool sclk_ss;
	84	bool mclk_ss;
	85	bool dynamic_ss;
	86	bool gfx_clock_gating;
	87	bool mg_clock_gating;
	88	bool mgcgtssm;
	89	bool power_gating;
	90	bool thermal_protection;
	91	bool display_gap;
	92	bool dcodt;
	93	bool ulps;
	94	/* registers */
	95	union r7xx_clock_registers clk_regs;
	96	u32 s0_vid_lower_smio_cntl;
	97	/* voltage */
	98	u32 vddc_mask_low;
	99	u32 mvdd_mask_low;
	100	u32 mvdd_split_frequency;
	101	u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
	102	u16 max_vddc;
	103	u16 max_vddc_in_table;
	104	u16 min_vddc_in_table;
	105	struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
	106	u8 valid_vddc_entries;
	107	/* dc odt */
	108	u32 mclk_odt_threshold;
	109	u8 odt_value_0[2];
	110	u8 odt_value_1[2];
	111	/* stored values */
	112	u32 boot_sclk;
	113	u16 acpi_vddc;
	114	u32 ref_div;
	115	u32 active_auto_throttle_sources;
	116	u32 mclk_stutter_mode_threshold;
	117	u32 mclk_strobe_mode_threshold;
	118	u32 mclk_edc_enable_threshold;
	119	u32 bsp;
	120	u32 bsu;
	121	u32 pbsp;
	122	u32 pbsu;
	123	u32 dsp;
	124	u32 psp;
	125	u32 asi;
	126	u32 pasi;
	127	u32 vrc;
	128	u32 restricted_levels;
	129	/* smc offsets */
	130	u16 state_table_start;
	131	u16 soft_regs_start;
	132	u16 sram_end;
	133	/* scratch structs */
	134	RV770_SMC_STATETABLE smc_statetable;
	135	};
	136
	137	struct rv7xx_pl {
	138	u32 sclk;
	139	u32 mclk;
	140	u16 vddc;
	141	u16 vddci; /* eg+ only */
	142	u32 flags;
	143	};
	144
	145	struct rv7xx_ps {
	146	struct rv7xx_pl high;
	147	struct rv7xx_pl medium;
	148	struct rv7xx_pl low;
	149	bool dc_compatible;
	150	};
	151
	152	#define RV770_RLP_DFLT 10
	153	#define RV770_RMP_DFLT 25
	154	#define RV770_LHP_DFLT 25
	155	#define RV770_LMP_DFLT 10
	156	#define RV770_VRC_DFLT 0x003f
	157	#define RV770_ASI_DFLT 1000
	158	#define RV770_HASI_DFLT 200000
	159	#define RV770_MGCGTTLOCAL0_DFLT 0x00100000
	160	#define RV7XX_MGCGTTLOCAL0_DFLT 0
	161	#define RV770_MGCGTTLOCAL1_DFLT 0xFFFF0000
	162	#define RV770_MGCGCGTSSMCTRL_DFLT 0x55940000
	163
	164	#define MVDD_LOW_INDEX 0
	165	#define MVDD_HIGH_INDEX 1
	166
	167	#define MVDD_LOW_VALUE 0
	168	#define MVDD_HIGH_VALUE 0xffff
	169
	170	#define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */
	171	#define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */
	172
	173	/* rv730/rv710 */
	174	int rv730_populate_sclk_value(struct radeon_device *rdev,
	175	u32 engine_clock,
	176	RV770_SMC_SCLK_VALUE *sclk);
	177	int rv730_populate_mclk_value(struct radeon_device *rdev,
	178	u32 engine_clock, u32 memory_clock,
	179	LPRV7XX_SMC_MCLK_VALUE mclk);
	180	void rv730_read_clock_registers(struct radeon_device *rdev);
	181	int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
	182	RV770_SMC_STATETABLE *table);
	183	int rv730_populate_smc_initial_state(struct radeon_device *rdev,
	184	struct radeon_ps *radeon_initial_state,
	185	RV770_SMC_STATETABLE *table);
	186	void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
	187	struct radeon_ps *radeon_state);
	188	void rv730_power_gating_enable(struct radeon_device *rdev,
	189	bool enable);
	190	void rv730_start_dpm(struct radeon_device *rdev);
	191	void rv730_stop_dpm(struct radeon_device *rdev);
	192	void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt);
	193	void rv730_get_odt_values(struct radeon_device *rdev);
	194
	195	/* rv740 */
	196	int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
	197	RV770_SMC_SCLK_VALUE *sclk);
	198	int rv740_populate_mclk_value(struct radeon_device *rdev,
	199	u32 engine_clock, u32 memory_clock,
	200	RV7XX_SMC_MCLK_VALUE *mclk);
	201	void rv740_read_clock_registers(struct radeon_device *rdev);
	202	int rv740_populate_smc_acpi_state(struct radeon_device *rdev,
	203	RV770_SMC_STATETABLE *table);
	204	void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev,
	205	bool enable);
	206	u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
	207	u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
	208	u32 rv740_get_decoded_reference_divider(u32 encoded_ref);
	209
	210	/* rv770 */
	211	u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
	212	int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
	213	RV770_SMC_VOLTAGE_VALUE *voltage);
	214	int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
	215	RV770_SMC_VOLTAGE_VALUE *voltage);
	216	u8 rv770_get_seq_value(struct radeon_device *rdev,
	217	struct rv7xx_pl *pl);
	218	int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
	219	RV770_SMC_VOLTAGE_VALUE *voltage);
	220	u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
	221	u32 engine_clock);
	222	void rv770_program_response_times(struct radeon_device *rdev);
	223	int rv770_populate_smc_sp(struct radeon_device *rdev,
	224	struct radeon_ps *radeon_state,
	225	RV770_SMC_SWSTATE *smc_state);
	226	int rv770_populate_smc_t(struct radeon_device *rdev,
	227	struct radeon_ps *radeon_state,
	228	RV770_SMC_SWSTATE *smc_state);
	229	void rv770_read_voltage_smio_registers(struct radeon_device *rdev);
	230	void rv770_get_memory_type(struct radeon_device *rdev);
	231	void r7xx_start_smc(struct radeon_device *rdev);
	232	u8 rv770_get_memory_module_index(struct radeon_device *rdev);
	233	void rv770_get_max_vddc(struct radeon_device *rdev);
	234	void rv770_get_pcie_gen2_status(struct radeon_device *rdev);
	235	void rv770_enable_acpi_pm(struct radeon_device *rdev);
	236	void rv770_restore_cgcg(struct radeon_device *rdev);
	237	bool rv770_dpm_enabled(struct radeon_device *rdev);
	238	void rv770_enable_voltage_control(struct radeon_device *rdev,
	239	bool enable);
	240	void rv770_enable_backbias(struct radeon_device *rdev,
	241	bool enable);
	242	void rv770_enable_thermal_protection(struct radeon_device *rdev,
	243	bool enable);
	244	void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
	245	enum radeon_dpm_auto_throttle_src source,
	246	bool enable);
	247	void rv770_setup_bsp(struct radeon_device *rdev);
	248	void rv770_program_git(struct radeon_device *rdev);
	249	void rv770_program_tp(struct radeon_device *rdev);
	250	void rv770_program_tpp(struct radeon_device *rdev);
	251	void rv770_program_sstp(struct radeon_device *rdev);
	252	void rv770_program_engine_speed_parameters(struct radeon_device *rdev);
	253	void rv770_program_vc(struct radeon_device *rdev);
	254	void rv770_clear_vc(struct radeon_device *rdev);
	255	int rv770_upload_firmware(struct radeon_device *rdev);
	256	void rv770_stop_dpm(struct radeon_device *rdev);
	257	void r7xx_stop_smc(struct radeon_device *rdev);
	258	void rv770_reset_smio_status(struct radeon_device *rdev);
	259	int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev);
	260	int rv770_unrestrict_performance_levels_after_switch(struct radeon_device *rdev);
	261	int rv770_halt_smc(struct radeon_device *rdev);
	262	int rv770_resume_smc(struct radeon_device *rdev);
	263	int rv770_set_sw_state(struct radeon_device *rdev);
	264	int rv770_set_boot_state(struct radeon_device *rdev);
	265	int rv7xx_parse_power_table(struct radeon_device *rdev);
	266
	267	/* smc */
	268	int rv770_read_smc_soft_register(struct radeon_device *rdev,
	269	u16 reg_offset, u32 *value);
	270	int rv770_write_smc_soft_register(struct radeon_device *rdev,
	271	u16 reg_offset, u32 value);
	272
	273	#endif