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authorAlex Deucher <alexander.deucher@amd.com>2013-07-31 18:32:33 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-08-07 17:37:10 -0400
commitb841ce7b41ffbecf84285b381b3ac23f05256d31 (patch)
tree0649a5c0c58f91c824c88789e1e1ee3cad383e08 /drivers/gpu/drm/radeon/rv770_dpm.c
parentfda837241f3680e5dc554c26e178c2deec7a039c (diff)
drm/radeon/dpm: fix spread spectrum setup (v2)
Need to check for engine and memory clock ss separately and only enable dynamic ss if either of them are found. This should fix systems which have a ss table, but do not have entries for engine or memory. On those systems we may enable dynamic spread spectrum without enabling it on the engine or memory clocks which can lead to a hang in some cases. fixes some systems reported here: https://bugs.freedesktop.org/show_bug.cgi?id=66963 v2: fix typo Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv770_dpm.c')
-rw-r--r--drivers/gpu/drm/radeon/rv770_dpm.c30
1 files changed, 17 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index 2ae54bba14d4..094c67a29d0d 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -2319,12 +2319,25 @@ int rv7xx_parse_power_table(struct radeon_device *rdev)
2319 return 0; 2319 return 0;
2320} 2320}
2321 2321
2322void rv770_get_engine_memory_ss(struct radeon_device *rdev)
2323{
2324 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2325 struct radeon_atom_ss ss;
2326
2327 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2328 ASIC_INTERNAL_ENGINE_SS, 0);
2329 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2330 ASIC_INTERNAL_MEMORY_SS, 0);
2331
2332 if (pi->sclk_ss || pi->mclk_ss)
2333 pi->dynamic_ss = true;
2334 else
2335 pi->dynamic_ss = false;
2336}
2337
2322int rv770_dpm_init(struct radeon_device *rdev) 2338int rv770_dpm_init(struct radeon_device *rdev)
2323{ 2339{
2324 struct rv7xx_power_info *pi; 2340 struct rv7xx_power_info *pi;
2325 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
2326 uint16_t data_offset, size;
2327 uint8_t frev, crev;
2328 struct atom_clock_dividers dividers; 2341 struct atom_clock_dividers dividers;
2329 int ret; 2342 int ret;
2330 2343
@@ -2369,16 +2382,7 @@ int rv770_dpm_init(struct radeon_device *rdev)
2369 pi->mvdd_control = 2382 pi->mvdd_control =
2370 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0); 2383 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
2371 2384
2372 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 2385 rv770_get_engine_memory_ss(rdev);
2373 &frev, &crev, &data_offset)) {
2374 pi->sclk_ss = true;
2375 pi->mclk_ss = true;
2376 pi->dynamic_ss = true;
2377 } else {
2378 pi->sclk_ss = false;
2379 pi->mclk_ss = false;
2380 pi->dynamic_ss = false;
2381 }
2382 2386
2383 pi->asi = RV770_ASI_DFLT; 2387 pi->asi = RV770_ASI_DFLT;
2384 pi->pasi = RV770_HASI_DFLT; 2388 pi->pasi = RV770_HASI_DFLT;