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author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-08-05 19:02:01 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-08-05 19:02:01 -0400 |
commit | fc1caf6eafb30ea185720e29f7f5eccca61ecd60 (patch) | |
tree | 666dabc25a9b02e5c05f9eba32fa6b0d8027341a /drivers/gpu/drm/radeon/rv770.c | |
parent | 9779714c8af09d57527f18d9aa2207dcc27a8687 (diff) | |
parent | 96576a9e1a0cdb8a43d3af5846be0948f52b4460 (diff) |
Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (204 commits)
agp: intel-agp: do not use PCI resources before pci_enable_device()
agp: efficeon-agp: do not use PCI resources before pci_enable_device()
drm: kill BKL from common code
drm/kms: Simplify setup of the initial I2C encoder config.
drm,io-mapping: Specify slot to use for atomic mappings
drm/radeon/kms: only expose underscan on avivo chips
drm/radeon: add new pci ids
drm: Cleanup after failing to create master->unique and dev->name
drm/radeon: tone down overchatty acpi debug messages.
drm/radeon/kms: enable underscan option for digital connectors
drm/radeon/kms: fix calculation of h/v scaling factors
drm/radeon/kms/igp: sideport is AMD only
drm/radeon/kms: handle the case of no active displays properly in the bandwidth code
drm: move ttm global code to core drm
drm/i915: Clear the Ironlake dithering flags when the pipe doesn't want it.
drm/radeon/kms: make sure HPD is set to NONE on analog-only connectors
drm/radeon/kms: make sure rio_mem is valid before unmapping it
drm/agp/i915: trim stolen space to 32M
drm/i915: Unset cursor if out-of-bounds upon mode change (v4)
drm/i915: Unreference object not handle on creation
...
Diffstat (limited to 'drivers/gpu/drm/radeon/rv770.c')
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 27 |
1 files changed, 23 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index b7fd82064922..f1c796810117 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -42,6 +42,21 @@ | |||
42 | static void rv770_gpu_init(struct radeon_device *rdev); | 42 | static void rv770_gpu_init(struct radeon_device *rdev); |
43 | void rv770_fini(struct radeon_device *rdev); | 43 | void rv770_fini(struct radeon_device *rdev); |
44 | 44 | ||
45 | /* get temperature in millidegrees */ | ||
46 | u32 rv770_get_temp(struct radeon_device *rdev) | ||
47 | { | ||
48 | u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> | ||
49 | ASIC_T_SHIFT; | ||
50 | u32 actual_temp = 0; | ||
51 | |||
52 | if ((temp >> 9) & 1) | ||
53 | actual_temp = 0; | ||
54 | else | ||
55 | actual_temp = (temp >> 1) & 0xff; | ||
56 | |||
57 | return actual_temp * 1000; | ||
58 | } | ||
59 | |||
45 | void rv770_pm_misc(struct radeon_device *rdev) | 60 | void rv770_pm_misc(struct radeon_device *rdev) |
46 | { | 61 | { |
47 | int req_ps_idx = rdev->pm.requested_power_state_index; | 62 | int req_ps_idx = rdev->pm.requested_power_state_index; |
@@ -189,7 +204,10 @@ static void rv770_mc_program(struct radeon_device *rdev) | |||
189 | WREG32((0x2c20 + j), 0x00000000); | 204 | WREG32((0x2c20 + j), 0x00000000); |
190 | WREG32((0x2c24 + j), 0x00000000); | 205 | WREG32((0x2c24 + j), 0x00000000); |
191 | } | 206 | } |
192 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | 207 | /* r7xx hw bug. Read from HDP_DEBUG1 rather |
208 | * than writing to HDP_REG_COHERENCY_FLUSH_CNTL | ||
209 | */ | ||
210 | tmp = RREG32(HDP_DEBUG1); | ||
193 | 211 | ||
194 | rv515_mc_stop(rdev, &save); | 212 | rv515_mc_stop(rdev, &save); |
195 | if (r600_mc_wait_for_idle(rdev)) { | 213 | if (r600_mc_wait_for_idle(rdev)) { |
@@ -659,8 +677,9 @@ static void rv770_gpu_init(struct radeon_device *rdev) | |||
659 | r600_count_pipe_bits((cc_rb_backend_disable & | 677 | r600_count_pipe_bits((cc_rb_backend_disable & |
660 | R7XX_MAX_BACKENDS_MASK) >> 16)), | 678 | R7XX_MAX_BACKENDS_MASK) >> 16)), |
661 | (cc_rb_backend_disable >> 16)); | 679 | (cc_rb_backend_disable >> 16)); |
662 | gb_tiling_config |= BACKEND_MAP(backend_map); | ||
663 | 680 | ||
681 | rdev->config.rv770.tile_config = gb_tiling_config; | ||
682 | gb_tiling_config |= BACKEND_MAP(backend_map); | ||
664 | 683 | ||
665 | WREG32(GB_TILING_CONFIG, gb_tiling_config); | 684 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
666 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | 685 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
@@ -919,8 +938,8 @@ int rv770_mc_init(struct radeon_device *rdev) | |||
919 | } | 938 | } |
920 | rdev->mc.vram_width = numchan * chansize; | 939 | rdev->mc.vram_width = numchan * chansize; |
921 | /* Could aper size report 0 ? */ | 940 | /* Could aper size report 0 ? */ |
922 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | 941 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
923 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | 942 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
924 | /* Setup GPU memory space */ | 943 | /* Setup GPU memory space */ |
925 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | 944 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
926 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | 945 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |