diff options
author | Jerome Glisse <jglisse@redhat.com> | 2009-09-14 12:29:49 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2009-09-14 18:53:14 -0400 |
commit | 4aac047323e3082d0866b8ad3784236632105af4 (patch) | |
tree | af4c118e42b9ea55c961c4f5bbb02998dc2cc4fe /drivers/gpu/drm/radeon/rv770.c | |
parent | 21f9a437222e92adb3abc68584a5f04801b92739 (diff) |
drm/radeon/kms: clear confusion in GART init/deinit path
GART static one time initialization was mixed up with GART
enabling/disabling which could happen several time for instance
during suspend/resume cycles. This patch splits all GART
handling into 4 differents function. gart_init is for one
time initialization, gart_deinit is called upon module unload
to free resources allocated by gart_init, gart_enable enable
the GART and is intented to be call after first initialization
and at each resume cycle or reset cycle. Finaly gart_disable
stop the GART and is intended to be call at suspend time or
when unloading the module.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv770.c')
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 37 |
1 files changed, 22 insertions, 15 deletions
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 5ba5204091ec..4f2098bc7974 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -48,16 +48,13 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev) | |||
48 | u32 tmp; | 48 | u32 tmp; |
49 | int r, i; | 49 | int r, i; |
50 | 50 | ||
51 | /* Initialize common gart structure */ | 51 | if (rdev->gart.table.vram.robj == NULL) { |
52 | r = radeon_gart_init(rdev); | 52 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
53 | if (r) { | 53 | return -EINVAL; |
54 | return r; | ||
55 | } | 54 | } |
56 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; | 55 | r = radeon_gart_table_vram_pin(rdev); |
57 | r = radeon_gart_table_vram_alloc(rdev); | 56 | if (r) |
58 | if (r) { | ||
59 | return r; | 57 | return r; |
60 | } | ||
61 | for (i = 0; i < rdev->gart.num_gpu_pages; i++) | 58 | for (i = 0; i < rdev->gart.num_gpu_pages; i++) |
62 | r600_gart_clear_page(rdev, i); | 59 | r600_gart_clear_page(rdev, i); |
63 | /* Setup L2 cache */ | 60 | /* Setup L2 cache */ |
@@ -98,10 +95,6 @@ void rv770_pcie_gart_disable(struct radeon_device *rdev) | |||
98 | u32 tmp; | 95 | u32 tmp; |
99 | int i; | 96 | int i; |
100 | 97 | ||
101 | /* Clear ptes*/ | ||
102 | for (i = 0; i < rdev->gart.num_gpu_pages; i++) | ||
103 | r600_gart_clear_page(rdev, i); | ||
104 | r600_pcie_gart_tlb_flush(rdev); | ||
105 | /* Disable all tables */ | 98 | /* Disable all tables */ |
106 | for (i = 0; i < 7; i++) | 99 | for (i = 0; i < 7; i++) |
107 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | 100 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
@@ -120,6 +113,17 @@ void rv770_pcie_gart_disable(struct radeon_device *rdev) | |||
120 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | 113 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
121 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | 114 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
122 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | 115 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
116 | if (rdev->gart.table.vram.robj) { | ||
117 | radeon_object_kunmap(rdev->gart.table.vram.robj); | ||
118 | radeon_object_unpin(rdev->gart.table.vram.robj); | ||
119 | } | ||
120 | } | ||
121 | |||
122 | void rv770_pcie_gart_fini(struct radeon_device *rdev) | ||
123 | { | ||
124 | rv770_pcie_gart_disable(rdev); | ||
125 | radeon_gart_table_vram_free(rdev); | ||
126 | radeon_gart_fini(rdev); | ||
123 | } | 127 | } |
124 | 128 | ||
125 | 129 | ||
@@ -871,6 +875,7 @@ int rv770_suspend(struct radeon_device *rdev) | |||
871 | { | 875 | { |
872 | /* FIXME: we should wait for ring to be empty */ | 876 | /* FIXME: we should wait for ring to be empty */ |
873 | r700_cp_stop(rdev); | 877 | r700_cp_stop(rdev); |
878 | rv770_pcie_gart_disable(rdev); | ||
874 | return 0; | 879 | return 0; |
875 | } | 880 | } |
876 | 881 | ||
@@ -944,6 +949,10 @@ int rv770_init(struct radeon_device *rdev) | |||
944 | } | 949 | } |
945 | } | 950 | } |
946 | 951 | ||
952 | r = r600_pcie_gart_init(rdev); | ||
953 | if (r) | ||
954 | return r; | ||
955 | |||
947 | r = rv770_resume(rdev); | 956 | r = rv770_resume(rdev); |
948 | if (r) { | 957 | if (r) { |
949 | if (rdev->flags & RADEON_IS_AGP) { | 958 | if (rdev->flags & RADEON_IS_AGP) { |
@@ -976,9 +985,7 @@ void rv770_fini(struct radeon_device *rdev) | |||
976 | { | 985 | { |
977 | r600_blit_fini(rdev); | 986 | r600_blit_fini(rdev); |
978 | radeon_ring_fini(rdev); | 987 | radeon_ring_fini(rdev); |
979 | rv770_pcie_gart_disable(rdev); | 988 | rv770_pcie_gart_fini(rdev); |
980 | radeon_gart_table_vram_free(rdev); | ||
981 | radeon_gart_fini(rdev); | ||
982 | radeon_gem_fini(rdev); | 989 | radeon_gem_fini(rdev); |
983 | radeon_fence_driver_fini(rdev); | 990 | radeon_fence_driver_fini(rdev); |
984 | radeon_clocks_fini(rdev); | 991 | radeon_clocks_fini(rdev); |