aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/rv770.c
diff options
context:
space:
mode:
authorAlex Deucher <alexander.deucher@amd.com>2011-10-04 10:46:34 -0400
committerDave Airlie <airlied@redhat.com>2011-10-04 12:24:14 -0400
commit12d5180bd7e683a4ae80830b82ba67e7b7fac7b2 (patch)
treeea3c0e5d3691a4f01474f27cdf297cf5a5e84873 /drivers/gpu/drm/radeon/rv770.c
parent02e6859eae4a8e511fa1a2c9a689ea25cdc6166a (diff)
drm/radeon/kms: fix channel_remap setup (v2)
Most asics just use the hw default value which requires no explicit programming. For those that need a different value, the vbios will program it properly. As such, there's no need to program these registers explicitly in the driver. Changing MC_SHARED_CHREMAP requires a reload of all data in vram otherwise its contents will be scambled. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=40103 v2: drop now unused channel_remap functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv770.c')
-rw-r--r--drivers/gpu/drm/radeon/rv770.c51
1 files changed, 0 insertions, 51 deletions
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 4720d000d440..b13c2eedc321 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
536 return backend_map; 536 return backend_map;
537} 537}
538 538
539static void rv770_program_channel_remap(struct radeon_device *rdev)
540{
541 u32 tcp_chan_steer, mc_shared_chremap, tmp;
542 bool force_no_swizzle;
543
544 switch (rdev->family) {
545 case CHIP_RV770:
546 case CHIP_RV730:
547 force_no_swizzle = false;
548 break;
549 case CHIP_RV710:
550 case CHIP_RV740:
551 default:
552 force_no_swizzle = true;
553 break;
554 }
555
556 tmp = RREG32(MC_SHARED_CHMAP);
557 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
558 case 0:
559 case 1:
560 default:
561 /* default mapping */
562 mc_shared_chremap = 0x00fac688;
563 break;
564 case 2:
565 case 3:
566 if (force_no_swizzle)
567 mc_shared_chremap = 0x00fac688;
568 else
569 mc_shared_chremap = 0x00bbc298;
570 break;
571 }
572
573 if (rdev->family == CHIP_RV740)
574 tcp_chan_steer = 0x00ef2a60;
575 else
576 tcp_chan_steer = 0x00fac688;
577
578 /* RV770 CE has special chremap setup */
579 if (rdev->pdev->device == 0x944e) {
580 tcp_chan_steer = 0x00b08b08;
581 mc_shared_chremap = 0x00b08b08;
582 }
583
584 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
585 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
586}
587
588static void rv770_gpu_init(struct radeon_device *rdev) 539static void rv770_gpu_init(struct radeon_device *rdev)
589{ 540{
590 int i, j, num_qd_pipes; 541 int i, j, num_qd_pipes;
@@ -785,8 +736,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
785 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 736 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
786 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 737 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
787 738
788 rv770_program_channel_remap(rdev);
789
790 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 739 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
791 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 740 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
792 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 741 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);