drm/radeon/kms: Fix R600/RV770 startup path & reset

We were calling reset unconditionaly in the startup path
this is bad we need to call GPU reset for a good reason
as after reset the GPU is in unknown states. To avoid any
more bad things to happen we now also unconditionaly
reinitialize the GPU after reset. This patch fix few issues
reported by different people regarding KMS & R6XX/RV7XX hw.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 8 insertions, 64 deletions

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index af20a8d48dca..a06e7497d49e 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -129,14 +129,9 @@ void rv770_pcie_gart_fini(struct radeon_device *rdev)
 /*
  * MC
  */
-static void rv770_mc_resume(struct radeon_device *rdev)
+static void rv770_mc_program(struct radeon_device *rdev)
 {
-        u32 d1vga_control, d2vga_control;
-        u32 vga_render_control, vga_hdp_control;
-        u32 d1crtc_control, d2crtc_control;
-        u32 new_d1grph_primary, new_d1grph_secondary;
-        u32 new_d2grph_primary, new_d2grph_secondary;
-        u64 old_vram_start;
+        struct rv515_mc_save save;
         u32 tmp;
         int i, j;
 
@@ -150,41 +145,12 @@ static void rv770_mc_resume(struct radeon_device *rdev)
         }
         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 
-        d1vga_control = RREG32(D1VGA_CONTROL);
-        d2vga_control = RREG32(D2VGA_CONTROL);
-        vga_render_control = RREG32(VGA_RENDER_CONTROL);
-        vga_hdp_control = RREG32(VGA_HDP_CONTROL);
-        d1crtc_control = RREG32(D1CRTC_CONTROL);
-        d2crtc_control = RREG32(D2CRTC_CONTROL);
-        old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
-        new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
-        new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
-        new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
-        new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
-        new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
-        new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
-        new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
-        new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
-
-        /* Stop all video */
-        WREG32(D1VGA_CONTROL, 0);
-        WREG32(D2VGA_CONTROL, 0);
-        WREG32(VGA_RENDER_CONTROL, 0);
-        WREG32(D1CRTC_UPDATE_LOCK, 1);
-        WREG32(D2CRTC_UPDATE_LOCK, 1);
-        WREG32(D1CRTC_CONTROL, 0);
-        WREG32(D2CRTC_CONTROL, 0);
-        WREG32(D1CRTC_UPDATE_LOCK, 0);
-        WREG32(D2CRTC_UPDATE_LOCK, 0);
-
-        mdelay(1);
+        rv515_mc_stop(rdev, &save);
         if (r600_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "[drm] MC not idle !\n");
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
         }
-
         /* Lockout access through VGA aperture*/
         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
-
         /* Update configuration */
         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
@@ -204,31 +170,10 @@ static void rv770_mc_resume(struct radeon_device *rdev)
                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
         }
-        WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
-        WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
-        WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
-        WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
-        WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
-
-        /* Unlock host access */
-        WREG32(VGA_HDP_CONTROL, vga_hdp_control);
-
-        mdelay(1);
         if (r600_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "[drm] MC not idle !\n");
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
         }
-
-        /* Restore video state */
-        WREG32(D1CRTC_UPDATE_LOCK, 1);
-        WREG32(D2CRTC_UPDATE_LOCK, 1);
-        WREG32(D1CRTC_CONTROL, d1crtc_control);
-        WREG32(D2CRTC_CONTROL, d2crtc_control);
-        WREG32(D1CRTC_UPDATE_LOCK, 0);
-        WREG32(D2CRTC_UPDATE_LOCK, 0);
-        WREG32(D1VGA_CONTROL, d1vga_control);
-        WREG32(D2VGA_CONTROL, d2vga_control);
-        WREG32(VGA_RENDER_CONTROL, vga_render_control);
-
+        rv515_mc_resume(rdev, &save);
         /* we need to own VRAM, so turn off the VGA renderer here
          * to stop it overwriting our objects */
         rv515_vga_render_disable(rdev);
@@ -861,8 +806,7 @@ static int rv770_startup(struct radeon_device *rdev)
 {
         int r;
 
-        radeon_gpu_reset(rdev);
-        rv770_mc_resume(rdev);
+        rv770_mc_program(rdev);
         r = rv770_pcie_gart_enable(rdev);
         if (r)
                 return r;
@@ -893,7 +837,7 @@ int rv770_resume(struct radeon_device *rdev)
 {
         int r;
 
-        if (radeon_gpu_reset(rdev)) {
+        if (rv770_gpu_reset(rdev)) {
                 /* FIXME: what do we want to do here ? */
         }
         /* post card */