diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-09-27 15:08:35 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2012-12-10 16:53:23 -0500 |
commit | 4d75658bffea78f0c6f82fd46df1ec983ccacdf0 (patch) | |
tree | a6c111fe8fb7ebb76af46924ec0bc5c8f7cc961b /drivers/gpu/drm/radeon/rv770.c | |
parent | 71bfe916ebe6d026cd3d0e41c398574fc1228e03 (diff) |
drm/radeon/kms: Add initial support for async DMA on r6xx/r7xx
Uses the new multi-ring infrastucture. 6xx/7xx has a single
async DMA ring.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv770.c')
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 31 |
1 files changed, 29 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 79814a08c8e5..87c979c4f721 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -316,6 +316,7 @@ void r700_cp_stop(struct radeon_device *rdev) | |||
316 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | 316 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
317 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); | 317 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
318 | WREG32(SCRATCH_UMSK, 0); | 318 | WREG32(SCRATCH_UMSK, 0); |
319 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; | ||
319 | } | 320 | } |
320 | 321 | ||
321 | static int rv770_cp_load_microcode(struct radeon_device *rdev) | 322 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
@@ -583,6 +584,8 @@ static void rv770_gpu_init(struct radeon_device *rdev) | |||
583 | WREG32(GB_TILING_CONFIG, gb_tiling_config); | 584 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
584 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | 585 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
585 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | 586 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
587 | WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); | ||
588 | WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); | ||
586 | 589 | ||
587 | WREG32(CGTS_SYS_TCC_DISABLE, 0); | 590 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
588 | WREG32(CGTS_TCC_DISABLE, 0); | 591 | WREG32(CGTS_TCC_DISABLE, 0); |
@@ -886,7 +889,7 @@ static int rv770_mc_init(struct radeon_device *rdev) | |||
886 | 889 | ||
887 | static int rv770_startup(struct radeon_device *rdev) | 890 | static int rv770_startup(struct radeon_device *rdev) |
888 | { | 891 | { |
889 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | 892 | struct radeon_ring *ring; |
890 | int r; | 893 | int r; |
891 | 894 | ||
892 | /* enable pcie gen2 link */ | 895 | /* enable pcie gen2 link */ |
@@ -932,6 +935,12 @@ static int rv770_startup(struct radeon_device *rdev) | |||
932 | return r; | 935 | return r; |
933 | } | 936 | } |
934 | 937 | ||
938 | r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); | ||
939 | if (r) { | ||
940 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); | ||
941 | return r; | ||
942 | } | ||
943 | |||
935 | /* Enable IRQ */ | 944 | /* Enable IRQ */ |
936 | r = r600_irq_init(rdev); | 945 | r = r600_irq_init(rdev); |
937 | if (r) { | 946 | if (r) { |
@@ -941,11 +950,20 @@ static int rv770_startup(struct radeon_device *rdev) | |||
941 | } | 950 | } |
942 | r600_irq_set(rdev); | 951 | r600_irq_set(rdev); |
943 | 952 | ||
953 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | ||
944 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, | 954 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
945 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, | 955 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
946 | 0, 0xfffff, RADEON_CP_PACKET2); | 956 | 0, 0xfffff, RADEON_CP_PACKET2); |
947 | if (r) | 957 | if (r) |
948 | return r; | 958 | return r; |
959 | |||
960 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; | ||
961 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, | ||
962 | DMA_RB_RPTR, DMA_RB_WPTR, | ||
963 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); | ||
964 | if (r) | ||
965 | return r; | ||
966 | |||
949 | r = rv770_cp_load_microcode(rdev); | 967 | r = rv770_cp_load_microcode(rdev); |
950 | if (r) | 968 | if (r) |
951 | return r; | 969 | return r; |
@@ -953,6 +971,10 @@ static int rv770_startup(struct radeon_device *rdev) | |||
953 | if (r) | 971 | if (r) |
954 | return r; | 972 | return r; |
955 | 973 | ||
974 | r = r600_dma_resume(rdev); | ||
975 | if (r) | ||
976 | return r; | ||
977 | |||
956 | r = radeon_ib_pool_init(rdev); | 978 | r = radeon_ib_pool_init(rdev); |
957 | if (r) { | 979 | if (r) { |
958 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | 980 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
@@ -995,7 +1017,7 @@ int rv770_suspend(struct radeon_device *rdev) | |||
995 | { | 1017 | { |
996 | r600_audio_fini(rdev); | 1018 | r600_audio_fini(rdev); |
997 | r700_cp_stop(rdev); | 1019 | r700_cp_stop(rdev); |
998 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; | 1020 | r600_dma_stop(rdev); |
999 | r600_irq_suspend(rdev); | 1021 | r600_irq_suspend(rdev); |
1000 | radeon_wb_disable(rdev); | 1022 | radeon_wb_disable(rdev); |
1001 | rv770_pcie_gart_disable(rdev); | 1023 | rv770_pcie_gart_disable(rdev); |
@@ -1066,6 +1088,9 @@ int rv770_init(struct radeon_device *rdev) | |||
1066 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; | 1088 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
1067 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); | 1089 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
1068 | 1090 | ||
1091 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; | ||
1092 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); | ||
1093 | |||
1069 | rdev->ih.ring_obj = NULL; | 1094 | rdev->ih.ring_obj = NULL; |
1070 | r600_ih_ring_init(rdev, 64 * 1024); | 1095 | r600_ih_ring_init(rdev, 64 * 1024); |
1071 | 1096 | ||
@@ -1078,6 +1103,7 @@ int rv770_init(struct radeon_device *rdev) | |||
1078 | if (r) { | 1103 | if (r) { |
1079 | dev_err(rdev->dev, "disabling GPU acceleration\n"); | 1104 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
1080 | r700_cp_fini(rdev); | 1105 | r700_cp_fini(rdev); |
1106 | r600_dma_fini(rdev); | ||
1081 | r600_irq_fini(rdev); | 1107 | r600_irq_fini(rdev); |
1082 | radeon_wb_fini(rdev); | 1108 | radeon_wb_fini(rdev); |
1083 | radeon_ib_pool_fini(rdev); | 1109 | radeon_ib_pool_fini(rdev); |
@@ -1093,6 +1119,7 @@ void rv770_fini(struct radeon_device *rdev) | |||
1093 | { | 1119 | { |
1094 | r600_blit_fini(rdev); | 1120 | r600_blit_fini(rdev); |
1095 | r700_cp_fini(rdev); | 1121 | r700_cp_fini(rdev); |
1122 | r600_dma_fini(rdev); | ||
1096 | r600_irq_fini(rdev); | 1123 | r600_irq_fini(rdev); |
1097 | radeon_wb_fini(rdev); | 1124 | radeon_wb_fini(rdev); |
1098 | radeon_ib_pool_fini(rdev); | 1125 | radeon_ib_pool_fini(rdev); |