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authorDave Airlie <airlied@redhat.com>2012-06-27 03:35:54 -0400
committerDave Airlie <airlied@redhat.com>2012-07-19 22:30:32 -0400
commit197bbb3d464f33eac1b458e83c1929d2f268d4c9 (patch)
treefdbbe5d8515307772fbce4ef30ff1d55300d8275 /drivers/gpu/drm/radeon/rv770.c
parentf42977841f4a28b82820384fdb9b9581b410dbb1 (diff)
drm/radeon/kms: auto detect pcie link speed from root port
This check the root ports supported link speeds and enables GEN2 mode if the 5.0 GT link speed is available. The first 3.0 cards are SI so they will probably need more investigation. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv770.c')
-rw-r--r--drivers/gpu/drm/radeon/rv770.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index eb4704e72bdb..ca8ffec10ff6 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -1112,6 +1112,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1112{ 1112{
1113 u32 link_width_cntl, lanes, speed_cntl, tmp; 1113 u32 link_width_cntl, lanes, speed_cntl, tmp;
1114 u16 link_cntl2; 1114 u16 link_cntl2;
1115 u32 mask;
1116 int ret;
1115 1117
1116 if (radeon_pcie_gen2 == 0) 1118 if (radeon_pcie_gen2 == 0)
1117 return; 1119 return;
@@ -1126,6 +1128,15 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1126 if (ASIC_IS_X2(rdev)) 1128 if (ASIC_IS_X2(rdev))
1127 return; 1129 return;
1128 1130
1131 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
1132 if (ret != 0)
1133 return;
1134
1135 if (!(mask & DRM_PCIE_SPEED_50))
1136 return;
1137
1138 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
1139
1129 /* advertise upconfig capability */ 1140 /* advertise upconfig capability */
1130 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 1141 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1131 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 1142 link_width_cntl &= ~LC_UPCONFIGURE_DIS;