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authorJerome Glisse <jglisse@redhat.com>2009-09-07 20:10:24 -0400
committerDave Airlie <airlied@redhat.com>2009-09-07 21:15:52 -0400
commit3ce0a23d2d253185df24e22e3d5f89800bb3dd1c (patch)
tree4b4defdbe33aec7317101cce0f89c33083f8d17b /drivers/gpu/drm/radeon/rv770.c
parent4ce001abafafe77e5dd943d1480fc9f87894e96f (diff)
drm/radeon/kms: add r600 KMS support
This adds the r600 KMS + CS support to the Linux kernel. The r600 TTM support is quite basic and still needs more work esp around using interrupts, but the polled fencing should work okay for now. Also currently TTM is using memcpy to do VRAM moves, the code is here to use a 3D blit to do this, but isn't fully debugged yet. Authors: Alex Deucher <alexdeucher@gmail.com> Dave Airlie <airlied@redhat.com> Jerome Glisse <jglisse@redhat.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv770.c')
-rw-r--r--drivers/gpu/drm/radeon/rv770.c987
1 files changed, 931 insertions, 56 deletions
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 21d8ffd57308..57765f6d5b20 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -25,100 +25,975 @@
25 * Alex Deucher 25 * Alex Deucher
26 * Jerome Glisse 26 * Jerome Glisse
27 */ 27 */
28#include <linux/firmware.h>
29#include <linux/platform_device.h>
28#include "drmP.h" 30#include "drmP.h"
29#include "radeon_reg.h"
30#include "radeon.h" 31#include "radeon.h"
32#include "radeon_share.h"
33#include "rv770d.h"
34#include "avivod.h"
35#include "atom.h"
31 36
32/* rv770,rv730,rv710 depends on : */ 37#define R700_PFP_UCODE_SIZE 848
33void rs600_mc_disable_clients(struct radeon_device *rdev); 38#define R700_PM4_UCODE_SIZE 1360
34 39
35/* This files gather functions specifics to: 40static void rv770_gpu_init(struct radeon_device *rdev);
36 * rv770,rv730,rv710 41void rv770_fini(struct radeon_device *rdev);
37 *
38 * Some of these functions might be used by newer ASICs.
39 */
40int rv770_mc_wait_for_idle(struct radeon_device *rdev);
41void rv770_gpu_init(struct radeon_device *rdev);
42 42
43 43
44/* 44/*
45 * MC 45 * GART
46 */ 46 */
47int rv770_mc_init(struct radeon_device *rdev) 47int rv770_pcie_gart_enable(struct radeon_device *rdev)
48{ 48{
49 uint32_t tmp; 49 u32 tmp;
50 int r, i;
50 51
51 rv770_gpu_init(rdev); 52 /* Initialize common gart structure */
53 r = radeon_gart_init(rdev);
54 if (r) {
55 return r;
56 }
57 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
58 r = radeon_gart_table_vram_alloc(rdev);
59 if (r) {
60 return r;
61 }
62 for (i = 0; i < rdev->gart.num_gpu_pages; i++)
63 r600_gart_clear_page(rdev, i);
64 /* Setup L2 cache */
65 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
66 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
67 EFFECTIVE_L2_QUEUE_SIZE(7));
68 WREG32(VM_L2_CNTL2, 0);
69 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
70 /* Setup TLB control */
71 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
72 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
73 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
74 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
75 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
76 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
77 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
78 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
79 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
80 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
81 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
82 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
83 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
84 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
85 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
86 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
87 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
88 (u32)(rdev->dummy_page.addr >> 12));
89 for (i = 1; i < 7; i++)
90 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
52 91
53 /* setup the gart before changing location so we can ask to 92 r600_pcie_gart_tlb_flush(rdev);
54 * discard unmapped mc request 93 rdev->gart.ready = true;
55 */
56 /* FIXME: disable out of gart access */
57 tmp = rdev->mc.gtt_location / 4096;
58 tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp);
59 WREG32(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp);
60 tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096;
61 tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp);
62 WREG32(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp);
63
64 rs600_mc_disable_clients(rdev);
65 if (rv770_mc_wait_for_idle(rdev)) {
66 printk(KERN_WARNING "Failed to wait MC idle while "
67 "programming pipes. Bad things might happen.\n");
68 }
69
70 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
71 tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24);
72 tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24);
73 WREG32(R700_MC_VM_FB_LOCATION, tmp);
74 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
75 tmp = REG_SET(R700_MC_AGP_TOP, tmp >> 22);
76 WREG32(R700_MC_VM_AGP_TOP, tmp);
77 tmp = REG_SET(R700_MC_AGP_BOT, rdev->mc.gtt_location >> 22);
78 WREG32(R700_MC_VM_AGP_BOT, tmp);
79 return 0; 94 return 0;
80} 95}
81 96
82void rv770_mc_fini(struct radeon_device *rdev) 97void rv770_pcie_gart_disable(struct radeon_device *rdev)
83{ 98{
84 /* FIXME: implement */ 99 u32 tmp;
100 int i;
101
102 /* Clear ptes*/
103 for (i = 0; i < rdev->gart.num_gpu_pages; i++)
104 r600_gart_clear_page(rdev, i);
105 r600_pcie_gart_tlb_flush(rdev);
106 /* Disable all tables */
107 for (i = 0; i < 7; i++)
108 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
109
110 /* Setup L2 cache */
111 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
112 EFFECTIVE_L2_QUEUE_SIZE(7));
113 WREG32(VM_L2_CNTL2, 0);
114 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
115 /* Setup TLB control */
116 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
117 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
118 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
119 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
120 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
121 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
122 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
123 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
85} 124}
86 125
87 126
88/* 127/*
89 * Global GPU functions 128 * MC
90 */ 129 */
91void rv770_errata(struct radeon_device *rdev) 130static void rv770_mc_resume(struct radeon_device *rdev)
92{ 131{
93 rdev->pll_errata = 0; 132 u32 d1vga_control, d2vga_control;
133 u32 vga_render_control, vga_hdp_control;
134 u32 d1crtc_control, d2crtc_control;
135 u32 new_d1grph_primary, new_d1grph_secondary;
136 u32 new_d2grph_primary, new_d2grph_secondary;
137 u64 old_vram_start;
138 u32 tmp;
139 int i, j;
140
141 /* Initialize HDP */
142 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
143 WREG32((0x2c14 + j), 0x00000000);
144 WREG32((0x2c18 + j), 0x00000000);
145 WREG32((0x2c1c + j), 0x00000000);
146 WREG32((0x2c20 + j), 0x00000000);
147 WREG32((0x2c24 + j), 0x00000000);
148 }
149 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
150
151 d1vga_control = RREG32(D1VGA_CONTROL);
152 d2vga_control = RREG32(D2VGA_CONTROL);
153 vga_render_control = RREG32(VGA_RENDER_CONTROL);
154 vga_hdp_control = RREG32(VGA_HDP_CONTROL);
155 d1crtc_control = RREG32(D1CRTC_CONTROL);
156 d2crtc_control = RREG32(D2CRTC_CONTROL);
157 old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
158 new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
159 new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
160 new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
161 new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
162 new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
163 new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
164 new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
165 new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
166
167 /* Stop all video */
168 WREG32(D1VGA_CONTROL, 0);
169 WREG32(D2VGA_CONTROL, 0);
170 WREG32(VGA_RENDER_CONTROL, 0);
171 WREG32(D1CRTC_UPDATE_LOCK, 1);
172 WREG32(D2CRTC_UPDATE_LOCK, 1);
173 WREG32(D1CRTC_CONTROL, 0);
174 WREG32(D2CRTC_CONTROL, 0);
175 WREG32(D1CRTC_UPDATE_LOCK, 0);
176 WREG32(D2CRTC_UPDATE_LOCK, 0);
177
178 mdelay(1);
179 if (r600_mc_wait_for_idle(rdev)) {
180 printk(KERN_WARNING "[drm] MC not idle !\n");
181 }
182
183 /* Lockout access through VGA aperture*/
184 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
185
186 /* Update configuration */
187 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
188 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
189 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
190 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
191 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
192 WREG32(MC_VM_FB_LOCATION, tmp);
193 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
194 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
195 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
196 if (rdev->flags & RADEON_IS_AGP) {
197 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
198 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
199 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
200 } else {
201 WREG32(MC_VM_AGP_BASE, 0);
202 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
203 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
204 }
205 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
206 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
207 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
208 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
209 WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
210
211 /* Unlock host access */
212 WREG32(VGA_HDP_CONTROL, vga_hdp_control);
213
214 mdelay(1);
215 if (r600_mc_wait_for_idle(rdev)) {
216 printk(KERN_WARNING "[drm] MC not idle !\n");
217 }
218
219 /* Restore video state */
220 WREG32(D1CRTC_UPDATE_LOCK, 1);
221 WREG32(D2CRTC_UPDATE_LOCK, 1);
222 WREG32(D1CRTC_CONTROL, d1crtc_control);
223 WREG32(D2CRTC_CONTROL, d2crtc_control);
224 WREG32(D1CRTC_UPDATE_LOCK, 0);
225 WREG32(D2CRTC_UPDATE_LOCK, 0);
226 WREG32(D1VGA_CONTROL, d1vga_control);
227 WREG32(D2VGA_CONTROL, d2vga_control);
228 WREG32(VGA_RENDER_CONTROL, vga_render_control);
94} 229}
95 230
96int rv770_mc_wait_for_idle(struct radeon_device *rdev) 231
232/*
233 * CP.
234 */
235void r700_cp_stop(struct radeon_device *rdev)
97{ 236{
98 /* FIXME: implement */ 237 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
99 return 0;
100} 238}
101 239
102void rv770_gpu_init(struct radeon_device *rdev) 240
241static int rv770_cp_load_microcode(struct radeon_device *rdev)
103{ 242{
104 /* FIXME: implement */ 243 const __be32 *fw_data;
244 int i;
245
246 if (!rdev->me_fw || !rdev->pfp_fw)
247 return -EINVAL;
248
249 r700_cp_stop(rdev);
250 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
251
252 /* Reset cp */
253 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
254 RREG32(GRBM_SOFT_RESET);
255 mdelay(15);
256 WREG32(GRBM_SOFT_RESET, 0);
257
258 fw_data = (const __be32 *)rdev->pfp_fw->data;
259 WREG32(CP_PFP_UCODE_ADDR, 0);
260 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
261 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
262 WREG32(CP_PFP_UCODE_ADDR, 0);
263
264 fw_data = (const __be32 *)rdev->me_fw->data;
265 WREG32(CP_ME_RAM_WADDR, 0);
266 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
267 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
268
269 WREG32(CP_PFP_UCODE_ADDR, 0);
270 WREG32(CP_ME_RAM_WADDR, 0);
271 WREG32(CP_ME_RAM_RADDR, 0);
272 return 0;
105} 273}
106 274
107 275
108/* 276/*
109 * VRAM info 277 * Core functions
110 */ 278 */
111void rv770_vram_get_type(struct radeon_device *rdev) 279static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
280 u32 num_backends,
281 u32 backend_disable_mask)
112{ 282{
113 /* FIXME: implement */ 283 u32 backend_map = 0;
284 u32 enabled_backends_mask;
285 u32 enabled_backends_count;
286 u32 cur_pipe;
287 u32 swizzle_pipe[R7XX_MAX_PIPES];
288 u32 cur_backend;
289 u32 i;
290
291 if (num_tile_pipes > R7XX_MAX_PIPES)
292 num_tile_pipes = R7XX_MAX_PIPES;
293 if (num_tile_pipes < 1)
294 num_tile_pipes = 1;
295 if (num_backends > R7XX_MAX_BACKENDS)
296 num_backends = R7XX_MAX_BACKENDS;
297 if (num_backends < 1)
298 num_backends = 1;
299
300 enabled_backends_mask = 0;
301 enabled_backends_count = 0;
302 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
303 if (((backend_disable_mask >> i) & 1) == 0) {
304 enabled_backends_mask |= (1 << i);
305 ++enabled_backends_count;
306 }
307 if (enabled_backends_count == num_backends)
308 break;
309 }
310
311 if (enabled_backends_count == 0) {
312 enabled_backends_mask = 1;
313 enabled_backends_count = 1;
314 }
315
316 if (enabled_backends_count != num_backends)
317 num_backends = enabled_backends_count;
318
319 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
320 switch (num_tile_pipes) {
321 case 1:
322 swizzle_pipe[0] = 0;
323 break;
324 case 2:
325 swizzle_pipe[0] = 0;
326 swizzle_pipe[1] = 1;
327 break;
328 case 3:
329 swizzle_pipe[0] = 0;
330 swizzle_pipe[1] = 2;
331 swizzle_pipe[2] = 1;
332 break;
333 case 4:
334 swizzle_pipe[0] = 0;
335 swizzle_pipe[1] = 2;
336 swizzle_pipe[2] = 3;
337 swizzle_pipe[3] = 1;
338 break;
339 case 5:
340 swizzle_pipe[0] = 0;
341 swizzle_pipe[1] = 2;
342 swizzle_pipe[2] = 4;
343 swizzle_pipe[3] = 1;
344 swizzle_pipe[4] = 3;
345 break;
346 case 6:
347 swizzle_pipe[0] = 0;
348 swizzle_pipe[1] = 2;
349 swizzle_pipe[2] = 4;
350 swizzle_pipe[3] = 5;
351 swizzle_pipe[4] = 3;
352 swizzle_pipe[5] = 1;
353 break;
354 case 7:
355 swizzle_pipe[0] = 0;
356 swizzle_pipe[1] = 2;
357 swizzle_pipe[2] = 4;
358 swizzle_pipe[3] = 6;
359 swizzle_pipe[4] = 3;
360 swizzle_pipe[5] = 1;
361 swizzle_pipe[6] = 5;
362 break;
363 case 8:
364 swizzle_pipe[0] = 0;
365 swizzle_pipe[1] = 2;
366 swizzle_pipe[2] = 4;
367 swizzle_pipe[3] = 6;
368 swizzle_pipe[4] = 3;
369 swizzle_pipe[5] = 1;
370 swizzle_pipe[6] = 7;
371 swizzle_pipe[7] = 5;
372 break;
373 }
374
375 cur_backend = 0;
376 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
377 while (((1 << cur_backend) & enabled_backends_mask) == 0)
378 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
379
380 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
381
382 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
383 }
384
385 return backend_map;
114} 386}
115 387
116void rv770_vram_info(struct radeon_device *rdev) 388static void rv770_gpu_init(struct radeon_device *rdev)
117{ 389{
118 rv770_vram_get_type(rdev); 390 int i, j, num_qd_pipes;
391 u32 sx_debug_1;
392 u32 smx_dc_ctl0;
393 u32 num_gs_verts_per_thread;
394 u32 vgt_gs_per_es;
395 u32 gs_prim_buffer_depth = 0;
396 u32 sq_ms_fifo_sizes;
397 u32 sq_config;
398 u32 sq_thread_resource_mgmt;
399 u32 hdp_host_path_cntl;
400 u32 sq_dyn_gpr_size_simd_ab_0;
401 u32 backend_map;
402 u32 gb_tiling_config = 0;
403 u32 cc_rb_backend_disable = 0;
404 u32 cc_gc_shader_pipe_config = 0;
405 u32 mc_arb_ramcfg;
406 u32 db_debug4;
119 407
120 /* FIXME: implement */ 408 /* setup chip specs */
409 switch (rdev->family) {
410 case CHIP_RV770:
411 rdev->config.rv770.max_pipes = 4;
412 rdev->config.rv770.max_tile_pipes = 8;
413 rdev->config.rv770.max_simds = 10;
414 rdev->config.rv770.max_backends = 4;
415 rdev->config.rv770.max_gprs = 256;
416 rdev->config.rv770.max_threads = 248;
417 rdev->config.rv770.max_stack_entries = 512;
418 rdev->config.rv770.max_hw_contexts = 8;
419 rdev->config.rv770.max_gs_threads = 16 * 2;
420 rdev->config.rv770.sx_max_export_size = 128;
421 rdev->config.rv770.sx_max_export_pos_size = 16;
422 rdev->config.rv770.sx_max_export_smx_size = 112;
423 rdev->config.rv770.sq_num_cf_insts = 2;
424
425 rdev->config.rv770.sx_num_of_sets = 7;
426 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
427 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
428 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
429 break;
430 case CHIP_RV730:
431 rdev->config.rv770.max_pipes = 2;
432 rdev->config.rv770.max_tile_pipes = 4;
433 rdev->config.rv770.max_simds = 8;
434 rdev->config.rv770.max_backends = 2;
435 rdev->config.rv770.max_gprs = 128;
436 rdev->config.rv770.max_threads = 248;
437 rdev->config.rv770.max_stack_entries = 256;
438 rdev->config.rv770.max_hw_contexts = 8;
439 rdev->config.rv770.max_gs_threads = 16 * 2;
440 rdev->config.rv770.sx_max_export_size = 256;
441 rdev->config.rv770.sx_max_export_pos_size = 32;
442 rdev->config.rv770.sx_max_export_smx_size = 224;
443 rdev->config.rv770.sq_num_cf_insts = 2;
444
445 rdev->config.rv770.sx_num_of_sets = 7;
446 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
447 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
448 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
449 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
450 rdev->config.rv770.sx_max_export_pos_size -= 16;
451 rdev->config.rv770.sx_max_export_smx_size += 16;
452 }
453 break;
454 case CHIP_RV710:
455 rdev->config.rv770.max_pipes = 2;
456 rdev->config.rv770.max_tile_pipes = 2;
457 rdev->config.rv770.max_simds = 2;
458 rdev->config.rv770.max_backends = 1;
459 rdev->config.rv770.max_gprs = 256;
460 rdev->config.rv770.max_threads = 192;
461 rdev->config.rv770.max_stack_entries = 256;
462 rdev->config.rv770.max_hw_contexts = 4;
463 rdev->config.rv770.max_gs_threads = 8 * 2;
464 rdev->config.rv770.sx_max_export_size = 128;
465 rdev->config.rv770.sx_max_export_pos_size = 16;
466 rdev->config.rv770.sx_max_export_smx_size = 112;
467 rdev->config.rv770.sq_num_cf_insts = 1;
468
469 rdev->config.rv770.sx_num_of_sets = 7;
470 rdev->config.rv770.sc_prim_fifo_size = 0x40;
471 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
472 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
473 break;
474 case CHIP_RV740:
475 rdev->config.rv770.max_pipes = 4;
476 rdev->config.rv770.max_tile_pipes = 4;
477 rdev->config.rv770.max_simds = 8;
478 rdev->config.rv770.max_backends = 4;
479 rdev->config.rv770.max_gprs = 256;
480 rdev->config.rv770.max_threads = 248;
481 rdev->config.rv770.max_stack_entries = 512;
482 rdev->config.rv770.max_hw_contexts = 8;
483 rdev->config.rv770.max_gs_threads = 16 * 2;
484 rdev->config.rv770.sx_max_export_size = 256;
485 rdev->config.rv770.sx_max_export_pos_size = 32;
486 rdev->config.rv770.sx_max_export_smx_size = 224;
487 rdev->config.rv770.sq_num_cf_insts = 2;
488
489 rdev->config.rv770.sx_num_of_sets = 7;
490 rdev->config.rv770.sc_prim_fifo_size = 0x100;
491 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
492 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
493
494 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
495 rdev->config.rv770.sx_max_export_pos_size -= 16;
496 rdev->config.rv770.sx_max_export_smx_size += 16;
497 }
498 break;
499 default:
500 break;
501 }
502
503 /* Initialize HDP */
504 j = 0;
505 for (i = 0; i < 32; i++) {
506 WREG32((0x2c14 + j), 0x00000000);
507 WREG32((0x2c18 + j), 0x00000000);
508 WREG32((0x2c1c + j), 0x00000000);
509 WREG32((0x2c20 + j), 0x00000000);
510 WREG32((0x2c24 + j), 0x00000000);
511 j += 0x18;
512 }
513
514 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
515
516 /* setup tiling, simd, pipe config */
517 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
518
519 switch (rdev->config.rv770.max_tile_pipes) {
520 case 1:
521 gb_tiling_config |= PIPE_TILING(0);
522 break;
523 case 2:
524 gb_tiling_config |= PIPE_TILING(1);
525 break;
526 case 4:
527 gb_tiling_config |= PIPE_TILING(2);
528 break;
529 case 8:
530 gb_tiling_config |= PIPE_TILING(3);
531 break;
532 default:
533 break;
534 }
535
536 if (rdev->family == CHIP_RV770)
537 gb_tiling_config |= BANK_TILING(1);
538 else
539 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
540
541 gb_tiling_config |= GROUP_SIZE(0);
542
543 if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
544 gb_tiling_config |= ROW_TILING(3);
545 gb_tiling_config |= SAMPLE_SPLIT(3);
546 } else {
547 gb_tiling_config |=
548 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
549 gb_tiling_config |=
550 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
551 }
552
553 gb_tiling_config |= BANK_SWAPS(1);
554
555 backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
556 rdev->config.rv770.max_backends,
557 (0xff << rdev->config.rv770.max_backends) & 0xff);
558 gb_tiling_config |= BACKEND_MAP(backend_map);
559
560 cc_gc_shader_pipe_config =
561 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
562 cc_gc_shader_pipe_config |=
563 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
564
565 cc_rb_backend_disable =
566 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
567
568 WREG32(GB_TILING_CONFIG, gb_tiling_config);
569 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
570 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
571
572 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
573 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
574 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
575
576 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
577 WREG32(CGTS_SYS_TCC_DISABLE, 0);
578 WREG32(CGTS_TCC_DISABLE, 0);
579 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
580 WREG32(CGTS_USER_TCC_DISABLE, 0);
581
582 num_qd_pipes =
583 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
584 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
585 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
586
587 /* set HW defaults for 3D engine */
588 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
589 ROQ_IB2_START(0x2b)));
590
591 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
592
593 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
594 SYNC_GRADIENT |
595 SYNC_WALKER |
596 SYNC_ALIGNER));
597
598 sx_debug_1 = RREG32(SX_DEBUG_1);
599 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
600 WREG32(SX_DEBUG_1, sx_debug_1);
601
602 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
603 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
604 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
605 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
606
607 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
608 GS_FLUSH_CTL(4) |
609 ACK_FLUSH_CTL(3) |
610 SYNC_FLUSH_CTL));
611
612 if (rdev->family == CHIP_RV770)
613 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
614 else {
615 db_debug4 = RREG32(DB_DEBUG4);
616 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
617 WREG32(DB_DEBUG4, db_debug4);
618 }
619
620 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
621 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
622 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
623
624 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
625 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
626 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
627
628 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
629
630 WREG32(VGT_NUM_INSTANCES, 1);
631
632 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
633
634 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
635
636 WREG32(CP_PERFMON_CNTL, 0);
637
638 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
639 DONE_FIFO_HIWATER(0xe0) |
640 ALU_UPDATE_FIFO_HIWATER(0x8));
641 switch (rdev->family) {
642 case CHIP_RV770:
643 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
644 break;
645 case CHIP_RV730:
646 case CHIP_RV710:
647 case CHIP_RV740:
648 default:
649 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
650 break;
651 }
652 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
653
654 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
655 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
656 */
657 sq_config = RREG32(SQ_CONFIG);
658 sq_config &= ~(PS_PRIO(3) |
659 VS_PRIO(3) |
660 GS_PRIO(3) |
661 ES_PRIO(3));
662 sq_config |= (DX9_CONSTS |
663 VC_ENABLE |
664 EXPORT_SRC_C |
665 PS_PRIO(0) |
666 VS_PRIO(1) |
667 GS_PRIO(2) |
668 ES_PRIO(3));
669 if (rdev->family == CHIP_RV710)
670 /* no vertex cache */
671 sq_config &= ~VC_ENABLE;
672
673 WREG32(SQ_CONFIG, sq_config);
674
675 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
676 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
677 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
678
679 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
680 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
681
682 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
683 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
684 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
685 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
686 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
687 else
688 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
689 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
690
691 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
692 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
693
694 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
695 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
696
697 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
698 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
699 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
700 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
701
702 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
703 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
704 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
705 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
706 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
707 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
708 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
709 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
710
711 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
712 FORCE_EOV_MAX_REZ_CNT(255)));
713
714 if (rdev->family == CHIP_RV710)
715 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
716 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
717 else
718 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
719 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
720
721 switch (rdev->family) {
722 case CHIP_RV770:
723 case CHIP_RV730:
724 case CHIP_RV740:
725 gs_prim_buffer_depth = 384;
726 break;
727 case CHIP_RV710:
728 gs_prim_buffer_depth = 128;
729 break;
730 default:
731 break;
732 }
733
734 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
735 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
736 /* Max value for this is 256 */
737 if (vgt_gs_per_es > 256)
738 vgt_gs_per_es = 256;
739
740 WREG32(VGT_ES_PER_GS, 128);
741 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
742 WREG32(VGT_GS_PER_VS, 2);
743
744 /* more default values. 2D/3D driver should adjust as needed */
745 WREG32(VGT_GS_VERTEX_REUSE, 16);
746 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
747 WREG32(VGT_STRMOUT_EN, 0);
748 WREG32(SX_MISC, 0);
749 WREG32(PA_SC_MODE_CNTL, 0);
750 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
751 WREG32(PA_SC_AA_CONFIG, 0);
752 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
753 WREG32(PA_SC_LINE_STIPPLE, 0);
754 WREG32(SPI_INPUT_Z, 0);
755 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
756 WREG32(CB_COLOR7_FRAG, 0);
757
758 /* clear render buffer base addresses */
759 WREG32(CB_COLOR0_BASE, 0);
760 WREG32(CB_COLOR1_BASE, 0);
761 WREG32(CB_COLOR2_BASE, 0);
762 WREG32(CB_COLOR3_BASE, 0);
763 WREG32(CB_COLOR4_BASE, 0);
764 WREG32(CB_COLOR5_BASE, 0);
765 WREG32(CB_COLOR6_BASE, 0);
766 WREG32(CB_COLOR7_BASE, 0);
767
768 WREG32(TCP_CNTL, 0);
769
770 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
771 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
772
773 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
774
775 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
776 NUM_CLIP_SEQ(3)));
777
778}
779
780int rv770_mc_init(struct radeon_device *rdev)
781{
782 fixed20_12 a;
783 u32 tmp;
784 int r;
785
786 /* Get VRAM informations */
787 /* FIXME: Don't know how to determine vram width, need to check
788 * vram_width usage
789 */
790 rdev->mc.vram_width = 128;
791 rdev->mc.vram_is_ddr = true;
121 /* Could aper size report 0 ? */ 792 /* Could aper size report 0 ? */
122 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 793 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
123 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 794 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
795 /* Setup GPU memory space */
796 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
797 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
798 if (rdev->flags & RADEON_IS_AGP) {
799 r = radeon_agp_init(rdev);
800 if (r)
801 return r;
802 /* gtt_size is setup by radeon_agp_init */
803 rdev->mc.gtt_location = rdev->mc.agp_base;
804 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
805 /* Try to put vram before or after AGP because we
806 * we want SYSTEM_APERTURE to cover both VRAM and
807 * AGP so that GPU can catch out of VRAM/AGP access
808 */
809 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
810 /* Enought place before */
811 rdev->mc.vram_location = rdev->mc.gtt_location -
812 rdev->mc.mc_vram_size;
813 } else if (tmp > rdev->mc.mc_vram_size) {
814 /* Enought place after */
815 rdev->mc.vram_location = rdev->mc.gtt_location +
816 rdev->mc.gtt_size;
817 } else {
818 /* Try to setup VRAM then AGP might not
819 * not work on some card
820 */
821 rdev->mc.vram_location = 0x00000000UL;
822 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
823 }
824 } else {
825 rdev->mc.vram_location = 0x00000000UL;
826 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
827 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
828 }
829 rdev->mc.vram_start = rdev->mc.vram_location;
830 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
831 rdev->mc.gtt_start = rdev->mc.gtt_location;
832 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
833 /* FIXME: we should enforce default clock in case GPU is not in
834 * default setup
835 */
836 a.full = rfixed_const(100);
837 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
838 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
839 return 0;
840}
841int rv770_gpu_reset(struct radeon_device *rdev)
842{
843 /* FIXME: implement */
844 return 0;
845}
846
847int rv770_resume(struct radeon_device *rdev)
848{
849 int r;
850
851 rv770_mc_resume(rdev);
852 r = rv770_pcie_gart_enable(rdev);
853 if (r)
854 return r;
855 rv770_gpu_init(rdev);
856 r = radeon_ring_init(rdev, rdev->cp.ring_size);
857 if (r)
858 return r;
859 r = rv770_cp_load_microcode(rdev);
860 if (r)
861 return r;
862 r = r600_cp_resume(rdev);
863 if (r)
864 return r;
865 r = r600_wb_init(rdev);
866 if (r)
867 return r;
868 return 0;
869}
870
871int rv770_suspend(struct radeon_device *rdev)
872{
873 /* FIXME: we should wait for ring to be empty */
874 r700_cp_stop(rdev);
875 return 0;
876}
877
878/* Plan is to move initialization in that function and use
879 * helper function so that radeon_device_init pretty much
880 * do nothing more than calling asic specific function. This
881 * should also allow to remove a bunch of callback function
882 * like vram_info.
883 */
884int rv770_init(struct radeon_device *rdev)
885{
886 int r;
887
888 rdev->new_init_path = true;
889 r = radeon_dummy_page_init(rdev);
890 if (r)
891 return r;
892 /* This don't do much */
893 r = radeon_gem_init(rdev);
894 if (r)
895 return r;
896 /* Read BIOS */
897 if (!radeon_get_bios(rdev)) {
898 if (ASIC_IS_AVIVO(rdev))
899 return -EINVAL;
900 }
901 /* Must be an ATOMBIOS */
902 if (!rdev->is_atom_bios)
903 return -EINVAL;
904 r = radeon_atombios_init(rdev);
905 if (r)
906 return r;
907 /* Post card if necessary */
908 if (!r600_card_posted(rdev) && rdev->bios) {
909 DRM_INFO("GPU not posted. posting now...\n");
910 atom_asic_init(rdev->mode_info.atom_context);
911 }
912 /* Initialize scratch registers */
913 r600_scratch_init(rdev);
914 /* Initialize surface registers */
915 radeon_surface_init(rdev);
916 r = radeon_clocks_init(rdev);
917 if (r)
918 return r;
919 /* Fence driver */
920 r = radeon_fence_driver_init(rdev);
921 if (r)
922 return r;
923 r = rv770_mc_init(rdev);
924 if (r) {
925 if (rdev->flags & RADEON_IS_AGP) {
926 /* Retry with disabling AGP */
927 rv770_fini(rdev);
928 rdev->flags &= ~RADEON_IS_AGP;
929 return rv770_init(rdev);
930 }
931 return r;
932 }
933 /* Memory manager */
934 r = radeon_object_init(rdev);
935 if (r)
936 return r;
937 rdev->cp.ring_obj = NULL;
938 r600_ring_init(rdev, 1024 * 1024);
939
940 if (!rdev->me_fw || !rdev->pfp_fw) {
941 r = r600_cp_init_microcode(rdev);
942 if (r) {
943 DRM_ERROR("Failed to load firmware!\n");
944 return r;
945 }
946 }
947
948 r = rv770_resume(rdev);
949 if (r) {
950 if (rdev->flags & RADEON_IS_AGP) {
951 /* Retry with disabling AGP */
952 rv770_fini(rdev);
953 rdev->flags &= ~RADEON_IS_AGP;
954 return rv770_init(rdev);
955 }
956 return r;
957 }
958 r = r600_blit_init(rdev);
959 if (r) {
960 DRM_ERROR("radeon: failled blitter (%d).\n", r);
961 return r;
962 }
963 r = radeon_ib_pool_init(rdev);
964 if (r) {
965 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
966 return r;
967 }
968 r = radeon_ib_test(rdev);
969 if (r) {
970 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
971 return r;
972 }
973 return 0;
974}
975
976void rv770_fini(struct radeon_device *rdev)
977{
978 r600_blit_fini(rdev);
979 radeon_ring_fini(rdev);
980 rv770_pcie_gart_disable(rdev);
981 radeon_gart_table_vram_free(rdev);
982 radeon_gart_fini(rdev);
983 radeon_gem_fini(rdev);
984 radeon_fence_driver_fini(rdev);
985 radeon_clocks_fini(rdev);
986#if __OS_HAS_AGP
987 if (rdev->flags & RADEON_IS_AGP)
988 radeon_agp_fini(rdev);
989#endif
990 radeon_object_fini(rdev);
991 if (rdev->is_atom_bios) {
992 radeon_atombios_fini(rdev);
993 } else {
994 radeon_combios_fini(rdev);
995 }
996 kfree(rdev->bios);
997 rdev->bios = NULL;
998 radeon_dummy_page_fini(rdev);
124} 999}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 18:12:47 -0500