diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2010-08-02 12:13:46 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-08-03 19:49:20 -0400 |
commit | e06b14ee91a2ddefc9a67443a6cd8ee0fa800115 (patch) | |
tree | 621e5dc5f78e538ff80a0448a803fb1f3ce93add /drivers/gpu/drm/radeon/rv515.c | |
parent | ba4420c224c2808f2661cf8428f43ceef7a73a4a (diff) |
drm/radeon/kms: handle the case of no active displays properly in the bandwidth code
Logic was:
if (mode0 && mode1)
else if (mode0)
else
Should be:
if (mode0 && mode1)
else if (mode0)
else if (mode1)
Otherwise we may end up calculating the priority regs with
unitialized values.
Fixes:
https://bugzilla.kernel.org/show_bug.cgi?id=16492
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Cc: stable@kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv515.c')
-rw-r--r-- | drivers/gpu/drm/radeon/rv515.c | 23 |
1 files changed, 9 insertions, 14 deletions
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index b951b8790175..4d6e86041a9f 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
@@ -927,7 +927,9 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |||
927 | struct drm_display_mode *mode1 = NULL; | 927 | struct drm_display_mode *mode1 = NULL; |
928 | struct rv515_watermark wm0; | 928 | struct rv515_watermark wm0; |
929 | struct rv515_watermark wm1; | 929 | struct rv515_watermark wm1; |
930 | u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; | 930 | u32 tmp; |
931 | u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF; | ||
932 | u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF; | ||
931 | fixed20_12 priority_mark02, priority_mark12, fill_rate; | 933 | fixed20_12 priority_mark02, priority_mark12, fill_rate; |
932 | fixed20_12 a, b; | 934 | fixed20_12 a, b; |
933 | 935 | ||
@@ -1001,10 +1003,6 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |||
1001 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | 1003 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1002 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | 1004 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1003 | } | 1005 | } |
1004 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | ||
1005 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | ||
1006 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | ||
1007 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | ||
1008 | } else if (mode0) { | 1006 | } else if (mode0) { |
1009 | if (dfixed_trunc(wm0.dbpp) > 64) | 1007 | if (dfixed_trunc(wm0.dbpp) > 64) |
1010 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); | 1008 | a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair); |
@@ -1034,11 +1032,7 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |||
1034 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); | 1032 | d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); |
1035 | if (rdev->disp_priority == 2) | 1033 | if (rdev->disp_priority == 2) |
1036 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | 1034 | d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1037 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | 1035 | } else if (mode1) { |
1038 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | ||
1039 | WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); | ||
1040 | WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | ||
1041 | } else { | ||
1042 | if (dfixed_trunc(wm1.dbpp) > 64) | 1036 | if (dfixed_trunc(wm1.dbpp) > 64) |
1043 | a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); | 1037 | a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair); |
1044 | else | 1038 | else |
@@ -1067,11 +1061,12 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev) | |||
1067 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); | 1061 | d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); |
1068 | if (rdev->disp_priority == 2) | 1062 | if (rdev->disp_priority == 2) |
1069 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; | 1063 | d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; |
1070 | WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); | ||
1071 | WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); | ||
1072 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | ||
1073 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | ||
1074 | } | 1064 | } |
1065 | |||
1066 | WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); | ||
1067 | WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); | ||
1068 | WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); | ||
1069 | WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); | ||
1075 | } | 1070 | } |
1076 | 1071 | ||
1077 | void rv515_bandwidth_update(struct radeon_device *rdev) | 1072 | void rv515_bandwidth_update(struct radeon_device *rdev) |