Merge branch 'drm-radeon-lockup' into drm-core-next

* drm-radeon-lockup:
  drm/radeon/kms: simplify & improve GPU reset V2
  drm/radeon/kms: rename gpu_reset to asic_reset
  drm/radeon/kms: fence cleanup + more reliable GPU lockup detection V4

Conflicts:
	drivers/gpu/drm/radeon/r300.c

1 files changed, 3 insertions, 93 deletions

diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 9035121f4b58..c513473d72ae 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -147,16 +147,11 @@ void rv515_gpu_init(struct radeon_device *rdev)
 {
         unsigned pipe_select_current, gb_pipe_select, tmp;
 
-        r100_hdp_reset(rdev);
-        r100_rb2d_reset(rdev);
-
         if (r100_gui_wait_for_idle(rdev)) {
                 printk(KERN_WARNING "Failed to wait GUI idle while "
                        "reseting GPU. Bad things might happen.\n");
         }
-
         rv515_vga_render_disable(rdev);
-
         r420_pipes_init(rdev);
         gb_pipe_select = RREG32(0x402C);
         tmp = RREG32(0x170C);
@@ -174,91 +169,6 @@ void rv515_gpu_init(struct radeon_device *rdev)
         }
 }
 
-int rv515_ga_reset(struct radeon_device *rdev)
-{
-        uint32_t tmp;
-        bool reinit_cp;
-        int i;
-
-        reinit_cp = rdev->cp.ready;
-        rdev->cp.ready = false;
-        for (i = 0; i < rdev->usec_timeout; i++) {
-                WREG32(CP_CSQ_MODE, 0);
-                WREG32(CP_CSQ_CNTL, 0);
-                WREG32(RBBM_SOFT_RESET, 0x32005);
-                (void)RREG32(RBBM_SOFT_RESET);
-                udelay(200);
-                WREG32(RBBM_SOFT_RESET, 0);
-                /* Wait to prevent race in RBBM_STATUS */
-                mdelay(1);
-                tmp = RREG32(RBBM_STATUS);
-                if (tmp & ((1 << 20) | (1 << 26))) {
-                        DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
-                        /* GA still busy soft reset it */
-                        WREG32(0x429C, 0x200);
-                        WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
-                        WREG32(0x43E0, 0);
-                        WREG32(0x43E4, 0);
-                        WREG32(0x24AC, 0);
-                }
-                /* Wait to prevent race in RBBM_STATUS */
-                mdelay(1);
-                tmp = RREG32(RBBM_STATUS);
-                if (!(tmp & ((1 << 20) | (1 << 26)))) {
-                        break;
-                }
-        }
-        for (i = 0; i < rdev->usec_timeout; i++) {
-                tmp = RREG32(RBBM_STATUS);
-                if (!(tmp & ((1 << 20) | (1 << 26)))) {
-                        DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
-                                 tmp);
-                        DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
-                        DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
-                        DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
-                        if (reinit_cp) {
-                                return r100_cp_init(rdev, rdev->cp.ring_size);
-                        }
-                        return 0;
-                }
-                DRM_UDELAY(1);
-        }
-        tmp = RREG32(RBBM_STATUS);
-        DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
-        return -1;
-}
-
-int rv515_gpu_reset(struct radeon_device *rdev)
-{
-        uint32_t status;
-
-        /* reset order likely matter */
-        status = RREG32(RBBM_STATUS);
-        /* reset HDP */
-        r100_hdp_reset(rdev);
-        /* reset rb2d */
-        if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
-                r100_rb2d_reset(rdev);
-        }
-        /* reset GA */
-        if (status & ((1 << 20) | (1 << 26))) {
-                rv515_ga_reset(rdev);
-        }
-        /* reset CP */
-        status = RREG32(RBBM_STATUS);
-        if (status & (1 << 16)) {
-                r100_cp_reset(rdev);
-        }
-        /* Check if GPU is idle */
-        status = RREG32(RBBM_STATUS);
-        if (status & (1 << 31)) {
-                DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
-                return -1;
-        }
-        DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
-        return 0;
-}
-
 static void rv515_vram_get_type(struct radeon_device *rdev)
 {
         uint32_t tmp;
@@ -335,7 +245,7 @@ static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 
         tmp = RREG32(0x2140);
         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
-        radeon_gpu_reset(rdev);
+        radeon_asic_reset(rdev);
         tmp = RREG32(0x425C);
         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
         return 0;
@@ -503,7 +413,7 @@ int rv515_resume(struct radeon_device *rdev)
         /* Resume clock before doing reset */
         rv515_clock_startup(rdev);
         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-        if (radeon_gpu_reset(rdev)) {
+        if (radeon_asic_reset(rdev)) {
                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                         RREG32(R_000E40_RBBM_STATUS),
                         RREG32(R_0007C0_CP_STAT));
@@ -573,7 +483,7 @@ int rv515_init(struct radeon_device *rdev)
                 return -EINVAL;
         }
         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-        if (radeon_gpu_reset(rdev)) {
+        if (radeon_asic_reset(rdev)) {
                 dev_warn(rdev->dev,
                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                         RREG32(R_000E40_RBBM_STATUS),