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authorBen Skeggs <bskeggs@redhat.com>2010-04-27 21:46:42 -0400
committerDave Airlie <airlied@redhat.com>2010-05-18 04:21:33 -0400
commit68adac5e49436992e9c999fbae879d9ac5b72d4e (patch)
tree6593c74a8baf4a0424bbc5b2a06264c0a6a9338d /drivers/gpu/drm/radeon/rs690.c
parent15a7df8db84e7a9d9915d879199ac4a870836c54 (diff)
drm: move radeon_fixed.h to shared drm_fixed.h header
Will be used by nouveau driver also in the near future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rs690.c')
-rw-r--r--drivers/gpu/drm/radeon/rs690.c280
1 files changed, 140 insertions, 140 deletions
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 56a0aec84af2..e8edfe617286 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -76,59 +76,59 @@ void rs690_pm_info(struct radeon_device *rdev)
76 /* Get various system informations from bios */ 76 /* Get various system informations from bios */
77 switch (crev) { 77 switch (crev) {
78 case 1: 78 case 1:
79 tmp.full = rfixed_const(100); 79 tmp.full = dfixed_const(100);
80 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info.ulBootUpMemoryClock); 80 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock);
81 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); 81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
82 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); 82 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
83 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->info.usFSBClock)); 83 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
84 rdev->pm.igp_ht_link_width.full = rfixed_const(info->info.ucHTLinkWidth); 84 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
85 break; 85 break;
86 case 2: 86 case 2:
87 tmp.full = rfixed_const(100); 87 tmp.full = dfixed_const(100);
88 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info_v2.ulBootUpSidePortClock); 88 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock);
89 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); 89 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
90 rdev->pm.igp_system_mclk.full = rfixed_const(info->info_v2.ulBootUpUMAClock); 90 rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
91 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); 91 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
92 rdev->pm.igp_ht_link_clk.full = rfixed_const(info->info_v2.ulHTLinkFreq); 92 rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq);
93 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp); 93 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
94 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); 94 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
95 break; 95 break;
96 default: 96 default:
97 tmp.full = rfixed_const(100); 97 tmp.full = dfixed_const(100);
98 /* We assume the slower possible clock ie worst case */ 98 /* We assume the slower possible clock ie worst case */
99 /* DDR 333Mhz */ 99 /* DDR 333Mhz */
100 rdev->pm.igp_sideport_mclk.full = rfixed_const(333); 100 rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
101 /* FIXME: system clock ? */ 101 /* FIXME: system clock ? */
102 rdev->pm.igp_system_mclk.full = rfixed_const(100); 102 rdev->pm.igp_system_mclk.full = dfixed_const(100);
103 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); 103 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
104 rdev->pm.igp_ht_link_clk.full = rfixed_const(200); 104 rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
105 rdev->pm.igp_ht_link_width.full = rfixed_const(8); 105 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
106 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 106 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
107 break; 107 break;
108 } 108 }
109 } else { 109 } else {
110 tmp.full = rfixed_const(100); 110 tmp.full = dfixed_const(100);
111 /* We assume the slower possible clock ie worst case */ 111 /* We assume the slower possible clock ie worst case */
112 /* DDR 333Mhz */ 112 /* DDR 333Mhz */
113 rdev->pm.igp_sideport_mclk.full = rfixed_const(333); 113 rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
114 /* FIXME: system clock ? */ 114 /* FIXME: system clock ? */
115 rdev->pm.igp_system_mclk.full = rfixed_const(100); 115 rdev->pm.igp_system_mclk.full = dfixed_const(100);
116 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); 116 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
117 rdev->pm.igp_ht_link_clk.full = rfixed_const(200); 117 rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
118 rdev->pm.igp_ht_link_width.full = rfixed_const(8); 118 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
119 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 119 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
120 } 120 }
121 /* Compute various bandwidth */ 121 /* Compute various bandwidth */
122 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 122 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
123 tmp.full = rfixed_const(4); 123 tmp.full = dfixed_const(4);
124 rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp); 124 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
125 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 125 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
126 * = ht_clk * ht_width / 5 126 * = ht_clk * ht_width / 5
127 */ 127 */
128 tmp.full = rfixed_const(5); 128 tmp.full = dfixed_const(5);
129 rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk, 129 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
130 rdev->pm.igp_ht_link_width); 130 rdev->pm.igp_ht_link_width);
131 rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp); 131 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
132 if (tmp.full < rdev->pm.max_bandwidth.full) { 132 if (tmp.full < rdev->pm.max_bandwidth.full) {
133 /* HT link is a limiting factor */ 133 /* HT link is a limiting factor */
134 rdev->pm.max_bandwidth.full = tmp.full; 134 rdev->pm.max_bandwidth.full = tmp.full;
@@ -136,10 +136,10 @@ void rs690_pm_info(struct radeon_device *rdev)
136 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 136 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
137 * = (sideport_clk * 14) / 10 137 * = (sideport_clk * 14) / 10
138 */ 138 */
139 tmp.full = rfixed_const(14); 139 tmp.full = dfixed_const(14);
140 rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp); 140 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
141 tmp.full = rfixed_const(10); 141 tmp.full = dfixed_const(10);
142 rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp); 142 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
143} 143}
144 144
145void rs690_mc_init(struct radeon_device *rdev) 145void rs690_mc_init(struct radeon_device *rdev)
@@ -239,20 +239,20 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
239 return; 239 return;
240 } 240 }
241 241
242 if (crtc->vsc.full > rfixed_const(2)) 242 if (crtc->vsc.full > dfixed_const(2))
243 wm->num_line_pair.full = rfixed_const(2); 243 wm->num_line_pair.full = dfixed_const(2);
244 else 244 else
245 wm->num_line_pair.full = rfixed_const(1); 245 wm->num_line_pair.full = dfixed_const(1);
246 246
247 b.full = rfixed_const(mode->crtc_hdisplay); 247 b.full = dfixed_const(mode->crtc_hdisplay);
248 c.full = rfixed_const(256); 248 c.full = dfixed_const(256);
249 a.full = rfixed_div(b, c); 249 a.full = dfixed_div(b, c);
250 request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair); 250 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
251 request_fifo_depth.full = rfixed_ceil(request_fifo_depth); 251 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
252 if (a.full < rfixed_const(4)) { 252 if (a.full < dfixed_const(4)) {
253 wm->lb_request_fifo_depth = 4; 253 wm->lb_request_fifo_depth = 4;
254 } else { 254 } else {
255 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); 255 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
256 } 256 }
257 257
258 /* Determine consumption rate 258 /* Determine consumption rate
@@ -261,23 +261,23 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
261 * vsc = vertical scaling ratio, defined as source/destination 261 * vsc = vertical scaling ratio, defined as source/destination
262 * hsc = horizontal scaling ration, defined as source/destination 262 * hsc = horizontal scaling ration, defined as source/destination
263 */ 263 */
264 a.full = rfixed_const(mode->clock); 264 a.full = dfixed_const(mode->clock);
265 b.full = rfixed_const(1000); 265 b.full = dfixed_const(1000);
266 a.full = rfixed_div(a, b); 266 a.full = dfixed_div(a, b);
267 pclk.full = rfixed_div(b, a); 267 pclk.full = dfixed_div(b, a);
268 if (crtc->rmx_type != RMX_OFF) { 268 if (crtc->rmx_type != RMX_OFF) {
269 b.full = rfixed_const(2); 269 b.full = dfixed_const(2);
270 if (crtc->vsc.full > b.full) 270 if (crtc->vsc.full > b.full)
271 b.full = crtc->vsc.full; 271 b.full = crtc->vsc.full;
272 b.full = rfixed_mul(b, crtc->hsc); 272 b.full = dfixed_mul(b, crtc->hsc);
273 c.full = rfixed_const(2); 273 c.full = dfixed_const(2);
274 b.full = rfixed_div(b, c); 274 b.full = dfixed_div(b, c);
275 consumption_time.full = rfixed_div(pclk, b); 275 consumption_time.full = dfixed_div(pclk, b);
276 } else { 276 } else {
277 consumption_time.full = pclk.full; 277 consumption_time.full = pclk.full;
278 } 278 }
279 a.full = rfixed_const(1); 279 a.full = dfixed_const(1);
280 wm->consumption_rate.full = rfixed_div(a, consumption_time); 280 wm->consumption_rate.full = dfixed_div(a, consumption_time);
281 281
282 282
283 /* Determine line time 283 /* Determine line time
@@ -285,18 +285,18 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
285 * LineTime = total number of horizontal pixels 285 * LineTime = total number of horizontal pixels
286 * pclk = pixel clock period(ns) 286 * pclk = pixel clock period(ns)
287 */ 287 */
288 a.full = rfixed_const(crtc->base.mode.crtc_htotal); 288 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
289 line_time.full = rfixed_mul(a, pclk); 289 line_time.full = dfixed_mul(a, pclk);
290 290
291 /* Determine active time 291 /* Determine active time
292 * ActiveTime = time of active region of display within one line, 292 * ActiveTime = time of active region of display within one line,
293 * hactive = total number of horizontal active pixels 293 * hactive = total number of horizontal active pixels
294 * htotal = total number of horizontal pixels 294 * htotal = total number of horizontal pixels
295 */ 295 */
296 a.full = rfixed_const(crtc->base.mode.crtc_htotal); 296 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
297 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); 297 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
298 wm->active_time.full = rfixed_mul(line_time, b); 298 wm->active_time.full = dfixed_mul(line_time, b);
299 wm->active_time.full = rfixed_div(wm->active_time, a); 299 wm->active_time.full = dfixed_div(wm->active_time, a);
300 300
301 /* Maximun bandwidth is the minimun bandwidth of all component */ 301 /* Maximun bandwidth is the minimun bandwidth of all component */
302 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; 302 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
@@ -304,8 +304,8 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
304 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 304 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
305 rdev->pm.sideport_bandwidth.full) 305 rdev->pm.sideport_bandwidth.full)
306 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; 306 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
307 read_delay_latency.full = rfixed_const(370 * 800 * 1000); 307 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
308 read_delay_latency.full = rfixed_div(read_delay_latency, 308 read_delay_latency.full = dfixed_div(read_delay_latency,
309 rdev->pm.igp_sideport_mclk); 309 rdev->pm.igp_sideport_mclk);
310 } else { 310 } else {
311 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && 311 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
@@ -314,23 +314,23 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
314 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && 314 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
315 rdev->pm.ht_bandwidth.full) 315 rdev->pm.ht_bandwidth.full)
316 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; 316 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
317 read_delay_latency.full = rfixed_const(5000); 317 read_delay_latency.full = dfixed_const(5000);
318 } 318 }
319 319
320 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ 320 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
321 a.full = rfixed_const(16); 321 a.full = dfixed_const(16);
322 rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a); 322 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
323 a.full = rfixed_const(1000); 323 a.full = dfixed_const(1000);
324 rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk); 324 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
325 /* Determine chunk time 325 /* Determine chunk time
326 * ChunkTime = the time it takes the DCP to send one chunk of data 326 * ChunkTime = the time it takes the DCP to send one chunk of data
327 * to the LB which consists of pipeline delay and inter chunk gap 327 * to the LB which consists of pipeline delay and inter chunk gap
328 * sclk = system clock(ns) 328 * sclk = system clock(ns)
329 */ 329 */
330 a.full = rfixed_const(256 * 13); 330 a.full = dfixed_const(256 * 13);
331 chunk_time.full = rfixed_mul(rdev->pm.sclk, a); 331 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
332 a.full = rfixed_const(10); 332 a.full = dfixed_const(10);
333 chunk_time.full = rfixed_div(chunk_time, a); 333 chunk_time.full = dfixed_div(chunk_time, a);
334 334
335 /* Determine the worst case latency 335 /* Determine the worst case latency
336 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 336 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
@@ -340,13 +340,13 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
340 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 340 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
341 * which consists of pipeline delay and inter chunk gap 341 * which consists of pipeline delay and inter chunk gap
342 */ 342 */
343 if (rfixed_trunc(wm->num_line_pair) > 1) { 343 if (dfixed_trunc(wm->num_line_pair) > 1) {
344 a.full = rfixed_const(3); 344 a.full = dfixed_const(3);
345 wm->worst_case_latency.full = rfixed_mul(a, chunk_time); 345 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
346 wm->worst_case_latency.full += read_delay_latency.full; 346 wm->worst_case_latency.full += read_delay_latency.full;
347 } else { 347 } else {
348 a.full = rfixed_const(2); 348 a.full = dfixed_const(2);
349 wm->worst_case_latency.full = rfixed_mul(a, chunk_time); 349 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
350 wm->worst_case_latency.full += read_delay_latency.full; 350 wm->worst_case_latency.full += read_delay_latency.full;
351 } 351 }
352 352
@@ -360,34 +360,34 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
360 * of data to the LB which consists of 360 * of data to the LB which consists of
361 * pipeline delay and inter chunk gap 361 * pipeline delay and inter chunk gap
362 */ 362 */
363 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { 363 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
364 tolerable_latency.full = line_time.full; 364 tolerable_latency.full = line_time.full;
365 } else { 365 } else {
366 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); 366 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
367 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 367 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
368 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); 368 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
369 tolerable_latency.full = line_time.full - tolerable_latency.full; 369 tolerable_latency.full = line_time.full - tolerable_latency.full;
370 } 370 }
371 /* We assume worst case 32bits (4 bytes) */ 371 /* We assume worst case 32bits (4 bytes) */
372 wm->dbpp.full = rfixed_const(4 * 8); 372 wm->dbpp.full = dfixed_const(4 * 8);
373 373
374 /* Determine the maximum priority mark 374 /* Determine the maximum priority mark
375 * width = viewport width in pixels 375 * width = viewport width in pixels
376 */ 376 */
377 a.full = rfixed_const(16); 377 a.full = dfixed_const(16);
378 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); 378 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
379 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); 379 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
380 wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max); 380 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
381 381
382 /* Determine estimated width */ 382 /* Determine estimated width */
383 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 383 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
384 estimated_width.full = rfixed_div(estimated_width, consumption_time); 384 estimated_width.full = dfixed_div(estimated_width, consumption_time);
385 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 385 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
386 wm->priority_mark.full = rfixed_const(10); 386 wm->priority_mark.full = dfixed_const(10);
387 } else { 387 } else {
388 a.full = rfixed_const(16); 388 a.full = dfixed_const(16);
389 wm->priority_mark.full = rfixed_div(estimated_width, a); 389 wm->priority_mark.full = dfixed_div(estimated_width, a);
390 wm->priority_mark.full = rfixed_ceil(wm->priority_mark); 390 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
391 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 391 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
392 } 392 }
393} 393}
@@ -439,58 +439,58 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
439 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); 439 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
440 440
441 if (mode0 && mode1) { 441 if (mode0 && mode1) {
442 if (rfixed_trunc(wm0.dbpp) > 64) 442 if (dfixed_trunc(wm0.dbpp) > 64)
443 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); 443 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
444 else 444 else
445 a.full = wm0.num_line_pair.full; 445 a.full = wm0.num_line_pair.full;
446 if (rfixed_trunc(wm1.dbpp) > 64) 446 if (dfixed_trunc(wm1.dbpp) > 64)
447 b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); 447 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
448 else 448 else
449 b.full = wm1.num_line_pair.full; 449 b.full = wm1.num_line_pair.full;
450 a.full += b.full; 450 a.full += b.full;
451 fill_rate.full = rfixed_div(wm0.sclk, a); 451 fill_rate.full = dfixed_div(wm0.sclk, a);
452 if (wm0.consumption_rate.full > fill_rate.full) { 452 if (wm0.consumption_rate.full > fill_rate.full) {
453 b.full = wm0.consumption_rate.full - fill_rate.full; 453 b.full = wm0.consumption_rate.full - fill_rate.full;
454 b.full = rfixed_mul(b, wm0.active_time); 454 b.full = dfixed_mul(b, wm0.active_time);
455 a.full = rfixed_mul(wm0.worst_case_latency, 455 a.full = dfixed_mul(wm0.worst_case_latency,
456 wm0.consumption_rate); 456 wm0.consumption_rate);
457 a.full = a.full + b.full; 457 a.full = a.full + b.full;
458 b.full = rfixed_const(16 * 1000); 458 b.full = dfixed_const(16 * 1000);
459 priority_mark02.full = rfixed_div(a, b); 459 priority_mark02.full = dfixed_div(a, b);
460 } else { 460 } else {
461 a.full = rfixed_mul(wm0.worst_case_latency, 461 a.full = dfixed_mul(wm0.worst_case_latency,
462 wm0.consumption_rate); 462 wm0.consumption_rate);
463 b.full = rfixed_const(16 * 1000); 463 b.full = dfixed_const(16 * 1000);
464 priority_mark02.full = rfixed_div(a, b); 464 priority_mark02.full = dfixed_div(a, b);
465 } 465 }
466 if (wm1.consumption_rate.full > fill_rate.full) { 466 if (wm1.consumption_rate.full > fill_rate.full) {
467 b.full = wm1.consumption_rate.full - fill_rate.full; 467 b.full = wm1.consumption_rate.full - fill_rate.full;
468 b.full = rfixed_mul(b, wm1.active_time); 468 b.full = dfixed_mul(b, wm1.active_time);
469 a.full = rfixed_mul(wm1.worst_case_latency, 469 a.full = dfixed_mul(wm1.worst_case_latency,
470 wm1.consumption_rate); 470 wm1.consumption_rate);
471 a.full = a.full + b.full; 471 a.full = a.full + b.full;
472 b.full = rfixed_const(16 * 1000); 472 b.full = dfixed_const(16 * 1000);
473 priority_mark12.full = rfixed_div(a, b); 473 priority_mark12.full = dfixed_div(a, b);
474 } else { 474 } else {
475 a.full = rfixed_mul(wm1.worst_case_latency, 475 a.full = dfixed_mul(wm1.worst_case_latency,
476 wm1.consumption_rate); 476 wm1.consumption_rate);
477 b.full = rfixed_const(16 * 1000); 477 b.full = dfixed_const(16 * 1000);
478 priority_mark12.full = rfixed_div(a, b); 478 priority_mark12.full = dfixed_div(a, b);
479 } 479 }
480 if (wm0.priority_mark.full > priority_mark02.full) 480 if (wm0.priority_mark.full > priority_mark02.full)
481 priority_mark02.full = wm0.priority_mark.full; 481 priority_mark02.full = wm0.priority_mark.full;
482 if (rfixed_trunc(priority_mark02) < 0) 482 if (dfixed_trunc(priority_mark02) < 0)
483 priority_mark02.full = 0; 483 priority_mark02.full = 0;
484 if (wm0.priority_mark_max.full > priority_mark02.full) 484 if (wm0.priority_mark_max.full > priority_mark02.full)
485 priority_mark02.full = wm0.priority_mark_max.full; 485 priority_mark02.full = wm0.priority_mark_max.full;
486 if (wm1.priority_mark.full > priority_mark12.full) 486 if (wm1.priority_mark.full > priority_mark12.full)
487 priority_mark12.full = wm1.priority_mark.full; 487 priority_mark12.full = wm1.priority_mark.full;
488 if (rfixed_trunc(priority_mark12) < 0) 488 if (dfixed_trunc(priority_mark12) < 0)
489 priority_mark12.full = 0; 489 priority_mark12.full = 0;
490 if (wm1.priority_mark_max.full > priority_mark12.full) 490 if (wm1.priority_mark_max.full > priority_mark12.full)
491 priority_mark12.full = wm1.priority_mark_max.full; 491 priority_mark12.full = wm1.priority_mark_max.full;
492 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); 492 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
493 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); 493 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
494 if (rdev->disp_priority == 2) { 494 if (rdev->disp_priority == 2) {
495 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 495 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
496 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 496 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
@@ -500,32 +500,32 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
500 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 500 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
501 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 501 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
502 } else if (mode0) { 502 } else if (mode0) {
503 if (rfixed_trunc(wm0.dbpp) > 64) 503 if (dfixed_trunc(wm0.dbpp) > 64)
504 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); 504 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
505 else 505 else
506 a.full = wm0.num_line_pair.full; 506 a.full = wm0.num_line_pair.full;
507 fill_rate.full = rfixed_div(wm0.sclk, a); 507 fill_rate.full = dfixed_div(wm0.sclk, a);
508 if (wm0.consumption_rate.full > fill_rate.full) { 508 if (wm0.consumption_rate.full > fill_rate.full) {
509 b.full = wm0.consumption_rate.full - fill_rate.full; 509 b.full = wm0.consumption_rate.full - fill_rate.full;
510 b.full = rfixed_mul(b, wm0.active_time); 510 b.full = dfixed_mul(b, wm0.active_time);
511 a.full = rfixed_mul(wm0.worst_case_latency, 511 a.full = dfixed_mul(wm0.worst_case_latency,
512 wm0.consumption_rate); 512 wm0.consumption_rate);
513 a.full = a.full + b.full; 513 a.full = a.full + b.full;
514 b.full = rfixed_const(16 * 1000); 514 b.full = dfixed_const(16 * 1000);
515 priority_mark02.full = rfixed_div(a, b); 515 priority_mark02.full = dfixed_div(a, b);
516 } else { 516 } else {
517 a.full = rfixed_mul(wm0.worst_case_latency, 517 a.full = dfixed_mul(wm0.worst_case_latency,
518 wm0.consumption_rate); 518 wm0.consumption_rate);
519 b.full = rfixed_const(16 * 1000); 519 b.full = dfixed_const(16 * 1000);
520 priority_mark02.full = rfixed_div(a, b); 520 priority_mark02.full = dfixed_div(a, b);
521 } 521 }
522 if (wm0.priority_mark.full > priority_mark02.full) 522 if (wm0.priority_mark.full > priority_mark02.full)
523 priority_mark02.full = wm0.priority_mark.full; 523 priority_mark02.full = wm0.priority_mark.full;
524 if (rfixed_trunc(priority_mark02) < 0) 524 if (dfixed_trunc(priority_mark02) < 0)
525 priority_mark02.full = 0; 525 priority_mark02.full = 0;
526 if (wm0.priority_mark_max.full > priority_mark02.full) 526 if (wm0.priority_mark_max.full > priority_mark02.full)
527 priority_mark02.full = wm0.priority_mark_max.full; 527 priority_mark02.full = wm0.priority_mark_max.full;
528 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); 528 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
529 if (rdev->disp_priority == 2) 529 if (rdev->disp_priority == 2)
530 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 530 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
531 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 531 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
@@ -535,32 +535,32 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
535 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, 535 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
536 S_006D4C_D2MODE_PRIORITY_B_OFF(1)); 536 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
537 } else { 537 } else {
538 if (rfixed_trunc(wm1.dbpp) > 64) 538 if (dfixed_trunc(wm1.dbpp) > 64)
539 a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); 539 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
540 else 540 else
541 a.full = wm1.num_line_pair.full; 541 a.full = wm1.num_line_pair.full;
542 fill_rate.full = rfixed_div(wm1.sclk, a); 542 fill_rate.full = dfixed_div(wm1.sclk, a);
543 if (wm1.consumption_rate.full > fill_rate.full) { 543 if (wm1.consumption_rate.full > fill_rate.full) {
544 b.full = wm1.consumption_rate.full - fill_rate.full; 544 b.full = wm1.consumption_rate.full - fill_rate.full;
545 b.full = rfixed_mul(b, wm1.active_time); 545 b.full = dfixed_mul(b, wm1.active_time);
546 a.full = rfixed_mul(wm1.worst_case_latency, 546 a.full = dfixed_mul(wm1.worst_case_latency,
547 wm1.consumption_rate); 547 wm1.consumption_rate);
548 a.full = a.full + b.full; 548 a.full = a.full + b.full;
549 b.full = rfixed_const(16 * 1000); 549 b.full = dfixed_const(16 * 1000);
550 priority_mark12.full = rfixed_div(a, b); 550 priority_mark12.full = dfixed_div(a, b);
551 } else { 551 } else {
552 a.full = rfixed_mul(wm1.worst_case_latency, 552 a.full = dfixed_mul(wm1.worst_case_latency,
553 wm1.consumption_rate); 553 wm1.consumption_rate);
554 b.full = rfixed_const(16 * 1000); 554 b.full = dfixed_const(16 * 1000);
555 priority_mark12.full = rfixed_div(a, b); 555 priority_mark12.full = dfixed_div(a, b);
556 } 556 }
557 if (wm1.priority_mark.full > priority_mark12.full) 557 if (wm1.priority_mark.full > priority_mark12.full)
558 priority_mark12.full = wm1.priority_mark.full; 558 priority_mark12.full = wm1.priority_mark.full;
559 if (rfixed_trunc(priority_mark12) < 0) 559 if (dfixed_trunc(priority_mark12) < 0)
560 priority_mark12.full = 0; 560 priority_mark12.full = 0;
561 if (wm1.priority_mark_max.full > priority_mark12.full) 561 if (wm1.priority_mark_max.full > priority_mark12.full)
562 priority_mark12.full = wm1.priority_mark_max.full; 562 priority_mark12.full = wm1.priority_mark_max.full;
563 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); 563 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
564 if (rdev->disp_priority == 2) 564 if (rdev->disp_priority == 2)
565 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 565 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
566 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, 566 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,