diff options
author | Jerome Glisse <jglisse@redhat.com> | 2010-03-09 09:45:12 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-04-05 21:21:11 -0400 |
commit | 90aca4d2740255bd130ea71a91530b9920c70abe (patch) | |
tree | acf9b8a4353e6727cd6cba5b71caaf9f067e465d /drivers/gpu/drm/radeon/rs600.c | |
parent | a2d07b7438f015a0349bc9af3c96a8164549bbc5 (diff) |
drm/radeon/kms: simplify & improve GPU reset V2
This simplify and improve GPU reset for R1XX-R6XX hw, it's
not 100% reliable here are result:
- R1XX/R2XX works bunch of time in a row, sometimes it
seems it can work indifinitly
- R3XX/R3XX the most unreliable one, sometimes you will be
able to reset few times, sometimes not even once
- R5XX more reliable than previous hw, seems to work most
of the times but once in a while it fails for no obvious
reasons (same status than previous reset just no same
happy ending)
- R6XX/R7XX are lot more reliable with this patch, still
it seems that it can fail after a bunch (reset every
2sec for 3hour bring down the GPU & computer)
This have been tested on various hw, for some odd reasons
i wasn't able to lockup RS480/RS690 (while they use to
love locking up).
Note that on R1XX-R5XX the cursor will disapear after
lockup haven't checked why, switch to console and back
to X will restore cursor.
Next step is to record the bogus command that leaded to
the lockup.
V2 Fix r6xx resume path to avoid reinitializing blit
module, use the gpu_lockup boolean to avoid entering
inifinite waiting loop on fence while reiniting the GPU
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rs600.c')
-rw-r--r-- | drivers/gpu/drm/radeon/rs600.c | 73 |
1 files changed, 72 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index c1be20afd429..a16d9d79f36f 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
@@ -147,6 +147,78 @@ void rs600_hpd_fini(struct radeon_device *rdev) | |||
147 | } | 147 | } |
148 | } | 148 | } |
149 | 149 | ||
150 | void rs600_bm_disable(struct radeon_device *rdev) | ||
151 | { | ||
152 | u32 tmp; | ||
153 | |||
154 | /* disable bus mastering */ | ||
155 | pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp); | ||
156 | pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB); | ||
157 | mdelay(1); | ||
158 | } | ||
159 | |||
160 | int rs600_asic_reset(struct radeon_device *rdev) | ||
161 | { | ||
162 | u32 status, tmp; | ||
163 | |||
164 | struct rv515_mc_save save; | ||
165 | |||
166 | /* Stops all mc clients */ | ||
167 | rv515_mc_stop(rdev, &save); | ||
168 | status = RREG32(R_000E40_RBBM_STATUS); | ||
169 | if (!G_000E40_GUI_ACTIVE(status)) { | ||
170 | return 0; | ||
171 | } | ||
172 | status = RREG32(R_000E40_RBBM_STATUS); | ||
173 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | ||
174 | /* stop CP */ | ||
175 | WREG32(RADEON_CP_CSQ_CNTL, 0); | ||
176 | tmp = RREG32(RADEON_CP_RB_CNTL); | ||
177 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); | ||
178 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | ||
179 | WREG32(RADEON_CP_RB_WPTR, 0); | ||
180 | WREG32(RADEON_CP_RB_CNTL, tmp); | ||
181 | pci_save_state(rdev->pdev); | ||
182 | /* disable bus mastering */ | ||
183 | rs600_bm_disable(rdev); | ||
184 | /* reset GA+VAP */ | ||
185 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | | ||
186 | S_0000F0_SOFT_RESET_GA(1)); | ||
187 | RREG32(R_0000F0_RBBM_SOFT_RESET); | ||
188 | mdelay(500); | ||
189 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | ||
190 | mdelay(1); | ||
191 | status = RREG32(R_000E40_RBBM_STATUS); | ||
192 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | ||
193 | /* reset CP */ | ||
194 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); | ||
195 | RREG32(R_0000F0_RBBM_SOFT_RESET); | ||
196 | mdelay(500); | ||
197 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | ||
198 | mdelay(1); | ||
199 | status = RREG32(R_000E40_RBBM_STATUS); | ||
200 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | ||
201 | /* reset MC */ | ||
202 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); | ||
203 | RREG32(R_0000F0_RBBM_SOFT_RESET); | ||
204 | mdelay(500); | ||
205 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | ||
206 | mdelay(1); | ||
207 | status = RREG32(R_000E40_RBBM_STATUS); | ||
208 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | ||
209 | /* restore PCI & busmastering */ | ||
210 | pci_restore_state(rdev->pdev); | ||
211 | /* Check if GPU is idle */ | ||
212 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { | ||
213 | dev_err(rdev->dev, "failed to reset GPU\n"); | ||
214 | rdev->gpu_lockup = true; | ||
215 | return -1; | ||
216 | } | ||
217 | rv515_mc_resume(rdev, &save); | ||
218 | dev_info(rdev->dev, "GPU reset succeed\n"); | ||
219 | return 0; | ||
220 | } | ||
221 | |||
150 | /* | 222 | /* |
151 | * GART. | 223 | * GART. |
152 | */ | 224 | */ |
@@ -454,7 +526,6 @@ int rs600_mc_wait_for_idle(struct radeon_device *rdev) | |||
454 | 526 | ||
455 | void rs600_gpu_init(struct radeon_device *rdev) | 527 | void rs600_gpu_init(struct radeon_device *rdev) |
456 | { | 528 | { |
457 | r100_hdp_reset(rdev); | ||
458 | r420_pipes_init(rdev); | 529 | r420_pipes_init(rdev); |
459 | /* Wait for mc idle */ | 530 | /* Wait for mc idle */ |
460 | if (rs600_mc_wait_for_idle(rdev)) | 531 | if (rs600_mc_wait_for_idle(rdev)) |