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authorLinus Torvalds <torvalds@linux-foundation.org>2010-03-04 10:49:37 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2010-03-04 10:49:37 -0500
commit03a2c4d76c9e99b80d74ab8a4f344e135a5ae44b (patch)
tree7fd7940a4f87dc1ace1c1bdeb1fb0d90ac3beb13 /drivers/gpu/drm/radeon/rs600.c
parenta27341cd5fcb7cf2d2d4726e9f324009f7162c00 (diff)
parentd424b925f7092b9d95e0a8556872349abe79d9b6 (diff)
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (151 commits) vga_switcheroo: disable default y by new rules. drm/nouveau: fix *staging* driver build with switcheroo off. drm/radeon: fix typo in Makefile vga_switcheroo: fix build on platforms with no ACPI drm/radeon: Fix printf type warning in 64bit system. drm/radeon/kms: bump the KMS version number for square tiling support. vga_switcheroo: initial implementation (v15) drm/radeon/kms: do not disable audio engine twice Revert "drm/radeon/kms: disable HDMI audio for now on rv710/rv730" drm/radeon/kms: do not preset audio stuff and start timer when not using audio drm/radeon: r100/r200 ums: block ability for userspace app to trash 0 page and beyond drm/ttm: fix function prototype to match implementation drm/radeon: use ALIGN instead of open coding it drm/radeon/kms: initialize set_surface_reg reg for rs600 asic drm/i915: Use a dmi quirk to skip a broken SDVO TV output. drm/i915: enable/disable LVDS port at DPMS time drm/i915: check for multiple write domains in pin_and_relocate drm/i915: clean-up i915_gem_flush_gpu_write_domain drm/i915: reuse i915_gpu_idle helper drm/i915: ensure lru ordering of fence_list ... Fixed trivial conflicts in drivers/gpu/vga/Kconfig
Diffstat (limited to 'drivers/gpu/drm/radeon/rs600.c')
-rw-r--r--drivers/gpu/drm/radeon/rs600.c56
1 files changed, 20 insertions, 36 deletions
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index c3818562a13e..47f046b78c6b 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -45,23 +45,6 @@
45void rs600_gpu_init(struct radeon_device *rdev); 45void rs600_gpu_init(struct radeon_device *rdev);
46int rs600_mc_wait_for_idle(struct radeon_device *rdev); 46int rs600_mc_wait_for_idle(struct radeon_device *rdev);
47 47
48int rs600_mc_init(struct radeon_device *rdev)
49{
50 /* read back the MC value from the hw */
51 int r;
52 u32 tmp;
53
54 /* Setup GPU memory space */
55 tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
56 rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
57 rdev->mc.gtt_location = 0xffffffffUL;
58 r = radeon_mc_setup(rdev);
59 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
60 if (r)
61 return r;
62 return 0;
63}
64
65/* hpd for digital panel detect/disconnect */ 48/* hpd for digital panel detect/disconnect */
66bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 49bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
67{ 50{
@@ -213,6 +196,7 @@ int rs600_gart_enable(struct radeon_device *rdev)
213 r = radeon_gart_table_vram_pin(rdev); 196 r = radeon_gart_table_vram_pin(rdev);
214 if (r) 197 if (r)
215 return r; 198 return r;
199 radeon_gart_restore(rdev);
216 /* Enable bus master */ 200 /* Enable bus master */
217 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; 201 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
218 WREG32(R_00004C_BUS_CNTL, tmp); 202 WREG32(R_00004C_BUS_CNTL, tmp);
@@ -406,10 +390,14 @@ int rs600_irq_process(struct radeon_device *rdev)
406 if (G_000044_SW_INT(status)) 390 if (G_000044_SW_INT(status))
407 radeon_fence_process(rdev); 391 radeon_fence_process(rdev);
408 /* Vertical blank interrupts */ 392 /* Vertical blank interrupts */
409 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) 393 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
410 drm_handle_vblank(rdev->ddev, 0); 394 drm_handle_vblank(rdev->ddev, 0);
411 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) 395 wake_up(&rdev->irq.vblank_queue);
396 }
397 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
412 drm_handle_vblank(rdev->ddev, 1); 398 drm_handle_vblank(rdev->ddev, 1);
399 wake_up(&rdev->irq.vblank_queue);
400 }
413 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) { 401 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
414 queue_hotplug = true; 402 queue_hotplug = true;
415 DRM_DEBUG("HPD1\n"); 403 DRM_DEBUG("HPD1\n");
@@ -470,22 +458,22 @@ void rs600_gpu_init(struct radeon_device *rdev)
470 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 458 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
471} 459}
472 460
473void rs600_vram_info(struct radeon_device *rdev) 461void rs600_mc_init(struct radeon_device *rdev)
474{ 462{
463 u64 base;
464
465 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
466 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
475 rdev->mc.vram_is_ddr = true; 467 rdev->mc.vram_is_ddr = true;
476 rdev->mc.vram_width = 128; 468 rdev->mc.vram_width = 128;
477
478 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 469 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
479 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 470 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
480 471 rdev->mc.visible_vram_size = rdev->mc.aper_size;
481 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 472 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
482 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 473 base = RREG32_MC(R_000004_MC_FB_LOCATION);
483 474 base = G_000004_MC_FB_START(base) << 16;
484 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) 475 radeon_vram_location(rdev, &rdev->mc, base);
485 rdev->mc.mc_vram_size = rdev->mc.aper_size; 476 radeon_gtt_location(rdev, &rdev->mc);
486
487 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
488 rdev->mc.real_vram_size = rdev->mc.aper_size;
489} 477}
490 478
491void rs600_bandwidth_update(struct radeon_device *rdev) 479void rs600_bandwidth_update(struct radeon_device *rdev)
@@ -661,12 +649,8 @@ int rs600_init(struct radeon_device *rdev)
661 radeon_get_clock_info(rdev->ddev); 649 radeon_get_clock_info(rdev->ddev);
662 /* Initialize power management */ 650 /* Initialize power management */
663 radeon_pm_init(rdev); 651 radeon_pm_init(rdev);
664 /* Get vram informations */ 652 /* initialize memory controller */
665 rs600_vram_info(rdev); 653 rs600_mc_init(rdev);
666 /* Initialize memory controller (also test AGP) */
667 r = rs600_mc_init(rdev);
668 if (r)
669 return r;
670 rs600_debugfs(rdev); 654 rs600_debugfs(rdev);
671 /* Fence driver */ 655 /* Fence driver */
672 r = radeon_fence_driver_init(rdev); 656 r = radeon_fence_driver_init(rdev);