aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/rs400.c
diff options
context:
space:
mode:
authorAlex Deucher <alexdeucher@gmail.com>2010-08-27 18:25:25 -0400
committerDave Airlie <airlied@redhat.com>2010-10-05 21:38:08 -0400
commit724c80e1d630296d1324859e964d80d35007d83c (patch)
tree954e86447e1c259160d09c732ac0eb0289b2ec8b /drivers/gpu/drm/radeon/rs400.c
parentb70d6bb3f67b2e2964abafb0117f1733f062cba5 (diff)
drm/radeon/kms: enable writeback (v2)
When writeback is enabled, the GPU shadows writes to certain registers into a buffer in memory. The driver can then read the values from the shadow rather than reading back from the register across the bus. Writeback can be disabled by setting the no_wb module param to 1. On r6xx/r7xx/evergreen, the following registers are shadowed: - CP scratch registers - CP read pointer - IH write pointer On r1xx-rr5xx, the following registers are shadowed: - CP scratch registers - CP read pointer v2: - Combine wb patches for r6xx-evergreen and r1xx-r5xx - Writeback is disabled on AGP boards since it tends to be unreliable on AGP using the gart. - Check radeon_wb_init return values properly. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rs400.c')
-rw-r--r--drivers/gpu/drm/radeon/rs400.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index ae2b76b9a388..f683e51a2a06 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -397,6 +397,12 @@ static int rs400_startup(struct radeon_device *rdev)
397 r = rs400_gart_enable(rdev); 397 r = rs400_gart_enable(rdev);
398 if (r) 398 if (r)
399 return r; 399 return r;
400
401 /* allocate wb buffer */
402 r = radeon_wb_init(rdev);
403 if (r)
404 return r;
405
400 /* Enable IRQ */ 406 /* Enable IRQ */
401 r100_irq_set(rdev); 407 r100_irq_set(rdev);
402 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 408 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -406,9 +412,6 @@ static int rs400_startup(struct radeon_device *rdev)
406 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 412 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
407 return r; 413 return r;
408 } 414 }
409 r = r100_wb_init(rdev);
410 if (r)
411 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
412 r = r100_ib_init(rdev); 415 r = r100_ib_init(rdev);
413 if (r) { 416 if (r) {
414 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 417 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
@@ -443,7 +446,7 @@ int rs400_resume(struct radeon_device *rdev)
443int rs400_suspend(struct radeon_device *rdev) 446int rs400_suspend(struct radeon_device *rdev)
444{ 447{
445 r100_cp_disable(rdev); 448 r100_cp_disable(rdev);
446 r100_wb_disable(rdev); 449 radeon_wb_disable(rdev);
447 r100_irq_disable(rdev); 450 r100_irq_disable(rdev);
448 rs400_gart_disable(rdev); 451 rs400_gart_disable(rdev);
449 return 0; 452 return 0;
@@ -452,7 +455,7 @@ int rs400_suspend(struct radeon_device *rdev)
452void rs400_fini(struct radeon_device *rdev) 455void rs400_fini(struct radeon_device *rdev)
453{ 456{
454 r100_cp_fini(rdev); 457 r100_cp_fini(rdev);
455 r100_wb_fini(rdev); 458 radeon_wb_fini(rdev);
456 r100_ib_fini(rdev); 459 r100_ib_fini(rdev);
457 radeon_gem_fini(rdev); 460 radeon_gem_fini(rdev);
458 rs400_gart_fini(rdev); 461 rs400_gart_fini(rdev);
@@ -526,7 +529,7 @@ int rs400_init(struct radeon_device *rdev)
526 /* Somethings want wront with the accel init stop accel */ 529 /* Somethings want wront with the accel init stop accel */
527 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 530 dev_err(rdev->dev, "Disabling GPU acceleration\n");
528 r100_cp_fini(rdev); 531 r100_cp_fini(rdev);
529 r100_wb_fini(rdev); 532 radeon_wb_fini(rdev);
530 r100_ib_fini(rdev); 533 r100_ib_fini(rdev);
531 rs400_gart_fini(rdev); 534 rs400_gart_fini(rdev);
532 radeon_irq_kms_fini(rdev); 535 radeon_irq_kms_fini(rdev);