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authorJerome Glisse <jglisse@redhat.com>2010-02-17 16:54:29 -0500
committerDave Airlie <airlied@redhat.com>2010-02-17 23:49:35 -0500
commitd594e46ace22afa1621254f6f669e65430048153 (patch)
treebefd5b54ce1b8284acc4ee450d085a7d2c7b01fd /drivers/gpu/drm/radeon/radeon_ttm.c
parent44ca7478d46aaad488d916f7262253e000ee60f9 (diff)
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the computation of vram_start|end & gtt_start|end. For R1XX-R2XX we place VRAM at the same address of PCI aperture, those GPU shouldn't have much memory and seems to behave better when setup that way. For R3XX and newer we place VRAM at 0. For R6XX-R7XX AGP we place VRAM before or after AGP aperture this might limit to limit the VRAM size but it's very unlikely. For IGP we don't change the VRAM placement. Tested on (compiz,quake3,suspend/resume): PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710 AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730 IGP:RS480(RPB*),RS690,RS780(RPB*),RS880 RPB: resume previously broken V2 correct commit message to reflect more accurately the bug and move VRAM placement to 0 for most of the GPU to avoid limiting VRAM. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_ttm.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index db820ae9a034..1157e0f758fa 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -150,7 +150,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
150 man->default_caching = TTM_PL_FLAG_CACHED; 150 man->default_caching = TTM_PL_FLAG_CACHED;
151 break; 151 break;
152 case TTM_PL_TT: 152 case TTM_PL_TT:
153 man->gpu_offset = rdev->mc.gtt_location; 153 man->gpu_offset = rdev->mc.gtt_start;
154 man->available_caching = TTM_PL_MASK_CACHING; 154 man->available_caching = TTM_PL_MASK_CACHING;
155 man->default_caching = TTM_PL_FLAG_CACHED; 155 man->default_caching = TTM_PL_FLAG_CACHED;
156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
@@ -180,7 +180,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
180 break; 180 break;
181 case TTM_PL_VRAM: 181 case TTM_PL_VRAM:
182 /* "On-card" video ram */ 182 /* "On-card" video ram */
183 man->gpu_offset = rdev->mc.vram_location; 183 man->gpu_offset = rdev->mc.vram_start;
184 man->flags = TTM_MEMTYPE_FLAG_FIXED | 184 man->flags = TTM_MEMTYPE_FLAG_FIXED |
185 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP | 185 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
186 TTM_MEMTYPE_FLAG_MAPPABLE; 186 TTM_MEMTYPE_FLAG_MAPPABLE;
@@ -262,10 +262,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo,
262 262
263 switch (old_mem->mem_type) { 263 switch (old_mem->mem_type) {
264 case TTM_PL_VRAM: 264 case TTM_PL_VRAM:
265 old_start += rdev->mc.vram_location; 265 old_start += rdev->mc.vram_start;
266 break; 266 break;
267 case TTM_PL_TT: 267 case TTM_PL_TT:
268 old_start += rdev->mc.gtt_location; 268 old_start += rdev->mc.gtt_start;
269 break; 269 break;
270 default: 270 default:
271 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 271 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
@@ -273,10 +273,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo,
273 } 273 }
274 switch (new_mem->mem_type) { 274 switch (new_mem->mem_type) {
275 case TTM_PL_VRAM: 275 case TTM_PL_VRAM:
276 new_start += rdev->mc.vram_location; 276 new_start += rdev->mc.vram_start;
277 break; 277 break;
278 case TTM_PL_TT: 278 case TTM_PL_TT:
279 new_start += rdev->mc.gtt_location; 279 new_start += rdev->mc.gtt_start;
280 break; 280 break;
281 default: 281 default:
282 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 282 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);