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authorAlex Deucher <alexdeucher@gmail.com>2009-11-23 17:39:28 -0500
committerDave Airlie <airlied@redhat.com>2009-12-07 19:22:41 -0500
commit6a93cb250a60af1bb7b4070949f8546a2fdc52ef (patch)
tree2c734dcc0a4c39ec5c626b17912845eae1448828 /drivers/gpu/drm/radeon/radeon_reg.h
parent1a66c95a64c9ae0bc8382254f544b24b23f498ec (diff)
drm/radeon/kms: i2c reorg
- keep the atom i2c id in the i2c rec - fix gpio regs for GPIO and MDGPIO on pre-avivo chips - track whether the i2c line is hw capable - track whether the i2c line uses the multimedia i2c block Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_reg.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index c4c41c8d908c..b8116401ffae 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -1148,16 +1148,16 @@
1148# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) 1148# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
1149# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) 1149# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
1150# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) 1150# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
1151
1151#define RADEON_GPIOPAD_MASK 0x0198 1152#define RADEON_GPIOPAD_MASK 0x0198
1152#define RADEON_GPIOPAD_A 0x019c 1153#define RADEON_GPIOPAD_A 0x019c
1153#define RADEON_GPIOPAD_EN 0x01a0 1154#define RADEON_GPIOPAD_EN 0x01a0
1154#define RADEON_GPIOPAD_Y 0x01a4 1155#define RADEON_GPIOPAD_Y 0x01a4
1155#define RADEON_LCD_GPIO_MASK 0x01a0 1156#define RADEON_MDGPIO_MASK 0x01a8
1156#define RADEON_LCD_GPIO_Y_REG 0x01a4 1157#define RADEON_MDGPIO_A 0x01ac
1157#define RADEON_MDGPIO_A_REG 0x01ac 1158#define RADEON_MDGPIO_EN 0x01b0
1158#define RADEON_MDGPIO_EN_REG 0x01b0 1159#define RADEON_MDGPIO_Y 0x01b4
1159#define RADEON_MDGPIO_MASK 0x0198 1160
1160#define RADEON_MDGPIO_Y_REG 0x01b4
1161#define RADEON_MEM_ADDR_CONFIG 0x0148 1161#define RADEON_MEM_ADDR_CONFIG 0x0148
1162#define RADEON_MEM_BASE 0x0f10 /* PCI */ 1162#define RADEON_MEM_BASE 0x0f10 /* PCI */
1163#define RADEON_MEM_CNTL 0x0140 1163#define RADEON_MEM_CNTL 0x0140