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author | Tejun Heo <tj@kernel.org> | 2010-04-04 22:37:28 -0400 |
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committer | Tejun Heo <tj@kernel.org> | 2010-04-04 22:37:28 -0400 |
commit | 336f5899d287f06d8329e208fc14ce50f7ec9698 (patch) | |
tree | 9b762d450d5eb248a6ff8317badb7e223d93ed58 /drivers/gpu/drm/radeon/radeon_reg.h | |
parent | a4ab2773205e8b94c18625455f85e3b6bb9d7ad6 (diff) | |
parent | db217dece3003df0841bacf9556b5c06aa097dae (diff) |
Merge branch 'master' into export-slabh
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_reg.h')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 5c0dc082d330..eabbc9cf30a7 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h | |||
@@ -346,6 +346,7 @@ | |||
346 | # define RADEON_TVPLL_PWRMGT_OFF (1 << 30) | 346 | # define RADEON_TVPLL_PWRMGT_OFF (1 << 30) |
347 | # define RADEON_TVCLK_TURNOFF (1 << 31) | 347 | # define RADEON_TVCLK_TURNOFF (1 << 31) |
348 | #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ | 348 | #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ |
349 | # define RADEON_PM_MODE_SEL (1 << 13) | ||
349 | # define RADEON_TCL_BYPASS_DISABLE (1 << 20) | 350 | # define RADEON_TCL_BYPASS_DISABLE (1 << 20) |
350 | #define RADEON_CLR_CMP_CLR_3D 0x1a24 | 351 | #define RADEON_CLR_CMP_CLR_3D 0x1a24 |
351 | #define RADEON_CLR_CMP_CLR_DST 0x15c8 | 352 | #define RADEON_CLR_CMP_CLR_DST 0x15c8 |