diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2010-01-19 17:16:10 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-01-24 02:24:23 -0500 |
commit | fc10332b8ac5ca32d11f898027d84c007543bd80 (patch) | |
tree | 28b24fb83e4c4bfc71286ce93f01271fa5027c95 /drivers/gpu/drm/radeon/radeon_mode.h | |
parent | a348c84d953f61c776e53cde0a63a4e407a23c18 (diff) |
drm/radeon/kms: clean up pll struct
- add a new flag for fixed post div
- pull the pll flags into the struct
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_mode.h | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index eb19b3022b0e..96b851f92f4c 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h | |||
@@ -125,16 +125,24 @@ struct radeon_tmds_pll { | |||
125 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) | 125 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
126 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) | 126 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
127 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) | 127 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
128 | #define RADEON_PLL_USE_POST_DIV (1 << 12) | ||
128 | 129 | ||
129 | struct radeon_pll { | 130 | struct radeon_pll { |
130 | uint16_t reference_freq; | 131 | /* reference frequency */ |
131 | uint16_t reference_div; | 132 | uint32_t reference_freq; |
133 | |||
134 | /* fixed dividers */ | ||
135 | uint32_t reference_div; | ||
136 | uint32_t post_div; | ||
137 | |||
138 | /* pll in/out limits */ | ||
132 | uint32_t pll_in_min; | 139 | uint32_t pll_in_min; |
133 | uint32_t pll_in_max; | 140 | uint32_t pll_in_max; |
134 | uint32_t pll_out_min; | 141 | uint32_t pll_out_min; |
135 | uint32_t pll_out_max; | 142 | uint32_t pll_out_max; |
136 | uint16_t xclk; | 143 | uint32_t best_vco; |
137 | 144 | ||
145 | /* divider limits */ | ||
138 | uint32_t min_ref_div; | 146 | uint32_t min_ref_div; |
139 | uint32_t max_ref_div; | 147 | uint32_t max_ref_div; |
140 | uint32_t min_post_div; | 148 | uint32_t min_post_div; |
@@ -143,7 +151,12 @@ struct radeon_pll { | |||
143 | uint32_t max_feedback_div; | 151 | uint32_t max_feedback_div; |
144 | uint32_t min_frac_feedback_div; | 152 | uint32_t min_frac_feedback_div; |
145 | uint32_t max_frac_feedback_div; | 153 | uint32_t max_frac_feedback_div; |
146 | uint32_t best_vco; | 154 | |
155 | /* flags for the current clock */ | ||
156 | uint32_t flags; | ||
157 | |||
158 | /* pll id */ | ||
159 | uint32_t id; | ||
147 | }; | 160 | }; |
148 | 161 | ||
149 | struct radeon_i2c_chan { | 162 | struct radeon_i2c_chan { |
@@ -417,8 +430,7 @@ extern void radeon_compute_pll(struct radeon_pll *pll, | |||
417 | uint32_t *fb_div_p, | 430 | uint32_t *fb_div_p, |
418 | uint32_t *frac_fb_div_p, | 431 | uint32_t *frac_fb_div_p, |
419 | uint32_t *ref_div_p, | 432 | uint32_t *ref_div_p, |
420 | uint32_t *post_div_p, | 433 | uint32_t *post_div_p); |
421 | int flags); | ||
422 | 434 | ||
423 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, | 435 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
424 | uint64_t freq, | 436 | uint64_t freq, |
@@ -426,8 +438,7 @@ extern void radeon_compute_pll_avivo(struct radeon_pll *pll, | |||
426 | uint32_t *fb_div_p, | 438 | uint32_t *fb_div_p, |
427 | uint32_t *frac_fb_div_p, | 439 | uint32_t *frac_fb_div_p, |
428 | uint32_t *ref_div_p, | 440 | uint32_t *ref_div_p, |
429 | uint32_t *post_div_p, | 441 | uint32_t *post_div_p); |
430 | int flags); | ||
431 | 442 | ||
432 | extern void radeon_setup_encoder_clones(struct drm_device *dev); | 443 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
433 | 444 | ||