aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/radeon_mode.h
diff options
context:
space:
mode:
authorAlex Deucher <alexdeucher@gmail.com>2009-11-10 15:59:44 -0500
committerDave Airlie <airlied@redhat.com>2009-12-01 20:36:39 -0500
commit9b9fe72488a3a637e0550cc888e3f7a8f70e521e (patch)
tree5739a07ba9a57c58174f79a065e547e92aafe3df /drivers/gpu/drm/radeon/radeon_mode.h
parentab1e9ea08f1e94639b2d21a6bde5b55d31b1deee (diff)
drm/radeon/kms: clean up i2c
- Change reg/mask names to match what we use internally and in the bios - Clarify how i2c over gpio on radeon actually works Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h30
1 files changed, 22 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 491a1ec81a4c..20847a2fc4dc 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -89,24 +89,38 @@ enum radeon_tv_std {
89 TV_STD_PAL_CN, 89 TV_STD_PAL_CN,
90}; 90};
91 91
92/* radeon gpio-based i2c
93 * 1. "mask" reg and bits
94 * grabs the gpio pins for software use
95 * 0=not held 1=held
96 * 2. "a" reg and bits
97 * output pin value
98 * 0=low 1=high
99 * 3. "en" reg and bits
100 * sets the pin direction
101 * 0=input 1=output
102 * 4. "y" reg and bits
103 * input pin value
104 * 0=low 1=high
105 */
92struct radeon_i2c_bus_rec { 106struct radeon_i2c_bus_rec {
93 bool valid; 107 bool valid;
94 uint32_t mask_clk_reg; 108 uint32_t mask_clk_reg;
95 uint32_t mask_data_reg; 109 uint32_t mask_data_reg;
96 uint32_t a_clk_reg; 110 uint32_t a_clk_reg;
97 uint32_t a_data_reg; 111 uint32_t a_data_reg;
98 uint32_t put_clk_reg; 112 uint32_t en_clk_reg;
99 uint32_t put_data_reg; 113 uint32_t en_data_reg;
100 uint32_t get_clk_reg; 114 uint32_t y_clk_reg;
101 uint32_t get_data_reg; 115 uint32_t y_data_reg;
102 uint32_t mask_clk_mask; 116 uint32_t mask_clk_mask;
103 uint32_t mask_data_mask; 117 uint32_t mask_data_mask;
104 uint32_t put_clk_mask;
105 uint32_t put_data_mask;
106 uint32_t get_clk_mask;
107 uint32_t get_data_mask;
108 uint32_t a_clk_mask; 118 uint32_t a_clk_mask;
109 uint32_t a_data_mask; 119 uint32_t a_data_mask;
120 uint32_t en_clk_mask;
121 uint32_t en_data_mask;
122 uint32_t y_clk_mask;
123 uint32_t y_data_mask;
110}; 124};
111 125
112struct radeon_tmds_pll { 126struct radeon_tmds_pll {