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author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-11-11 14:32:04 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-11-11 14:32:04 -0500 |
commit | 6b46362c0ea472b174c336786fd406c504326ad4 (patch) | |
tree | f403d941d88ea9e2ee59ec977cb4d6c7b782018d /drivers/gpu/drm/radeon/radeon_gart.c | |
parent | 961767b75d63c21aa60ee3ccf940288c3c1afde6 (diff) | |
parent | eeba57518c01cf462d87bbfc59049139da47adcb (diff) |
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (52 commits)
drm/kms: Init the CRTC info fields for modes forced from the command line.
drm/radeon/r600: CS parser updates
drm/radeon/kms: add debugfs for power management for AtomBIOS devices
drm/radeon/kms: initial mode validation support
drm/radeon/kms/atom/dce3: call transmitter init on mode set
drm/radeon/kms: store detailed connector info
drm/radeon/kms/atom/dce3: fix up usPixelClock calculation for Transmitter tables
drm/radeon/kms/r600: fix rs880 support v2
drm/radeon/kms/r700: fix some typos in chip init
drm/radeon/kms: remove some misleading debugging output
drm/radeon/kms: stop putting VRAM at 0 in MC space on r600s.
drm/radeon/kms: disable D1VGA and D2VGA if enabled
drm/radeon/kms: Don't RMW CP_RB_CNTL
drm/radeon/kms: fix coherency issues on AGP cards.
drm/radeon/kms: fix rc410 suspend/resume.
drm/radeon/kms: add quirk for hp dc5750
drm/radeon/kms/atom: fix potential oops in spread spectrum code
drm/kms: typo fix
drm/radeon/kms/atom: Make card_info per device
drm/radeon/kms/atom: Fix DVO support
...
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_gart.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_gart.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c index a931af065dd4..a68d7566178c 100644 --- a/drivers/gpu/drm/radeon/radeon_gart.c +++ b/drivers/gpu/drm/radeon/radeon_gart.c | |||
@@ -140,15 +140,15 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |||
140 | WARN(1, "trying to unbind memory to unitialized GART !\n"); | 140 | WARN(1, "trying to unbind memory to unitialized GART !\n"); |
141 | return; | 141 | return; |
142 | } | 142 | } |
143 | t = offset / 4096; | 143 | t = offset / RADEON_GPU_PAGE_SIZE; |
144 | p = t / (PAGE_SIZE / 4096); | 144 | p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); |
145 | for (i = 0; i < pages; i++, p++) { | 145 | for (i = 0; i < pages; i++, p++) { |
146 | if (rdev->gart.pages[p]) { | 146 | if (rdev->gart.pages[p]) { |
147 | pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p], | 147 | pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p], |
148 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | 148 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
149 | rdev->gart.pages[p] = NULL; | 149 | rdev->gart.pages[p] = NULL; |
150 | rdev->gart.pages_addr[p] = 0; | 150 | rdev->gart.pages_addr[p] = 0; |
151 | for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) { | 151 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
152 | radeon_gart_set_page(rdev, t, 0); | 152 | radeon_gart_set_page(rdev, t, 0); |
153 | } | 153 | } |
154 | } | 154 | } |
@@ -169,8 +169,8 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |||
169 | DRM_ERROR("trying to bind memory to unitialized GART !\n"); | 169 | DRM_ERROR("trying to bind memory to unitialized GART !\n"); |
170 | return -EINVAL; | 170 | return -EINVAL; |
171 | } | 171 | } |
172 | t = offset / 4096; | 172 | t = offset / RADEON_GPU_PAGE_SIZE; |
173 | p = t / (PAGE_SIZE / 4096); | 173 | p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); |
174 | 174 | ||
175 | for (i = 0; i < pages; i++, p++) { | 175 | for (i = 0; i < pages; i++, p++) { |
176 | /* we need to support large memory configurations */ | 176 | /* we need to support large memory configurations */ |
@@ -185,9 +185,9 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |||
185 | } | 185 | } |
186 | rdev->gart.pages[p] = pagelist[i]; | 186 | rdev->gart.pages[p] = pagelist[i]; |
187 | page_base = rdev->gart.pages_addr[p]; | 187 | page_base = rdev->gart.pages_addr[p]; |
188 | for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) { | 188 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
189 | radeon_gart_set_page(rdev, t, page_base); | 189 | radeon_gart_set_page(rdev, t, page_base); |
190 | page_base += 4096; | 190 | page_base += RADEON_GPU_PAGE_SIZE; |
191 | } | 191 | } |
192 | } | 192 | } |
193 | mb(); | 193 | mb(); |
@@ -200,14 +200,14 @@ int radeon_gart_init(struct radeon_device *rdev) | |||
200 | if (rdev->gart.pages) { | 200 | if (rdev->gart.pages) { |
201 | return 0; | 201 | return 0; |
202 | } | 202 | } |
203 | /* We need PAGE_SIZE >= 4096 */ | 203 | /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */ |
204 | if (PAGE_SIZE < 4096) { | 204 | if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) { |
205 | DRM_ERROR("Page size is smaller than GPU page size!\n"); | 205 | DRM_ERROR("Page size is smaller than GPU page size!\n"); |
206 | return -EINVAL; | 206 | return -EINVAL; |
207 | } | 207 | } |
208 | /* Compute table size */ | 208 | /* Compute table size */ |
209 | rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; | 209 | rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; |
210 | rdev->gart.num_gpu_pages = rdev->mc.gtt_size / 4096; | 210 | rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE; |
211 | DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", | 211 | DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", |
212 | rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); | 212 | rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); |
213 | /* Allocate pages table */ | 213 | /* Allocate pages table */ |