drm/radeon: UVD bringup v8

Just everything needed to decode videos using UVD.

v6: just all the bugfixes and support for R7xx-SI merged in one patch
v7: UVD_CGC_GATE is a write only register, lockup detection fix
v8: split out VRAM fallback changes, remove support for RV770,
    add support for HEMLOCK, add buffer sizes checks

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 18 insertions, 5 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 34356252567a..82fe1835ff8c 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -31,9 +31,9 @@
 #include <linux/seq_file.h>
 #include <linux/atomic.h>
 #include <linux/wait.h>
-#include <linux/list.h>
 #include <linux/kref.h>
 #include <linux/slab.h>
+#include <linux/firmware.h>
 #include <drm/drmP.h>
 #include "radeon_reg.h"
 #include "radeon.h"
@@ -767,8 +767,21 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
 
         radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
         if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
-                rdev->fence_drv[ring].scratch_reg = 0;
-                index = R600_WB_EVENT_OFFSET + ring * 4;
+                if (ring != R600_RING_TYPE_UVD_INDEX) {
+                        rdev->fence_drv[ring].scratch_reg = 0;
+                        index = R600_WB_EVENT_OFFSET + ring * 4;
+                        rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
+                        rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
+                                                         index;
+
+                } else {
+                        /* put fence directly behind firmware */
+                        rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr +
+                                                         rdev->uvd_fw->size;
+                        rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr +
+                                                         rdev->uvd_fw->size;
+                }
+
         } else {
                 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
                 if (r) {
@@ -778,9 +791,9 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
                 index = RADEON_WB_SCRATCH_OFFSET +
                         rdev->fence_drv[ring].scratch_reg -
                         rdev->scratch.reg_base;
+                rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
+                rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
         }
-        rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
-        rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
         radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
         rdev->fence_drv[ring].initialized = true;
         dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",