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authorJerome Glisse <jglisse@redhat.com>2010-04-26 16:23:42 -0400
committerDave Airlie <airlied@redhat.com>2010-04-26 19:48:16 -0400
commita1e9ada3e148dc300fdd25705bd3ac024897dc68 (patch)
tree3cd724dc3b385553f228dcd310c10b6f32f23ec6 /drivers/gpu/drm/radeon/radeon_fence.c
parentf2594933df9719bd2b0aaaa8ea9b2b850d6e1c42 (diff)
drm/radeon/kms: R3XX-R4XX fix GPU reset code
Previous reset code leaded to computer hard lockup (need to unplug the power too reboot the computer) on various configuration. This patch change the reset code to avoid hard lockup. The GPU reset is failing most of the time but at least user can log in remotely or properly shutdown the computer. Two issues were leading to hard lockup : - Writting to the scratch register lead to hard lockup most likely because the write back mecanism is in fuzy state after GPU lockup. - Resetting the GPU memory controller and not reinitializing it after leaded to hard lockup. We did only reinitialize in case of successfull reset thus unsuccessfull reset quickly leaded to hard lockup. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_fence.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 1b8b9cc271f2..b1f9a81b5d1d 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -237,10 +237,10 @@ retry:
237 * as signaled for now 237 * as signaled for now
238 */ 238 */
239 rdev->gpu_lockup = true; 239 rdev->gpu_lockup = true;
240 WREG32(rdev->fence_drv.scratch_reg, fence->seq);
241 r = radeon_gpu_reset(rdev); 240 r = radeon_gpu_reset(rdev);
242 if (r) 241 if (r)
243 return r; 242 return r;
243 WREG32(rdev->fence_drv.scratch_reg, fence->seq);
244 rdev->gpu_lockup = false; 244 rdev->gpu_lockup = false;
245 } 245 }
246 timeout = RADEON_FENCE_JIFFIES_TIMEOUT; 246 timeout = RADEON_FENCE_JIFFIES_TIMEOUT;