diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2011-05-20 04:34:15 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-05-20 06:02:20 -0400 |
commit | df271bec805b42527d864777ed035fcbb42e76c0 (patch) | |
tree | f0147418442af534bab26040b5aa45ec009cf666 /drivers/gpu/drm/radeon/radeon_encoders.c | |
parent | 96b3bef8c1d20b3f0087a26313296bf476930380 (diff) |
drm/radeon/kms: properly handle bpc >8 in atom command tables
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_encoders.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_encoders.c | 70 |
1 files changed, 67 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index b2e0b586e784..6c6793e6e3a5 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c | |||
@@ -760,6 +760,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |||
760 | int dp_clock = 0; | 760 | int dp_clock = 0; |
761 | int dp_lane_count = 0; | 761 | int dp_lane_count = 0; |
762 | int hpd_id = RADEON_HPD_NONE; | 762 | int hpd_id = RADEON_HPD_NONE; |
763 | int bpc = 8; | ||
763 | 764 | ||
764 | if (connector) { | 765 | if (connector) { |
765 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 766 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
@@ -769,6 +770,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |||
769 | dp_clock = dig_connector->dp_clock; | 770 | dp_clock = dig_connector->dp_clock; |
770 | dp_lane_count = dig_connector->dp_lane_count; | 771 | dp_lane_count = dig_connector->dp_lane_count; |
771 | hpd_id = radeon_connector->hpd.hpd; | 772 | hpd_id = radeon_connector->hpd.hpd; |
773 | bpc = connector->display_info.bpc; | ||
772 | } | 774 | } |
773 | 775 | ||
774 | /* no dig encoder assigned */ | 776 | /* no dig encoder assigned */ |
@@ -810,7 +812,27 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |||
810 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; | 812 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
811 | } | 813 | } |
812 | args.v4.acConfig.ucDigSel = dig->dig_encoder; | 814 | args.v4.acConfig.ucDigSel = dig->dig_encoder; |
813 | args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; | 815 | switch (bpc) { |
816 | case 0: | ||
817 | args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE; | ||
818 | break; | ||
819 | case 6: | ||
820 | args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR; | ||
821 | break; | ||
822 | case 8: | ||
823 | default: | ||
824 | args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; | ||
825 | break; | ||
826 | case 10: | ||
827 | args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR; | ||
828 | break; | ||
829 | case 12: | ||
830 | args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR; | ||
831 | break; | ||
832 | case 16: | ||
833 | args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR; | ||
834 | break; | ||
835 | } | ||
814 | if (hpd_id == RADEON_HPD_NONE) | 836 | if (hpd_id == RADEON_HPD_NONE) |
815 | args.v4.ucHPD_ID = 0; | 837 | args.v4.ucHPD_ID = 0; |
816 | else | 838 | else |
@@ -819,7 +841,27 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) | |||
819 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) | 841 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) |
820 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; | 842 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; |
821 | args.v3.acConfig.ucDigSel = dig->dig_encoder; | 843 | args.v3.acConfig.ucDigSel = dig->dig_encoder; |
822 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; | 844 | switch (bpc) { |
845 | case 0: | ||
846 | args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE; | ||
847 | break; | ||
848 | case 6: | ||
849 | args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR; | ||
850 | break; | ||
851 | case 8: | ||
852 | default: | ||
853 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; | ||
854 | break; | ||
855 | case 10: | ||
856 | args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR; | ||
857 | break; | ||
858 | case 12: | ||
859 | args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR; | ||
860 | break; | ||
861 | case 16: | ||
862 | args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR; | ||
863 | break; | ||
864 | } | ||
823 | } else { | 865 | } else { |
824 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) | 866 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) |
825 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | 867 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; |
@@ -1099,6 +1141,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, | |||
1099 | int dp_lane_count = 0; | 1141 | int dp_lane_count = 0; |
1100 | int connector_object_id = 0; | 1142 | int connector_object_id = 0; |
1101 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; | 1143 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
1144 | int bpc = 8; | ||
1102 | 1145 | ||
1103 | if (connector) { | 1146 | if (connector) { |
1104 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 1147 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
@@ -1109,6 +1152,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, | |||
1109 | dp_lane_count = dig_connector->dp_lane_count; | 1152 | dp_lane_count = dig_connector->dp_lane_count; |
1110 | connector_object_id = | 1153 | connector_object_id = |
1111 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | 1154 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
1155 | bpc = connector->display_info.bpc; | ||
1112 | } | 1156 | } |
1113 | 1157 | ||
1114 | memset(&args, 0, sizeof(args)); | 1158 | memset(&args, 0, sizeof(args)); |
@@ -1166,7 +1210,27 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, | |||
1166 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; | 1210 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; |
1167 | break; | 1211 | break; |
1168 | } | 1212 | } |
1169 | args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; | 1213 | switch (bpc) { |
1214 | case 0: | ||
1215 | args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE; | ||
1216 | break; | ||
1217 | case 6: | ||
1218 | args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR; | ||
1219 | break; | ||
1220 | case 8: | ||
1221 | default: | ||
1222 | args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; | ||
1223 | break; | ||
1224 | case 10: | ||
1225 | args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR; | ||
1226 | break; | ||
1227 | case 12: | ||
1228 | args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR; | ||
1229 | break; | ||
1230 | case 16: | ||
1231 | args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR; | ||
1232 | break; | ||
1233 | } | ||
1170 | break; | 1234 | break; |
1171 | default: | 1235 | default: |
1172 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | 1236 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |