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authorAlex Deucher <alexander.deucher@amd.com>2011-10-26 15:59:50 -0400
committerDave Airlie <airlied@redhat.com>2011-11-01 12:04:57 -0400
commit996d5c59006cd970dd3a9007aa1f76532909bae2 (patch)
treed7b7fd7a900c042b9d1c48bf1f13c86d03cccf46 /drivers/gpu/drm/radeon/radeon_encoders.c
parentc41384f8279f6eeecfe186976f67c2a513f3c81b (diff)
drm/radeon/kms: check for DP MST mode in a few more places (v2)
DP MST is DP multi-stream support, part of DP 1.2. v2: switch to a helper macro as suggested by Michel. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_encoders.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c20
1 files changed, 9 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index f01b6b135b99..e57fd6dab4ba 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -834,8 +834,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
834 else 834 else
835 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 835 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
836 836
837 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || 837 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
838 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
839 args.v1.ucLaneNum = dp_lane_count; 838 args.v1.ucLaneNum = dp_lane_count;
840 else if (radeon_encoder->pixel_clock > 165000) 839 else if (radeon_encoder->pixel_clock > 165000)
841 args.v1.ucLaneNum = 8; 840 args.v1.ucLaneNum = 8;
@@ -843,8 +842,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
843 args.v1.ucLaneNum = 4; 842 args.v1.ucLaneNum = 4;
844 843
845 if (ASIC_IS_DCE5(rdev)) { 844 if (ASIC_IS_DCE5(rdev)) {
846 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || 845 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
847 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
848 if (dp_clock == 270000) 846 if (dp_clock == 270000)
849 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 847 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
850 else if (dp_clock == 540000) 848 else if (dp_clock == 540000)
@@ -877,7 +875,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
877 else 875 else
878 args.v4.ucHPD_ID = hpd_id + 1; 876 args.v4.ucHPD_ID = hpd_id + 1;
879 } else if (ASIC_IS_DCE4(rdev)) { 877 } else if (ASIC_IS_DCE4(rdev)) {
880 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) 878 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
881 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 879 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
882 args.v3.acConfig.ucDigSel = dig->dig_encoder; 880 args.v3.acConfig.ucDigSel = dig->dig_encoder;
883 switch (bpc) { 881 switch (bpc) {
@@ -902,7 +900,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
902 break; 900 break;
903 } 901 }
904 } else { 902 } else {
905 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) 903 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
906 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 904 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
907 switch (radeon_encoder->encoder_id) { 905 switch (radeon_encoder->encoder_id) {
908 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 906 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
@@ -977,7 +975,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
977 if (dig_encoder == -1) 975 if (dig_encoder == -1)
978 return; 976 return;
979 977
980 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) 978 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
981 is_dp = true; 979 is_dp = true;
982 980
983 memset(&args, 0, sizeof(args)); 981 memset(&args, 0, sizeof(args));
@@ -1246,7 +1244,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
1246 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1244 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1247 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1245 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1248 1246
1249 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { 1247 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1250 if (dp_clock == 270000) 1248 if (dp_clock == 270000)
1251 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1249 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1252 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1250 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
@@ -1263,7 +1261,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
1263 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1261 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1264 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1262 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1265 1263
1266 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { 1264 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1267 if (dp_clock == 270000) 1265 if (dp_clock == 270000)
1268 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1266 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1269 else if (dp_clock == 540000) 1267 else if (dp_clock == 540000)
@@ -1458,7 +1456,7 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1458 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1456 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1459 else 1457 else
1460 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1458 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1461 if ((atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) && connector) { 1459 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1462 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1460 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1463 atombios_set_edp_panel_power(connector, 1461 atombios_set_edp_panel_power(connector,
1464 ATOM_TRANSMITTER_ACTION_POWER_ON); 1462 ATOM_TRANSMITTER_ACTION_POWER_ON);
@@ -1477,7 +1475,7 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1477 case DRM_MODE_DPMS_SUSPEND: 1475 case DRM_MODE_DPMS_SUSPEND:
1478 case DRM_MODE_DPMS_OFF: 1476 case DRM_MODE_DPMS_OFF:
1479 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1477 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1480 if ((atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) && connector) { 1478 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1481 if (ASIC_IS_DCE4(rdev)) 1479 if (ASIC_IS_DCE4(rdev))
1482 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1480 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1483 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1481 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {