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authorJerome Glisse <jglisse@redhat.com>2009-09-07 20:10:24 -0400
committerDave Airlie <airlied@redhat.com>2009-09-07 21:15:52 -0400
commit3ce0a23d2d253185df24e22e3d5f89800bb3dd1c (patch)
tree4b4defdbe33aec7317101cce0f89c33083f8d17b /drivers/gpu/drm/radeon/radeon_drv.h
parent4ce001abafafe77e5dd943d1480fc9f87894e96f (diff)
drm/radeon/kms: add r600 KMS support
This adds the r600 KMS + CS support to the Linux kernel. The r600 TTM support is quite basic and still needs more work esp around using interrupts, but the polled fencing should work okay for now. Also currently TTM is using memcpy to do VRAM moves, the code is here to use a 3D blit to do this, but isn't fully debugged yet. Authors: Alex Deucher <alexdeucher@gmail.com> Dave Airlie <airlied@redhat.com> Jerome Glisse <jglisse@redhat.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_drv.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h141
1 files changed, 135 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 40294a07976f..c7b185924f6c 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -356,6 +356,12 @@ typedef struct drm_radeon_private {
356 int r700_sc_hiz_tile_fifo_size; 356 int r700_sc_hiz_tile_fifo_size;
357 int r700_sc_earlyz_tile_fifo_fize; 357 int r700_sc_earlyz_tile_fifo_fize;
358 358
359 struct mutex cs_mutex;
360 u32 cs_id_scnt;
361 u32 cs_id_wcnt;
362 /* r6xx/r7xx drm blit vertex buffer */
363 struct drm_buf *blit_vb;
364
359 /* firmware */ 365 /* firmware */
360 const struct firmware *me_fw, *pfp_fw; 366 const struct firmware *me_fw, *pfp_fw;
361} drm_radeon_private_t; 367} drm_radeon_private_t;
@@ -396,6 +402,9 @@ static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
396 (off >= gart_start && off <= gart_end)); 402 (off >= gart_start && off <= gart_end));
397} 403}
398 404
405/* radeon_state.c */
406extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf);
407
399 /* radeon_cp.c */ 408 /* radeon_cp.c */
400extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 409extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
401extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 410extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
@@ -487,6 +496,22 @@ extern int r600_cp_dispatch_indirect(struct drm_device *dev,
487 struct drm_buf *buf, int start, int end); 496 struct drm_buf *buf, int start, int end);
488extern int r600_page_table_init(struct drm_device *dev); 497extern int r600_page_table_init(struct drm_device *dev);
489extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); 498extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
499extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
500extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv);
501extern int r600_cp_dispatch_texture(struct drm_device *dev,
502 struct drm_file *file_priv,
503 drm_radeon_texture_t *tex,
504 drm_radeon_tex_image_t *image);
505/* r600_blit.c */
506extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv);
507extern void r600_done_blit_copy(struct drm_device *dev);
508extern void r600_blit_copy(struct drm_device *dev,
509 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
510 int size_bytes);
511extern void r600_blit_swap(struct drm_device *dev,
512 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
513 int sx, int sy, int dx, int dy,
514 int w, int h, int src_pitch, int dst_pitch, int cpp);
490 515
491/* Flags for stats.boxes 516/* Flags for stats.boxes
492 */ 517 */
@@ -1114,13 +1139,71 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
1114# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1139# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1115# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1140# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1116 1141
1117# define R600_IT_INDIRECT_BUFFER 0x00003200 1142# define R600_IT_INDIRECT_BUFFER_END 0x00001700
1118# define R600_IT_ME_INITIALIZE 0x00004400 1143# define R600_IT_SET_PREDICATION 0x00002000
1144# define R600_IT_REG_RMW 0x00002100
1145# define R600_IT_COND_EXEC 0x00002200
1146# define R600_IT_PRED_EXEC 0x00002300
1147# define R600_IT_START_3D_CMDBUF 0x00002400
1148# define R600_IT_DRAW_INDEX_2 0x00002700
1149# define R600_IT_CONTEXT_CONTROL 0x00002800
1150# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900
1151# define R600_IT_INDEX_TYPE 0x00002A00
1152# define R600_IT_DRAW_INDEX 0x00002B00
1153# define R600_IT_DRAW_INDEX_AUTO 0x00002D00
1154# define R600_IT_DRAW_INDEX_IMMD 0x00002E00
1155# define R600_IT_NUM_INSTANCES 0x00002F00
1156# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400
1157# define R600_IT_INDIRECT_BUFFER_MP 0x00003800
1158# define R600_IT_MEM_SEMAPHORE 0x00003900
1159# define R600_IT_MPEG_INDEX 0x00003A00
1160# define R600_IT_WAIT_REG_MEM 0x00003C00
1161# define R600_IT_MEM_WRITE 0x00003D00
1162# define R600_IT_INDIRECT_BUFFER 0x00003200
1163# define R600_IT_CP_INTERRUPT 0x00004000
1164# define R600_IT_SURFACE_SYNC 0x00004300
1165# define R600_CB0_DEST_BASE_ENA (1 << 6)
1166# define R600_TC_ACTION_ENA (1 << 23)
1167# define R600_VC_ACTION_ENA (1 << 24)
1168# define R600_CB_ACTION_ENA (1 << 25)
1169# define R600_DB_ACTION_ENA (1 << 26)
1170# define R600_SH_ACTION_ENA (1 << 27)
1171# define R600_SMX_ACTION_ENA (1 << 28)
1172# define R600_IT_ME_INITIALIZE 0x00004400
1119# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1173# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1120# define R600_IT_EVENT_WRITE 0x00004600 1174# define R600_IT_COND_WRITE 0x00004500
1121# define R600_IT_SET_CONFIG_REG 0x00006800 1175# define R600_IT_EVENT_WRITE 0x00004600
1122# define R600_SET_CONFIG_REG_OFFSET 0x00008000 1176# define R600_IT_EVENT_WRITE_EOP 0x00004700
1123# define R600_SET_CONFIG_REG_END 0x0000ac00 1177# define R600_IT_ONE_REG_WRITE 0x00005700
1178# define R600_IT_SET_CONFIG_REG 0x00006800
1179# define R600_SET_CONFIG_REG_OFFSET 0x00008000
1180# define R600_SET_CONFIG_REG_END 0x0000ac00
1181# define R600_IT_SET_CONTEXT_REG 0x00006900
1182# define R600_SET_CONTEXT_REG_OFFSET 0x00028000
1183# define R600_SET_CONTEXT_REG_END 0x00029000
1184# define R600_IT_SET_ALU_CONST 0x00006A00
1185# define R600_SET_ALU_CONST_OFFSET 0x00030000
1186# define R600_SET_ALU_CONST_END 0x00032000
1187# define R600_IT_SET_BOOL_CONST 0x00006B00
1188# define R600_SET_BOOL_CONST_OFFSET 0x0003e380
1189# define R600_SET_BOOL_CONST_END 0x00040000
1190# define R600_IT_SET_LOOP_CONST 0x00006C00
1191# define R600_SET_LOOP_CONST_OFFSET 0x0003e200
1192# define R600_SET_LOOP_CONST_END 0x0003e380
1193# define R600_IT_SET_RESOURCE 0x00006D00
1194# define R600_SET_RESOURCE_OFFSET 0x00038000
1195# define R600_SET_RESOURCE_END 0x0003c000
1196# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0
1197# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1
1198# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2
1199# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3
1200# define R600_IT_SET_SAMPLER 0x00006E00
1201# define R600_SET_SAMPLER_OFFSET 0x0003c000
1202# define R600_SET_SAMPLER_END 0x0003cff0
1203# define R600_IT_SET_CTL_CONST 0x00006F00
1204# define R600_SET_CTL_CONST_OFFSET 0x0003cff0
1205# define R600_SET_CTL_CONST_END 0x0003e200
1206# define R600_IT_SURFACE_BASE_UPDATE 0x00007300
1124 1207
1125#define RADEON_CP_PACKET_MASK 0xC0000000 1208#define RADEON_CP_PACKET_MASK 0xC0000000
1126#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1209#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
@@ -1598,6 +1681,52 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
1598#define R600_CB_COLOR7_BASE 0x2805c 1681#define R600_CB_COLOR7_BASE 0x2805c
1599#define R600_CB_COLOR7_FRAG 0x280fc 1682#define R600_CB_COLOR7_FRAG 0x280fc
1600 1683
1684#define R600_CB_COLOR0_SIZE 0x28060
1685#define R600_CB_COLOR0_VIEW 0x28080
1686#define R600_CB_COLOR0_INFO 0x280a0
1687#define R600_CB_COLOR0_TILE 0x280c0
1688#define R600_CB_COLOR0_FRAG 0x280e0
1689#define R600_CB_COLOR0_MASK 0x28100
1690
1691#define AVIVO_D1MODE_VLINE_START_END 0x6538
1692#define AVIVO_D2MODE_VLINE_START_END 0x6d38
1693#define R600_CP_COHER_BASE 0x85f8
1694#define R600_DB_DEPTH_BASE 0x2800c
1695#define R600_SQ_PGM_START_FS 0x28894
1696#define R600_SQ_PGM_START_ES 0x28880
1697#define R600_SQ_PGM_START_VS 0x28858
1698#define R600_SQ_PGM_RESOURCES_VS 0x28868
1699#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0
1700#define R600_SQ_PGM_START_GS 0x2886c
1701#define R600_SQ_PGM_START_PS 0x28840
1702#define R600_SQ_PGM_RESOURCES_PS 0x28850
1703#define R600_SQ_PGM_EXPORTS_PS 0x28854
1704#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc
1705#define R600_VGT_DMA_BASE 0x287e8
1706#define R600_VGT_DMA_BASE_HI 0x287e4
1707#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10
1708#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14
1709#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18
1710#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c
1711#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44
1712#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48
1713#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c
1714#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50
1715#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8
1716#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8
1717#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8
1718#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08
1719#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc
1720#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec
1721#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc
1722#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c
1723
1724#define R600_VGT_PRIMITIVE_TYPE 0x8958
1725
1726#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030
1727#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240
1728#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204
1729
1601#define R600_TC_CNTL 0x9608 1730#define R600_TC_CNTL 0x9608
1602# define R600_TC_L2_SIZE(x) ((x) << 5) 1731# define R600_TC_L2_SIZE(x) ((x) << 5)
1603# define R600_L2_DISABLE_LATE_HIT (1 << 9) 1732# define R600_L2_DISABLE_LATE_HIT (1 << 9)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 09:01:25 -0500