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authorJerome Glisse <jglisse@redhat.com>2010-02-17 16:54:29 -0500
committerDave Airlie <airlied@redhat.com>2010-02-17 23:49:35 -0500
commitd594e46ace22afa1621254f6f669e65430048153 (patch)
treebefd5b54ce1b8284acc4ee450d085a7d2c7b01fd /drivers/gpu/drm/radeon/radeon_device.c
parent44ca7478d46aaad488d916f7262253e000ee60f9 (diff)
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the computation of vram_start|end & gtt_start|end. For R1XX-R2XX we place VRAM at the same address of PCI aperture, those GPU shouldn't have much memory and seems to behave better when setup that way. For R3XX and newer we place VRAM at 0. For R6XX-R7XX AGP we place VRAM before or after AGP aperture this might limit to limit the VRAM size but it's very unlikely. For IGP we don't change the VRAM placement. Tested on (compiz,quake3,suspend/resume): PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710 AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730 IGP:RS480(RPB*),RS690,RS780(RPB*),RS880 RPB: resume previously broken V2 correct commit message to reflect more accurately the bug and move VRAM placement to 0 for most of the GPU to avoid limiting VRAM. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_device.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c157
1 files changed, 90 insertions, 67 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 7be3a6968463..91a9b966238e 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -100,80 +100,103 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
100 } 100 }
101} 101}
102 102
103/* 103/**
104 * MC common functions 104 * radeon_vram_location - try to find VRAM location
105 * @rdev: radeon device structure holding all necessary informations
106 * @mc: memory controller structure holding memory informations
107 * @base: base address at which to put VRAM
108 *
109 * Function will place try to place VRAM at base address provided
110 * as parameter (which is so far either PCI aperture address or
111 * for IGP TOM base address).
112 *
113 * If there is not enough space to fit the unvisible VRAM in the 32bits
114 * address space then we limit the VRAM size to the aperture.
115 *
116 * If we are using AGP and if the AGP aperture doesn't allow us to have
117 * room for all the VRAM than we restrict the VRAM to the PCI aperture
118 * size and print a warning.
119 *
120 * This function will never fails, worst case are limiting VRAM.
121 *
122 * Note: GTT start, end, size should be initialized before calling this
123 * function on AGP platform.
124 *
125 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
126 * this shouldn't be a problem as we are using the PCI aperture as a reference.
127 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
128 * not IGP.
129 *
130 * Note: we use mc_vram_size as on some board we need to program the mc to
131 * cover the whole aperture even if VRAM size is inferior to aperture size
132 * Novell bug 204882 + along with lots of ubuntu ones
133 *
134 * Note: when limiting vram it's safe to overwritte real_vram_size because
135 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
136 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
137 * ones)
138 *
139 * Note: IGP TOM addr should be the same as the aperture addr, we don't
140 * explicitly check for that thought.
141 *
142 * FIXME: when reducing VRAM size align new size on power of 2.
105 */ 143 */
106int radeon_mc_setup(struct radeon_device *rdev) 144void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
145{
146 mc->vram_start = base;
147 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
148 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
149 mc->real_vram_size = mc->aper_size;
150 mc->mc_vram_size = mc->aper_size;
151 }
152 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
153 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) {
154 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
155 mc->real_vram_size = mc->aper_size;
156 mc->mc_vram_size = mc->aper_size;
157 }
158 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
159 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
160 mc->mc_vram_size >> 20, mc->vram_start,
161 mc->vram_end, mc->real_vram_size >> 20);
162}
163
164/**
165 * radeon_gtt_location - try to find GTT location
166 * @rdev: radeon device structure holding all necessary informations
167 * @mc: memory controller structure holding memory informations
168 *
169 * Function will place try to place GTT before or after VRAM.
170 *
171 * If GTT size is bigger than space left then we ajust GTT size.
172 * Thus function will never fails.
173 *
174 * FIXME: when reducing GTT size align new size on power of 2.
175 */
176void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
107{ 177{
108 uint32_t tmp; 178 u64 size_af, size_bf;
109 179
110 /* Some chips have an "issue" with the memory controller, the 180 size_af = 0xFFFFFFFF - mc->vram_end;
111 * location must be aligned to the size. We just align it down, 181 size_bf = mc->vram_start;
112 * too bad if we walk over the top of system memory, we don't 182 if (size_bf > size_af) {
113 * use DMA without a remapped anyway. 183 if (mc->gtt_size > size_bf) {
114 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP 184 dev_warn(rdev->dev, "limiting GTT\n");
115 */ 185 mc->gtt_size = size_bf;
116 /* FGLRX seems to setup like this, VRAM a 0, then GART.
117 */
118 /*
119 * Note: from R6xx the address space is 40bits but here we only
120 * use 32bits (still have to see a card which would exhaust 4G
121 * address space).
122 */
123 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
124 /* vram location was already setup try to put gtt after
125 * if it fits */
126 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
127 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
128 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
129 rdev->mc.gtt_location = tmp;
130 } else {
131 if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
132 printk(KERN_ERR "[drm] GTT too big to fit "
133 "before or after vram location.\n");
134 return -EINVAL;
135 }
136 rdev->mc.gtt_location = 0;
137 }
138 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
139 /* gtt location was already setup try to put vram before
140 * if it fits */
141 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
142 rdev->mc.vram_location = 0;
143 } else {
144 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
145 tmp += (rdev->mc.mc_vram_size - 1);
146 tmp &= ~(rdev->mc.mc_vram_size - 1);
147 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
148 rdev->mc.vram_location = tmp;
149 } else {
150 printk(KERN_ERR "[drm] vram too big to fit "
151 "before or after GTT location.\n");
152 return -EINVAL;
153 }
154 } 186 }
187 mc->gtt_start = mc->vram_start - mc->gtt_size;
155 } else { 188 } else {
156 rdev->mc.vram_location = 0; 189 if (mc->gtt_size > size_af) {
157 tmp = rdev->mc.mc_vram_size; 190 dev_warn(rdev->dev, "limiting GTT\n");
158 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); 191 mc->gtt_size = size_af;
159 rdev->mc.gtt_location = tmp; 192 }
160 } 193 mc->gtt_start = mc->vram_end + 1;
161 rdev->mc.vram_start = rdev->mc.vram_location; 194 }
162 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; 195 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
163 rdev->mc.gtt_start = rdev->mc.gtt_location; 196 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
164 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; 197 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
165 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
166 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
167 (unsigned)rdev->mc.vram_location,
168 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
169 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
170 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
171 (unsigned)rdev->mc.gtt_location,
172 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
173 return 0;
174} 198}
175 199
176
177/* 200/*
178 * GPU helpers function. 201 * GPU helpers function.
179 */ 202 */