drm/radeon: add helper function to support golden registers

Golden registers are arrays of register settings from the
hw team that need to be initialized at asic startup.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 36 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 62d0ba338582..237b7a7549e6 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -98,6 +98,42 @@ static const char radeon_family_name[][16] = {
 };
 
 /**
+ * radeon_program_register_sequence - program an array of registers.
+ *
+ * @rdev: radeon_device pointer
+ * @registers: pointer to the register array
+ * @array_size: size of the register array
+ *
+ * Programs an array or registers with and and or masks.
+ * This is a helper for setting golden registers.
+ */
+void radeon_program_register_sequence(struct radeon_device *rdev,
+                                      const u32 *registers,
+                                      const u32 array_size)
+{
+        u32 tmp, reg, and_mask, or_mask;
+        int i;
+
+        if (array_size % 3)
+                return;
+
+        for (i = 0; i < array_size; i +=3) {
+                reg = registers[i + 0];
+                and_mask = registers[i + 1];
+                or_mask = registers[i + 2];
+
+                if (and_mask == 0xffffffff) {
+                        tmp = or_mask;
+                } else {
+                        tmp = RREG32(reg);
+                        tmp &= ~and_mask;
+                        tmp |= or_mask;
+                }
+                WREG32(reg, tmp);
+        }
+}
+
+/**
  * radeon_surface_init - Clear GPU surface registers.
  *
  * @rdev: radeon_device pointer