aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/radeon_cp.c
diff options
context:
space:
mode:
authorAlex Deucher <alexdeucher@gmail.com>2009-02-25 16:57:49 -0500
committerDave Airlie <airlied@redhat.com>2009-03-13 00:24:13 -0400
commitc1556f71513f2e660fb2bbdc29344361b1ebff35 (patch)
treea7720f25bf130eb77475b6735fc522e151dcbf9d /drivers/gpu/drm/radeon/radeon_cp.c
parent7659e9804b7a66047433182d86393d38ba4eff79 (diff)
radeon: add support for rs600 GPUs
RS600s are an AMD IGP for Intel CPUs, that look like RS690s from a lot of perspectives but look like r600s from a memory controller point of view. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_cp.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c127
1 files changed, 123 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 596da014dfd9..15cfe56c7aaa 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -142,11 +142,22 @@ static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
142 return ret; 142 return ret;
143} 143}
144 144
145static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
146{
147 u32 ret;
148 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
149 RS600_MC_IND_CITF_ARB0));
150 ret = RADEON_READ(RS600_MC_DATA);
151 return ret;
152}
153
145static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 154static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
146{ 155{
147 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 156 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
148 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 157 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
149 return RS690_READ_MCIND(dev_priv, addr); 158 return RS690_READ_MCIND(dev_priv, addr);
159 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
160 return RS600_READ_MCIND(dev_priv, addr);
150 else 161 else
151 return RS480_READ_MCIND(dev_priv, addr); 162 return RS480_READ_MCIND(dev_priv, addr);
152} 163}
@@ -163,6 +174,8 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
163 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 174 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
164 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 175 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
165 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 176 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
177 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
178 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
166 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
167 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 180 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
168 else 181 else
@@ -180,6 +193,8 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
180 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 193 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
181 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 194 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
182 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 195 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
196 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
197 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
183 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 198 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
184 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 199 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
185 else 200 else
@@ -200,6 +215,8 @@ void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
200 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 215 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
201 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 216 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
202 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 217 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
218 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
219 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
203 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 220 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
204 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 221 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
205 else 222 else
@@ -224,6 +241,9 @@ void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
224 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 241 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
225 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); 242 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
226 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); 243 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
244 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
245 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
246 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
227 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { 247 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
228 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); 248 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
229 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); 249 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
@@ -494,6 +514,14 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
494 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 514 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
495 RS690_cp_microcode[i][0]); 515 RS690_cp_microcode[i][0]);
496 } 516 }
517 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
518 DRM_INFO("Loading RS600 Microcode\n");
519 for (i = 0; i < 256; i++) {
520 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
521 RS600_cp_microcode[i][1]);
522 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
523 RS600_cp_microcode[i][0]);
524 }
497 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || 525 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
498 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || 526 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
499 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || 527 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
@@ -899,6 +927,82 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
899 } 927 }
900} 928}
901 929
930/* Enable or disable IGP GART on the chip */
931static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
932{
933 u32 temp;
934 int i;
935
936 if (on) {
937 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
938 dev_priv->gart_vm_start,
939 (long)dev_priv->gart_info.bus_addr,
940 dev_priv->gart_size);
941
942 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
943 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
944
945 for (i = 0; i < 19; i++)
946 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
947 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
948 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
949 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
950 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
951 RS600_ENABLE_FRAGMENT_PROCESSING |
952 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
953
954 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
955 RS600_PAGE_TABLE_TYPE_FLAT));
956
957 /* disable all other contexts */
958 for (i = 1; i < 8; i++)
959 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
960
961 /* setup the page table aperture */
962 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
963 dev_priv->gart_info.bus_addr);
964 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
965 dev_priv->gart_vm_start);
966 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
967 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
968 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
969
970 /* setup the system aperture */
971 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
972 dev_priv->gart_vm_start);
973 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
974 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
975
976 /* enable page tables */
977 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
978 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
979
980 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
981 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
982
983 /* invalidate the cache */
984 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
985
986 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
987 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
988 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
989
990 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
991 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
992 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
993
994 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
995 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
996 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
997
998 } else {
999 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1000 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1001 temp &= ~RS600_ENABLE_PAGE_TABLES;
1002 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1003 }
1004}
1005
902static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) 1006static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
903{ 1007{
904 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); 1008 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
@@ -940,6 +1044,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
940 return; 1044 return;
941 } 1045 }
942 1046
1047 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1048 rs600_set_igpgart(dev_priv, on);
1049 return;
1050 }
1051
943 if (dev_priv->flags & RADEON_IS_PCIE) { 1052 if (dev_priv->flags & RADEON_IS_PCIE) {
944 radeon_set_pciegart(dev_priv, on); 1053 radeon_set_pciegart(dev_priv, on);
945 return; 1054 return;
@@ -1350,7 +1459,10 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1350 1459
1351 sctrl = RADEON_READ(RADEON_SURFACE_CNTL); 1460 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1352 RADEON_WRITE(RADEON_SURFACE_CNTL, 0); 1461 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1353 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info); 1462 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1463 ret = r600_page_table_init(dev);
1464 else
1465 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1354 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl); 1466 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1355 1467
1356 if (!ret) { 1468 if (!ret) {
@@ -1362,7 +1474,10 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1362 ret = radeon_setup_pcigart_surface(dev_priv); 1474 ret = radeon_setup_pcigart_surface(dev_priv);
1363 if (ret) { 1475 if (ret) {
1364 DRM_ERROR("failed to setup GART surface!\n"); 1476 DRM_ERROR("failed to setup GART surface!\n");
1365 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info); 1477 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1478 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1479 else
1480 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1366 radeon_do_cleanup_cp(dev); 1481 radeon_do_cleanup_cp(dev);
1367 return ret; 1482 return ret;
1368 } 1483 }
@@ -1415,8 +1530,12 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
1415 if (dev_priv->gart_info.bus_addr) { 1530 if (dev_priv->gart_info.bus_addr) {
1416 /* Turn off PCI GART */ 1531 /* Turn off PCI GART */
1417 radeon_set_pcigart(dev_priv, 0); 1532 radeon_set_pcigart(dev_priv, 0);
1418 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 1533 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1419 DRM_ERROR("failed to cleanup PCI GART!\n"); 1534 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1535 else {
1536 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1537 DRM_ERROR("failed to cleanup PCI GART!\n");
1538 }
1420 } 1539 }
1421 1540
1422 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) 1541 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)