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authorAlex Deucher <alexdeucher@gmail.com>2009-10-09 15:14:30 -0400
committerDave Airlie <airlied@redhat.com>2009-10-11 23:42:48 -0400
commitde2103e452ec7f2db5db7c44279735688608381d (patch)
tree10ccecbf806c916a774a486eb83c1b01520c607c /drivers/gpu/drm/radeon/radeon_combios.c
parent5a9bcacc0a56f0d9577494e834519480018a6cc3 (diff)
drm/radeon/kms: use drm_mode directly for panel modes
This reduces the number of mode format conversions needed and makes native panel mode support cleaner. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_combios.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c64
1 files changed, 31 insertions, 33 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 748265a105b3..e91aba8530b6 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -808,25 +808,25 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
808 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 808 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
809 809
810 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 810 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
811 lvds->native_mode.panel_yres = 811 lvds->native_mode.vdisplay =
812 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 812 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
813 RADEON_VERT_PANEL_SHIFT) + 1; 813 RADEON_VERT_PANEL_SHIFT) + 1;
814 else 814 else
815 lvds->native_mode.panel_yres = 815 lvds->native_mode.vdisplay =
816 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 816 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
817 817
818 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 818 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
819 lvds->native_mode.panel_xres = 819 lvds->native_mode.hdisplay =
820 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 820 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
821 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 821 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
822 else 822 else
823 lvds->native_mode.panel_xres = 823 lvds->native_mode.hdisplay =
824 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 824 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
825 825
826 if ((lvds->native_mode.panel_xres < 640) || 826 if ((lvds->native_mode.hdisplay < 640) ||
827 (lvds->native_mode.panel_yres < 480)) { 827 (lvds->native_mode.vdisplay < 480)) {
828 lvds->native_mode.panel_xres = 640; 828 lvds->native_mode.hdisplay = 640;
829 lvds->native_mode.panel_yres = 480; 829 lvds->native_mode.vdisplay = 480;
830 } 830 }
831 831
832 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 832 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
@@ -846,8 +846,8 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
846 lvds->panel_vcc_delay = 200; 846 lvds->panel_vcc_delay = 200;
847 847
848 DRM_INFO("Panel info derived from registers\n"); 848 DRM_INFO("Panel info derived from registers\n");
849 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres, 849 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
850 lvds->native_mode.panel_yres); 850 lvds->native_mode.vdisplay);
851 851
852 return lvds; 852 return lvds;
853} 853}
@@ -882,11 +882,11 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
882 882
883 DRM_INFO("Panel ID String: %s\n", stmp); 883 DRM_INFO("Panel ID String: %s\n", stmp);
884 884
885 lvds->native_mode.panel_xres = RBIOS16(lcd_info + 0x19); 885 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
886 lvds->native_mode.panel_yres = RBIOS16(lcd_info + 0x1b); 886 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
887 887
888 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres, 888 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
889 lvds->native_mode.panel_yres); 889 lvds->native_mode.vdisplay);
890 890
891 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 891 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
892 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0) 892 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
@@ -944,27 +944,25 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
944 if (tmp == 0) 944 if (tmp == 0)
945 break; 945 break;
946 946
947 if ((RBIOS16(tmp) == lvds->native_mode.panel_xres) && 947 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
948 (RBIOS16(tmp + 2) == 948 (RBIOS16(tmp + 2) ==
949 lvds->native_mode.panel_yres)) { 949 lvds->native_mode.vdisplay)) {
950 lvds->native_mode.hblank = 950 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
951 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 951 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
952 lvds->native_mode.hoverplus = 952 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
953 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 953 RBIOS16(tmp + 21)) * 8;
954 1) * 8; 954
955 lvds->native_mode.hsync_width = 955 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
956 RBIOS8(tmp + 23) * 8; 956 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
957 957 lvds->native_mode.vsync_end =
958 lvds->native_mode.vblank = (RBIOS16(tmp + 24) - 958 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
959 RBIOS16(tmp + 26)); 959 (RBIOS16(tmp + 28) & 0x7ff);
960 lvds->native_mode.voverplus = 960
961 ((RBIOS16(tmp + 28) & 0x7ff) - 961 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
962 RBIOS16(tmp + 26));
963 lvds->native_mode.vsync_width =
964 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
965 lvds->native_mode.dotclock =
966 RBIOS16(tmp + 9) * 10;
967 lvds->native_mode.flags = 0; 962 lvds->native_mode.flags = 0;
963 /* set crtc values */
964 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
965
968 } 966 }
969 } 967 }
970 } else { 968 } else {