drm/radeon/kms: fix divide by 0 in clocks code

If the chip isn't initialised properly this can happen.
also fix return value in combios clocks function.

Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index a81354167621..2c541e08f160 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -44,6 +44,10 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
 
         ref_div =
             RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
+
+        if (ref_div == 0)
+                return 0;
+
         sclk = fb_div / ref_div;
 
         post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
@@ -70,6 +74,10 @@ static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
 
         ref_div =
             RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
+
+        if (ref_div == 0)
+                return 0;
+
         mclk = fb_div / ref_div;
 
         post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;