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authorAlex Deucher <alexdeucher@gmail.com>2009-10-08 15:09:31 -0400
committerDave Airlie <airlied@redhat.com>2009-10-11 23:42:44 -0400
commit5a9bcacc0a56f0d9577494e834519480018a6cc3 (patch)
treef46fe410f8c875cf28d3905d23fdffcea4f374c0 /drivers/gpu/drm/radeon/radeon_atombios.c
parent2606c88608122339cbd5c6b5c149a2eb74ccfe9e (diff)
drm/radeon/kms/atom: rework crtc modeset
- clean up tv timing handling - unify SetCRTC_Timing and SetCRTC_UsingDTDTiming Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_atombios.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c93
1 files changed, 60 insertions, 33 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 5b6c08cee40e..979ddfdf209c 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -857,8 +857,7 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
857} 857}
858 858
859bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 859bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
860 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, 860 struct drm_display_mode *mode)
861 int32_t *pixel_clock)
862{ 861{
863 struct radeon_mode_info *mode_info = &rdev->mode_info; 862 struct radeon_mode_info *mode_info = &rdev->mode_info;
864 ATOM_ANALOG_TV_INFO *tv_info; 863 ATOM_ANALOG_TV_INFO *tv_info;
@@ -866,7 +865,7 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
866 ATOM_DTD_FORMAT *dtd_timings; 865 ATOM_DTD_FORMAT *dtd_timings;
867 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 866 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
868 u8 frev, crev; 867 u8 frev, crev;
869 uint16_t data_offset; 868 u16 data_offset, misc;
870 869
871 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); 870 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
872 871
@@ -876,28 +875,37 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
876 if (index > MAX_SUPPORTED_TV_TIMING) 875 if (index > MAX_SUPPORTED_TV_TIMING)
877 return false; 876 return false;
878 877
879 crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 878 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
880 crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 879 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
881 crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 880 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
882 crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 881 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
883 882 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
884 crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 883
885 crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 884 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
886 crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 885 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
887 crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 886 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
888 887 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
889 crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo; 888 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
890 889
891 crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight); 890 mode->flags = 0;
892 crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft); 891 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
893 crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom); 892 if (misc & ATOM_VSYNC_POLARITY)
894 crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop); 893 mode->flags |= DRM_MODE_FLAG_NVSYNC;
895 *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 894 if (misc & ATOM_HSYNC_POLARITY)
895 mode->flags |= DRM_MODE_FLAG_NHSYNC;
896 if (misc & ATOM_COMPOSITESYNC)
897 mode->flags |= DRM_MODE_FLAG_CSYNC;
898 if (misc & ATOM_INTERLACE)
899 mode->flags |= DRM_MODE_FLAG_INTERLACE;
900 if (misc & ATOM_DOUBLE_CLOCK_MODE)
901 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
902
903 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
896 904
897 if (index == 1) { 905 if (index == 1) {
898 /* PAL timings appear to have wrong values for totals */ 906 /* PAL timings appear to have wrong values for totals */
899 crtc_timing->usH_Total -= 1; 907 mode->crtc_htotal -= 1;
900 crtc_timing->usV_Total -= 1; 908 mode->crtc_vtotal -= 1;
901 } 909 }
902 break; 910 break;
903 case 2: 911 case 2:
@@ -906,17 +914,36 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
906 return false; 914 return false;
907 915
908 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 916 dtd_timings = &tv_info_v1_2->aModeTimings[index];
909 crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time); 917 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
910 crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive); 918 le16_to_cpu(dtd_timings->usHBlanking_Time);
911 crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset); 919 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
912 crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth); 920 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
913 crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time); 921 le16_to_cpu(dtd_timings->usHSyncOffset);
914 crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive); 922 mode->crtc_hsync_end = mode->crtc_hsync_start +
915 crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset); 923 le16_to_cpu(dtd_timings->usHSyncWidth);
916 crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth); 924
917 925 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
918 crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 926 le16_to_cpu(dtd_timings->usVBlanking_Time);
919 *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10; 927 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
928 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
929 le16_to_cpu(dtd_timings->usVSyncOffset);
930 mode->crtc_vsync_end = mode->crtc_vsync_start +
931 le16_to_cpu(dtd_timings->usVSyncWidth);
932
933 mode->flags = 0;
934 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
935 if (misc & ATOM_VSYNC_POLARITY)
936 mode->flags |= DRM_MODE_FLAG_NVSYNC;
937 if (misc & ATOM_HSYNC_POLARITY)
938 mode->flags |= DRM_MODE_FLAG_NHSYNC;
939 if (misc & ATOM_COMPOSITESYNC)
940 mode->flags |= DRM_MODE_FLAG_CSYNC;
941 if (misc & ATOM_INTERLACE)
942 mode->flags |= DRM_MODE_FLAG_INTERLACE;
943 if (misc & ATOM_DOUBLE_CLOCK_MODE)
944 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
945
946 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
920 break; 947 break;
921 } 948 }
922 return true; 949 return true;