drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5

NI chips no longer load the MC ucode in the asic_init sequence so
the asic comes up in a basic mode with low engine/memory clocks and
a voltage.  Once the MC ucode is loaded by the driver the card
can be programmed to it's proper default clocks and voltage.  As such
the default clocks in the firmware info table as the post clocks, not
the default running clocks.  Track the default post clocks and default
running clocks separately to handle this.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 16 insertions, 9 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 03f1c9a10ba4..1573202a6418 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2249,15 +2249,22 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde
                 rdev->pm.default_power_state_index = state_index;
                 rdev->pm.power_state[state_index].default_clock_mode =
                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
-                /* patch the table values with the default slck/mclk from firmware info */
-                for (j = 0; j < mode_index; j++) {
-                        rdev->pm.power_state[state_index].clock_info[j].mclk =
-                                rdev->clock.default_mclk;
-                        rdev->pm.power_state[state_index].clock_info[j].sclk =
-                                rdev->clock.default_sclk;
-                        if (vddc)
-                                rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
-                                        vddc;
+                if (ASIC_IS_DCE5(rdev)) {
+                        /* NI chips post without MC ucode, so default clocks are strobe mode only */
+                        rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
+                        rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
+                        rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
+                } else {
+                        /* patch the table values with the default slck/mclk from firmware info */
+                        for (j = 0; j < mode_index; j++) {
+                                rdev->pm.power_state[state_index].clock_info[j].mclk =
+                                        rdev->clock.default_mclk;
+                                rdev->pm.power_state[state_index].clock_info[j].sclk =
+                                        rdev->clock.default_sclk;
+                                if (vddc)
+                                        rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
+                                                vddc;
+                        }
                 }
         }
 }